Display panel and display device

Abstract

The utility model provides a display panel and a display device. The display panel comprises a gate layer, a semiconductor layer, a source and drain electrode layer, a pixel electrode layer, a contact layer and a common electrode layer. The gate layer is provided with a first surface and a second surface which are oppositely arranged; the semiconductor layer is arranged on the first surface; the source and drain electrode layer is arranged on one side, far away from the grid electrode layer, of the semiconductor layer; the pixel electrode layer is arranged on one side, far away from the semiconductor layer, of the source and drain electrode layer; the contact layer is arranged on one side, far away from the source and drain electrode layer, of the pixel electrode layer; the common electrode layer is arranged on one side, far away from the pixel electrode layer, of the contact layer; wherein the source and drain electrode layer is connected with the common electrode layer, and the pixel electrode layer is connected with the common electrode layer. Therefore, the coupling capacitance can be reduced, and the dual performance of touch control and display is improved.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a display panel and display device. Background Technology

[0002] Display panels are components in electronic devices used to display images and text, typically consisting of three main parts: display units, a glass substrate, and driving circuitry. Display panels are widely used in televisions, computer monitors, mobile phones, tablets, e-readers, automotive displays, and other fields. They are crucial infrastructure for daily life and the modern electronic information industry. With technological advancements, display panels are also being applied to emerging fields such as wearable devices, smart homes, and medical devices, driving the development of related industries.

[0003] TDDI (Touch and Display Driver Integration) technology is widely used in existing display panels. TDDI is a display technology that integrates touch and display together, that is, the common electrode is used for both touch and display, which improves the integration. However, the common electrode of the existing display panel is too close to the source and drain layers (such as metal data lines and metal touch lines). The metal capacitive coupling between the common electrode layer and the source and drain layers is large, which makes the touch effect worse.

[0004] Therefore, providing a display panel and display device that can improve the touch effect has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0005] This application provides a display panel and a display device.

[0006] This application provides a display panel including a gate layer, a semiconductor layer, a source / drain layer, a pixel electrode layer, a contact layer, and a common electrode layer. The gate layer has a first surface and a second surface disposed opposite to each other.

[0007] A semiconductor layer is disposed on the first surface; a source / drain layer is disposed on the side of the semiconductor layer away from the gate layer; a pixel electrode layer is disposed on the side of the source / drain layer away from the semiconductor layer; a contact layer is disposed on the side of the pixel electrode layer away from the source / drain layer; and a common electrode layer is disposed on the side of the contact layer away from the pixel electrode layer; wherein the source / drain layer is connected to the common electrode layer, and the pixel electrode layer is connected to the common electrode layer.

[0008] In some embodiments, a first insulating layer is provided between the source / drain layer and the pixel electrode layer, and a second insulating layer is provided between the pixel electrode layer and the contact layer.

[0009] In some embodiments, a first via and a second via are included. The first via passes through the contact layer and the first insulating layer and the second insulating layer. The second via passes through the contact layer and the second insulating layer. The source / drain layer and the common electrode layer are connected through the first via. The pixel electrode layer and the common electrode layer are connected through the second via.

[0010] In some embodiments, the semiconductor layer corresponds to the gate layer, and the semiconductor layer forms an amorphous silicon island.

[0011] In some embodiments, the gate layer and the source / drain layer form a pixel region.

[0012] In some embodiments, the pixel electrode layer is located within the pixel region.

[0013] In some embodiments, the common electrode layer has a hollowed-out area.

[0014] In some embodiments, an isolation layer is provided between the contact layer and the common electrode layer.

[0015] In some embodiments, the opening of the second via gradually decreases from the contact layer side toward the second insulating layer side.

[0016] Another embodiment of this application provides a display device, including the display panel described in the above embodiments.

[0017] One embodiment of the application provides a display panel, including a gate layer, a semiconductor layer, a source / drain layer, a pixel electrode layer, a contact layer, and a common electrode layer. The gate layer has a first surface and a second surface disposed opposite to each other.

[0018] A semiconductor layer is disposed on the first surface; a source / drain layer is disposed on the side of the semiconductor layer away from the gate layer; a pixel electrode layer is disposed on the side of the source / drain layer away from the semiconductor layer; a contact layer is disposed on the side of the pixel electrode layer away from the source / drain layer; and a common electrode layer is disposed on the side of the contact layer away from the pixel electrode layer. The source / drain layer is connected to the common electrode layer, and the pixel electrode layer is also connected to the common electrode layer. By first connecting the common electrode layer to the source / drain layer, and then connecting the common electrode layer to the pixel electrode layer, a conductive path is cleverly constructed from the source / drain layer to the pixel electrode layer, thus achieving an effective connection between the source / drain layer and the common electrode layer. This reduces coupling capacitance and improves both touch and display performance. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application.

[0021] Figure 2 This is another structural schematic diagram of the display panel provided in an embodiment of this application.

[0022] Figure 3 Another structural schematic diagram of the display panel provided in the embodiments of this application.

[0023] Figure 4 This is a schematic diagram of the display device structure provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0026] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0027] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0028] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0029] This application provides a display panel and a display device.

[0030] Please see Figure 1 and Figure 2This application provides a display panel including a gate layer 10, a semiconductor layer 20, a source / drain layer 30, a pixel electrode layer 40, a contact layer 50, and a common electrode layer 60. The gate layer 10 has a first surface 10a and a second surface 10b disposed opposite to each other; the semiconductor layer 20 is disposed on the first surface 10a; the source / drain layer 30 is disposed on the side of the semiconductor layer 20 away from the gate layer 10; the pixel electrode layer 40 is disposed on the side of the source / drain layer 30 away from the semiconductor layer 20; the contact layer 50 is disposed on the side of the pixel electrode layer 40 away from the source / drain layer 30; and the common electrode layer 60 is disposed on the side of the contact layer 50 away from the pixel electrode layer 40. The source / drain layer 30 is connected to the common electrode layer 60, and the pixel electrode layer 40 is connected to the common electrode layer 60.

[0031] In this embodiment, the first surface 10a is the upper surface of the gate layer 10, and the second surface 10b is the lower surface of the gate layer 10. Of course, the positions of the first surface 10a and the second surface 10b can be interchanged as needed. In this embodiment, unless otherwise specified, the first surface 10a is assumed to be the upper surface of the gate layer 10.

[0032] Among them, the gate layer 10, as a key component of the thin-film transistor (TFT) structure in the display panel, plays a core role in controlling the current flow. When the display panel is working, by applying a corresponding scanning signal to the gate layer 10, it is possible to determine whether the conductive channel of the semiconductor layer 20 is formed, thereby controlling whether the current can pass between the source and drain layers 30. This is the starting point for achieving precise pixel addressing and display control.

[0033] Semiconductor layer 20: Located on the first surface 10a of gate layer 10, it is the active region of the TFT. Its conductivity dynamically changes according to the voltage applied to gate layer 10. When the gate voltage reaches a specific threshold, a conductive channel is formed between the source and drain regions in semiconductor layer 20, allowing current to be conducted between source and drain layers 30, thereby realizing the transmission and control of electrical signals. Its carrier mobility and other characteristics affect the response speed and display performance of the TFT and the entire display panel.

[0034] The source-drain layer 30 is located on the side of the semiconductor layer 20 away from the gate layer 10, and mainly performs the function of conducting current. On the one hand, it receives electrical signals from external circuits (such as display driving circuits) after being controlled by the TFT, and on the other hand, it further transmits these signals. It plays a connecting role in the entire electrical signal chain of the display panel. In this structure, it is connected to the common electrode layer 60 and participates in subsequent display-related electrical processes.

[0035] The pixel electrode layer 40 is disposed on the side of the source / drain layer 30 away from the semiconductor layer 20, and is an important conductive layer that directly controls the pixel display state. In liquid crystal display (LCD) mode, the pixel electrode layer 40 works in conjunction with the common electrode layer 60 to change the alignment direction of liquid crystal molecules through the electric field generated between them, thereby controlling the transmission and blocking of light and achieving different display effects. In organic light-emitting diode (OLED) display mode, the pixel electrode layer 40 directly provides driving current to the organic light-emitting material, causing the pixel to emit light to present the corresponding image content.

[0036] The contact layer 50 is located on the side of the pixel electrode layer 40 away from the source / drain layer 30. Its main function is to optimize the contact between the pixel electrode layer 40 and the common electrode layer 60. Given the differences in surface properties and lattice structures of different materials, direct contact may cause problems such as high contact resistance. The contact layer 50 improves this contact with its suitable physical and chemical properties, ensuring a more stable and efficient electrical connection between the pixel electrode layer 40 and the common electrode layer 60, which helps to form a good electric field and facilitates the smooth transmission of electrical signals.

[0037] The common electrode layer 60 is located on the side of the contact layer 50 away from the pixel electrode layer 40. It works in conjunction with the pixel electrode layer 40 to complete the display function. It plays an indispensable role in both LCD and OLED display modes. Through reasonable electrical connection and electric field distribution with the pixel electrode layer 40, it precisely controls the display state of the pixels, ensuring that the entire display panel can present image information uniformly and accurately.

[0038] By first connecting the common electrode layer 60 to the source / drain layer 30, and then connecting the common electrode layer 60 to the pixel electrode layer 40, a conductive path is cleverly constructed from the source / drain layer 30 to the pixel electrode layer 40, thus achieving the effect of connecting the source / drain layer 30 to the pixel electrode layer 40. This is similar to connecting two originally unconnected endpoints with a wire in circuit construction, allowing electrical signals to be transmitted smoothly between them, laying the necessary electrical connection foundation for the subsequent implementation of display panel functions.

[0039] The common electrode layer 60 acts as a "bridge," closely connected to the source-drain layer 30, which forms the foundation of the pixel circuit's conductive components, receiving electrical signals from the source and drain. Simultaneously, it connects to the pixel electrode layer 40, which is closely related to pixel display control, further transmitting the received signals. From the perspective of the overall electrical structure of the display panel, this establishes an effective connection between conductive layers of different functional levels, making signal transmission within the entire display panel more coherent and smooth, ensuring that all components can work together to achieve functions such as image display.

[0040] By connecting the common electrode layer 60 to the source / drain layer 30 and the pixel electrode layer 40 respectively, the electric field distribution and interaction between the common electrode layer 60 and the metal source / drain layer 30 are altered. On one hand, this connection may reduce the relative effective area between the common electrode layer 60 and the source / drain layer 30 electrically (although the physical area may remain unchanged, from an electrical equivalence perspective, the connection method changes the effective range of their interaction). According to the capacitance calculation formula, the reduction in relative area helps to lower the coupling capacitance value. On the other hand, the connection may change the electric field line distribution between the two layers, making the electric field more concentrated in a specific area, reducing unnecessary electric field coupling, which also helps to reduce the coupling capacitance. The reduction in the coupling capacitance between the touch layer common electrode layer 60 and the metal source / drain layer 30 significantly improves the overall performance of the display panel. In terms of touch control, it improves the sensitivity and accuracy of touch operations. When users touch the screen, the device can more quickly and accurately identify the touch location and operation, reducing accidental triggers and providing a smoother and more comfortable touch experience. Regarding display functionality, it helps ensure the purity of the display signal, avoiding signal interference and distortion caused by coupling capacitors. This allows pixels to display according to accurate signal instructions, improving image clarity, color accuracy, and resulting in a higher quality visual effect for the display panel.

[0041] Overall, this method of establishing a connection through the common electrode layer 60 not only achieves an effective connection between the source / drain layer 30 and the pixel electrode layer 40, but also plays an important role in optimizing the electrical performance of the display panel. By reducing the coupling capacitance, it improves both touch and display performance, which is of positive and crucial significance for enhancing the user experience and functional performance of the entire display panel in practical applications.

[0042] Furthermore, this application also proposes that a first insulating layer 70 is provided between the source / drain layer 30 and the pixel electrode layer 40, and a second insulating layer 80 is provided between the pixel electrode layer 40 and the common electrode layer 60.

[0043] In existing display panels, the common electrode layer 60 and the source / drain layer 30 are too close, resulting in large capacitive coupling and affecting touch performance. To address this issue, this application proposes a technical solution that involves placing a first insulating layer 70 between the source / drain layer 30 and the pixel electrode layer 40, and a second insulating layer 80 between the pixel electrode layer 40 and the common electrode layer 60. By adding insulating layers between these layers, capacitive coupling can be effectively reduced, improving touch performance.

[0044] Specifically, the first insulating layer 70 can be made of materials such as silicon oxide and silicon nitride, which have good insulation properties and stability. The second insulating layer 80 can be made of the same or similar materials to ensure the insulation effect and stability of the entire structure. In this way, the capacitive coupling between the source / drain layer 30 and the pixel electrode layer 40, and between the pixel electrode layer 40 and the common electrode layer 60, is effectively reduced, thereby improving the touch performance of the display panel.

[0045] In one preferred embodiment, the thicknesses of the first insulating layer 70 and the second insulating layer 80 can be adjusted according to actual needs to achieve optimal insulation and touch performance. For example, the degree of capacitive coupling can be optimized by adjusting the thickness of the insulating layers, thereby further improving the touch performance of the display panel.

[0046] Therefore, by providing a first insulating layer 70 between the source / drain layer 30 and the pixel electrode layer 40, and a second insulating layer 80 between the pixel electrode layer 40 and the common electrode layer 60, this application solves the problem of large capacitive coupling in the prior art and significantly improves the touch performance of the display panel.

[0047] Furthermore, this application proposes a first via 101 and a second via 102, wherein the first via 101 passes through the contact layer 50 and the first insulating layer 70 and the second insulating layer 80, and the second via 102 passes through the contact layer 50 and the second insulating layer. The source / drain layer 30 and the common electrode layer 60 are connected through the first via 101, and the pixel electrode layer 40 and the common electrode layer 60 are connected through the second via 102. In existing display panels, the distance between the common electrode layer 60 and the source / drain layer 30 is relatively short, which easily leads to large capacitive coupling and a deterioration in touch performance. This application effectively increases the distance between the common electrode layer 60 and the source / drain layer 30 by setting the first insulating layer 70 between the source / drain layer 30 and the pixel electrode layer 40, and by setting the second insulating layer 80 between the pixel electrode layer 40 and the common electrode layer 60, thereby reducing capacitive coupling. The source / drain layer 30 is connected to the common electrode layer 60 through a first via 101, and the pixel electrode layer 40 is connected to the common electrode layer 60 through a second via 102, further improving the touch performance. Specifically, the first insulating layer 70 can be made of silicon oxide, with a thickness ranging from 100nm to 300nm. The second insulating layer 80 can also be made of silicon oxide, with a thickness ranging from 100nm to 300nm. The diameters of the first via 101 and the second via 102 can be designed according to actual needs, typically between 1μm and 10μm. The contact layer 50 can be made of a transparent conductive material, such as ITO (indium tin oxide) or IZO (indium zinc oxide), to ensure good electrical and optical performance. Thus, through the above structural design, this application effectively solves the capacitive coupling problem caused by the close proximity of the common electrode layer 60 and the source / drain layer 30 in the prior art, thereby significantly improving the touch performance. Compared with existing technologies, the display panel of this application has significant advantages in touch accuracy and response speed, and can better meet the needs of electronic devices for high-performance display and touch functions.

[0048] Furthermore, the semiconductor layer 20 corresponds to the gate layer 10, and the semiconductor layer 20 forms amorphous silicon islands. The formation of amorphous silicon islands can effectively improve the performance of the semiconductor layer 20, enhancing the display effect and touch sensitivity of the display panel. Amorphous silicon islands can be formed using conventional semiconductor manufacturing processes, such as photolithography and etching techniques, to process amorphous silicon material into island-like structures. This structural design can further optimize the performance of the display panel and improve the user experience. Therefore, this application, by introducing a design in which the semiconductor layer 20 corresponds to the gate layer 10 and forms amorphous silicon islands in the display panel, effectively solves the problem of poor touch performance in the prior art. Compared with the prior art, the display panel structure of this application improves the touch effect while maintaining good display performance, demonstrating significant technical advantages.

[0049] Furthermore, the gate layer 10 and the source / drain layer 30 form a pixel region 103.

[0050] To improve touch performance, the gate layer 10 and the source / drain layer 30 form a pixel region 103. This structural design effectively reduces the capacitive coupling between the common electrode layer 60 and the source / drain layer 30, thereby improving touch performance. Specifically, the pixel region 103 formed by the gate layer 10 and the source / drain layer 30 can be implemented in various ways. For example, the gate layer 10 can be made using different materials and processes to ensure a stable pixel region 103 is formed between it and the source / drain layer 30. Furthermore, the performance of the pixel region 103 can be further optimized by adjusting the layout and size of the gate layer 10 and the source / drain layer 30. Therefore, by introducing the design of the gate layer 10 and the source / drain layer 30 forming a pixel region 103 in the display panel, this application effectively improves the touch performance of the display panel and solves the problem of large metal capacitive coupling between the common electrode layer 60 and the source / drain layer 30 in the prior art.

[0051] Furthermore, the pixel electrode layer 40 is located within the pixel region 103.

[0052] The pixel electrode layer 40 is located within the pixel region 103, forming a complete display structure together with other layers such as the source / drain layer 30 and the common electrode layer 60. The pixel electrode layer 40 ensures optimal display performance within the pixel region 103, thereby enhancing the overall performance of the display panel. The pixel electrode layer 40 can be made from various materials, such as transparent conductive materials like indium tin oxide (ITO). The fabrication process for the pixel electrode layer 40 can include conventional processes such as sputtering and vapor deposition. By optimizing the materials and processes of the pixel electrode layer 40, the display effect and touch performance of the display panel can be further improved.

[0053] Furthermore, the common electrode layer 60 is provided with a hollow area.

[0054] This application improves touch performance by creating a hollowed-out area on the common electrode layer 60, effectively reducing capacitive coupling between the common electrode layer 60 and the source / drain layer 30. Compared with existing technologies, the display panel structure of this application is more optimized, better meeting the demands of modern electronic devices for high-performance display and touch.

[0055] Please see Figure 3 In some embodiments, an isolation layer 90 is provided between the contact layer 50 and the common electrode layer 60.

[0056] The isolation layer 90 can be implemented in various ways. For example, a dielectric material can be used as the isolation layer 90 to reduce capacitive coupling. The thickness and material selection of the isolation layer 90 can be adjusted according to specific application requirements to achieve the best touch performance. In addition, the isolation layer 90 can also be designed with a specific shape and structure to further optimize the touch performance of the display panel.

[0057] In some embodiments, the opening of the second via 102 gradually decreases from the contact layer 50 side toward the second insulating layer 80 side.

[0058] Please see Figure 4 Another embodiment of this application also provides a display device 1000, including the display panel 100 described in the above embodiments. Since the display panel 100 has been described in detail in the above embodiments, the display panel 100 in this application will not be described in detail again.

[0059] The display panel and display device provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: A gate layer having a first surface and a second surface disposed opposite to each other; A semiconductor layer is disposed on the first surface; The source and drain layers are disposed on the side of the semiconductor layer away from the gate layer; A pixel electrode layer is disposed on the side of the source / drain layer away from the semiconductor layer; A contact layer is disposed on the side of the pixel electrode layer away from the source / drain layer; A common electrode layer is disposed on the side of the contact layer away from the pixel electrode layer; The source / drain layer is connected to the common electrode layer, and the pixel electrode layer is connected to the common electrode layer.

2. The display panel according to claim 1, characterized in that, A first insulating layer is provided between the source / drain layer and the pixel electrode layer, and a second insulating layer is provided between the pixel electrode layer and the contact layer.

3. The display panel according to claim 2, characterized in that, It includes a first via and a second via. The first via passes through the contact layer and the first insulating layer and the second insulating layer. The second via passes through the contact layer and the second insulating layer. The source and drain layers are connected to the common electrode layer through the first via. The pixel electrode layer is connected to the common electrode layer through the second via.

4. The display panel according to claim 1, characterized in that, The semiconductor layer corresponds to the gate layer, and the semiconductor layer forms amorphous silicon islands.

5. The display panel according to claim 1, characterized in that, The gate layer and the source / drain layer form a pixel region.

6. The display panel according to claim 5, characterized in that, The pixel electrode layer is located within the pixel region.

7. The display panel according to claim 1, characterized in that, The common electrode layer has a hollowed-out area.

8. The display panel according to claim 1, characterized in that, An isolation layer is provided between the contact layer and the common electrode layer.

9. The display panel according to claim 3, characterized in that, The opening of the second via gradually decreases from the contact layer side to the second insulating layer side.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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