LVDS communication board of 3U CPCI architecture

Abstract

The utility model relates to an LVDS (Low Voltage Differential Signaling) communication board of a 3U CPCI (Compact Peripheral Component Interconnect) architecture, which adopts the 3U CPCI architecture, takes an ARM (Advanced RISC Machines) and an FPGA (Field Programmable Gate Array) as a core, and provides 80 TTL (Transistor-Transistor Logic) level input and output functions, one RS232 debugging serial port and 16 LVDS interface communication functions which can be selected. The FPGA and the ARM both support a reconfigurable design. The LVDS communication board of the 3U CPCI architecture developed by the utility model can be conveniently applied to data transceiving and information processing functions.

Description

TECHNICAL FIELD

[0001] The utility model relates to 3U CPCI architecture's information communication field, concretely relates to a 3U CPCI architecture's LVDS communication board. BACKGROUND

[0002] ARM+FPGA processing system is widely applied to complex information communication field, and the agility of FPGA is strong, and the powerful parallel processing capability can guarantee the timeliness of data processing.The specialty of ARM is transaction management function, and can realize multi-task real-time processing without affecting each other with the cooperation of system controller. ARM+FPGA processing system has the advantages of FPGA and ARM simultaneously, and has the digital information communication function and transaction management function, supports higher computing processing capability and better compatible capability, and has flexible system reconfiguration scheme. However, the 3U CPCI architecture LVDS communication board with ARM+FPGA as the core does not exist in the prior art. SUMMARY

[0003] In order to solve the above technical problems, the utility model discloses a 3U CPCI architecture LVDS communication board, which comprises an FPGA and an ARM chip, connects an LVDS subboard and a TTL subcard through an inter-board connector, sets a plurality of TTL information communication interfaces and a plurality of LVDS communication interfaces outside, interconnects the FPGA and the ARM chip through an FMC bus interface, and mounts an SPI FLASH chip and an EEPROM chip on the FPGA.

[0004] Beneficial effects:

[0005] The 3U CPCI architecture LVDS communication board developed by the utility model can be applied to data acquisition, data transmission and information processing. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 The utility model discloses a 3U CPCI architecture LVDS communication board hardware component block diagram;

[0007] Figure 2 The utility model discloses a 3U CPCI architecture LVDS communication board hardware component block diagram; DETAILED DESCRIPTION

[0008] The technical scheme in the embodiments of the utility model will be described clearly and completely in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only a part of the embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the utility model.

[0009] According to the embodiment, the utility model discloses a 3U CPCI frame's LVDS communication board, Figure 1 It includes two core parts of FPGA and ARM on the LVDS communication board, can select and plug LVDS daughter card or TTL daughter card through the interboard connector, realizes 80 way TTL information communication and 16 way LVDS interface communication function, realizes the collection function of external signal. The LVDS communication board of ARM+FPGA frame developed through the utility model can be conveniently used when needing data collection, information processing function.

[0010] The interface connection of the FPGA chip is as shown in Figure 1 The configuration mode of FPGA selects QSPI mode. The reconfiguration function of FPGA program is that STM32F429 is connected with FPGA through FMC bus, realizes the reconfiguration function of XC7A200T program. FPGA chip is mainly used for the processing and transmission of TTL signal and the communication of LVDS interface. FPGA and ARM are interconnected through FMC bus interface to realize the data transmission between FPGA and ARM. FPGA mounts a SPI FLASH chip for storing user program. FPGA mounts an EEPROM chip for storing board card information. In the design, FPGA provides 80 way configurable TTL information communication path, and the conversion of TTL signal and TTL / LVCOMS signal is carried out through level conversion chip. In the design, different subcards can be adapted through the board connector to realize LVDS communication or TTL information communication function.

[0011] If LVDS subcard is selected, FPGA expands 16 way LVDS bus interface.

[0012] If TTL subcard is selected, FPGA expands 120 way TTL signal, and the interface increases static protection, and is suitable for various application occasions.

[0013] The ARM chip adopts STM32F429ZIT6 (hereinafter referred to as: STM32F429) of ST company. The chip is based on the high-performance ARM Cortex-M4 32-bit RISC core, and the working frequency is as high as 180MHz. The Cortex-M4 core has a single-precision floating point unit (FPU), and supports single-precision data processing instructions and data types. The chip has the characteristics of high performance, low power consumption and high reliability. STM32F429 outputs a way RS232 serial port to the front panel, and MAX3232ESE of MAXIM is selected in the design, and the transmission rate is 120kbps, and is used for realizing debugging and communication function, and the serial port can be reconfigured.

[0014] The FPGA chip uses Xilinx's Aertix-7 series FPGA, specifically XC7A200T-2FBG676I (hereinafter referred to as: XC7A200T). XC7A200T is mainly used for information processing of TTL signals and data transmission of LVDS interface. The chip is developed based on high-performance, low-power 28nm, HKMG process, and has the advantages of high performance, low power consumption, high capacity and strong design portability. The collected or processed data can be quickly communicated with ARM, or data exchange can be performed with other boards through the LVDS interface. The configuration mode of the FPGA is selected as QSPI mode, and Micron's MT25QL256ABA8ESF-0SIT series FLASH is selected. The capacity is 256Mb, and X4 operation is supported. XC7A200T is connected to the CPCI backplane connector through the level conversion chip SN74CBTD16210 after signal conversion, and the information of the board is reported to the host system through the bus. XC7A200T is externally connected with an EEPROM for storing related management information.

[0015] The TTL level conversion chip selects TI's SN74ALVC164245 chip. SN74ALVC164245 is a typical tri-state level conversion driver chip with tri-state output function, realizing bidirectional 16-bit data transmission and level conversion function. In this design, five single cards are selected and connected to the FPGA to realize 80-way TTL information communication.

[0016] As Figure 2As shown, the LVDS chip adopts TI's DS91C176TMA (hereinafter referred to as: DS91C176). LVDS is an improved LVDS, and the traditional LVDS can only support point-to-point connection, and the LVDS can not only support point-to-point application, but also can support bus type multi-point to multi-point connection. The chip can convert the received TTL / LVCOMS signal into a full differential LVDS signal output, and can also convert the received LVDS signal into an LVCOMS signal output, and the receiving end has a fault protection function, and can be applied to point-to-point communication occasions with urgent needs of low power consumption, high data transmission rate and anti-interference capability. The chip can be configured to receive or transmit through software, and the design realizes data communication by extending 16-way LVDS interface through XC7A200T. The J30J-144ZKW-JY connector is connected with the SN74ALVC164245 chip and the MAX3232ESE chip, and transmits TTL signals outward, and when transmitting LVDS signals, the high-density, high-communication-rate and domestically-produced 12226-5150-00FR type connector is used for the external connector, and the transmission rate can exceed 200Mbps, and the 16-channel LVDS signals can be interacted with the external connection through two connectors. The J30J-144ZKW-JY connector is used for transmitting TTL signals, and the TTL level signal is a +5V / 0V level signal, and the transmission signal quality is high, and the J30J-144ZKW-JY connector can meet the requirements of most TTL signal transmission.

[0017] 40MHz crystal oscillator is connected with the XC7A200T. The 40MHz crystal oscillator provides a stable clock signal in the XC7A200T, and ensures the synchronization and correctness of various operations and data transmission in the XC7A200T. The frequency of the 40MHz crystal oscillator is typical, and the clock divider in the XC7A200T can provide common clocks for LVDS and TTL signals, and ensure the accuracy and applicability of the signal frequency. The common frequencies of 10MHz, 100MHz and 200MHz can be provided for the LVDS signal.

[0018] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but it should be understood that the above description is only exemplary. Those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. The protection scope of the present application is defined by the appended claims.

Claims

1. An LVDS communication board with a 3U CPCI architecture, characterized in that: The FPGA and ARM chip are connected with LVDS subboard and TTL subcard through inter-board connector, and are provided with several TTL information communication interfaces and several LVDS communication interfaces; the FPGA and ARM chip are interconnected through FMC bus interface; the FPGA is mounted with SPI FLASH chip and EEPROM chip.

2. The LVDS communication board of 3U CPCI architecture according to claim 1, wherein: The FPGA chip uses Xilinx Aertix-7 series FPGA, model XC7A200T-2FBG676I, the FPGA chip adopts QSPI configuration mode, the SPIFLASH chip selects Micron MT25QL256ABA8ESF-0SIT series FLASH, and the FPGA chip is connected to the CPCI backplane connector after signal conversion through a level conversion chip SN74CBTD16210. ​ 3. The LVDS communication board of 3U CPCI architecture according to claim 2, characterized in that: The ARM chip adopts ST STM32F429ZIT6, the ARM chip outputs RS232 serial port to the front panel, selects MAXIM MAX3232ESE as the RS232 serial port chip, and the transmission rate is 120 kbps.

4. The LVDS communication board of 3U CPCI architecture according to claim 3, characterized in that: The level conversion chip of TTL information communication interface selects TI SN74ALVC164245 chip, the TTL subcard is five, and is connected to the FPGA to realize 80 TTL information communication ports.

5. The LVDS communication board of 3U CPCI architecture according to claim 4, characterized in that: The LVDS subboard is connected with the inter-board connector through an LVDS chip, the inter-board connector is connected with the FPGA chip, and the LVDS chip adopts TI DS91C176TMA.

6. The LVDS communication board of 3U CPCI architecture according to claim 4, characterized in that: The J30J-144ZKW-JY connector is connected with the SN74ALVC164245 chip and the MAX3232ESE chip to transmit TTL signals outward.

7. The LVDS communication board of 3U CPCI architecture according to claim 3, characterized in that: The 40MHz crystal oscillator is connected with the XC7A200T.

8. The LVDS communication board of 3U CPCI architecture according to claim 1, wherein: The number of SPI FLASH chips is one.

9. The LVDS communication board of 3U CPCI architecture according to claim 1, characterized in that: The number of EEPROM chips is one.

10. The LVDS communication board of 3U CPCI architecture according to claim 1, wherein: The number of LVDS communication interfaces is 16. ​

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