Intelligent fusion terminal SPI (Serial Peripheral Interface) communication interface circuit for preventing backward flowing of peripherals

Abstract

The utility model discloses an intelligent fusion terminal SPI (Serial Peripheral Interface) communication interface circuit for preventing backward flowing of peripherals, which is integrated with a peripheral SPI interface and a main control unit which are arranged on an intelligent fusion terminal, the peripheral SPI interface is used for electrically connecting external SPI slave equipment, and the peripheral SPI interface is bidirectionally and electrically connected with the main control unit; the peripheral SPI comprises an output clock circuit, a main equipment output circuit, a main equipment input circuit and a chip selection circuit, and a first protection module is arranged between the output clock circuit and the main equipment output circuit; a second protection module is arranged on the main equipment input circuit; and a third protection module is arranged on the chip selection circuit. According to the utility model, the directions and risks of all signal lines of the peripheral SPI interface are distinguished, and different protection strategies are adopted, so that the requirement of high-rate communication of the conventional SPI interface in the prior art is better met.

Description

TECHNICAL FIELD

[0001] The utility model relates to interface circuit technical field, concretely relates to a prevent external device backflow intelligent fusion terminal SPI communication interface circuit. BACKGROUND

[0002] SPI is the key communication bus that intelligent fusion terminal and external function module (such as ESAM safety module, measurement chip, extended communication module etc.) carry out high-speed data interaction, and the intelligent fusion terminal is as SPI host equipment, needs to provide SPI clock, host output slave input data line and slice selection signal, and receives the data returned from slave equipment.

[0003] In actual engineering application, the following risks exist: external module can be powered by independent power supply, if its power on time sequence is abnormal or breaks down, can lead to its IO port voltage higher than the IO voltage of terminal host chip, thereby through MISO etc. Signal line pours into current to terminal, damages the input buffer of host chip. When plugging in the SPI module, instantaneous short circuit or voltage peak can be generated between the connector pins, and the host chip is impacted through SCLK, MOSI, CS etc. Peripheral short circuit fault: internal short circuit of peripheral module can pull signal line to power supply or ground, and the continuous large current backflow leads to peripheral short circuit fault. The general solution only connects TVS tube in parallel in the interface and carries out electrostatic protection, and the continuous power backflow and signal line reverse current protection are insufficient.

[0004] Therefore, an intelligent fusion terminal SPI communication interface circuit for preventing external device backflow, which can effectively block abnormal current and does not affect the normal communication performance of SPI, becomes a further improvement direction. UTILITY MODEL CONTENTS

[0005] To solve the above technical problems, the utility model provides an intelligent fusion terminal SPI communication interface circuit for preventing external device backflow, which includes external SPI interface and host control unit arranged integrally on the intelligent fusion terminal, the external SPI interface is used for electrically connecting external SPI slave equipment, and the external SPI interface is bidirectionally electrically connected with the host control unit, the external SPI interface includes output clock circuit, host equipment output circuit, host equipment input circuit and slice selection circuit, and the first protection module is arranged between the output clock circuit and the host equipment output circuit, the second protection module is arranged on the host equipment input circuit, and the third protection module is arranged on the slice selection circuit.

[0006] Preferably, the first protection module comprises a current-limiting resistor R1, a current-limiting resistor R12, a clamping diode V3, a clamping diode V4, a unidirectional isolation diode D1 and a unidirectional isolation diode D4, the unidirectional isolation diode D4 and the current-limiting resistor R12 are connected in series at the output end of the output clock circuit, the unidirectional isolation diode D1 and the current-limiting resistor R1 are connected in series at the output end of the master device output circuit, the cathodes of the clamping diode V3 and the clamping diode V4 are connected in parallel between the unidirectional isolation diode D4 and the current-limiting resistor R12, the unidirectional isolation diode D1 and the current-limiting resistor R1, and the anodes of the clamping diode V3 and the clamping diode V4 are grounded, for clamping the negative voltage of the output clock circuit and the master device output circuit to the vicinity of the ground level.

[0007] Preferably, the second protection module comprises a current-limiting resistor R4 and a Schottky diode D2, the Schottky diode D2 and the current-limiting resistor R4 are connected in series at the output end of the master device output circuit, the anode of the Schottky diode D2 is connected with the MISO pin of the peripheral SPI interface, and the cathode of the Schottky diode D2 is connected with the MISO input pin of the master control unit.

[0008] Preferably, the third protection module comprises a pull-down resistor R3 and a transient voltage suppression diode D3, the pull-down resistor R3 and the transient voltage suppression diode D3 are connected in parallel at the chip select circuit, one end of the pull-down resistor R3 is connected with the chip select circuit, and the other end is grounded, one end of the transient voltage suppression diode D3 is connected with the chip select circuit, and the other end is grounded, and the transient voltage suppression diode D3 is used for clamping an abnormal high voltage spike at the chip select circuit to a safe voltage.

[0009] Preferably, the chip select circuit is bidirectionally connected with the GPIO of the master control unit, and the on-resistance of the output stage of the GPIO of the master control unit is smaller than the resistance value of the pull-down resistor R3.

[0010] Preferably, the resistance value of the current-limiting resistor R1 and the current-limiting resistor R12 is 10-100 ohms.

[0011] Compared with the prior art, the utility model has the following beneficial effects:

[0012] (1) The utility model discloses an external device SPI interface and master control unit are arranged on the intelligent fusion terminal, and the external device SPI interface is used for electric connection external SPI slave equipment, and the external device SPI interface is bidirectionally electrically connected with the master control unit, the external device SPI interface includes output clock circuit, master device output circuit, master device input circuit and slice selection circuit, and the first protection module is arranged between output clock circuit and master device output circuit, the second protection module is arranged on master device input circuit, and the third protection module is arranged on slice selection circuit, the utility model distinguishes the direction of each signal line of external device SPI interface and risk, adopts different protection strategy, especially one -way conduction circuit is designed to master device input circuit, and the power reverse flow problem is solved fundamentally. BRIEF DESCRIPTION OF DRAWINGS

[0013] Fig. 1 It is flow chart of the utility model.

[0014] Fig. 2 It is circuit diagram of output clock circuit and master device output circuit of the utility model.

[0015] Fig. 3 It is circuit diagram of master device input circuit of the utility model.

[0016] Fig. 4 It is circuit diagram of slice selection circuit of the utility model. DETAILED DESCRIPTION

[0017] The utility model will be further described below in combination with the drawings and specific embodiment.

[0018] In the description of the utility model, unless otherwise specified, the meaning of "multiple" is two or more than two;The orientation or position relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", "front end", "rear end", "head", "tail" and the like are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the utility model and simplifying the description, and cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, a particular orientation and operation, therefore, cannot be understood as limiting the utility model. In addition, the terms "first", "second", "third" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0019] In the description of the utility model, it is to explain that, unless there is definite stipulation and limitation, the term "connects", "connects" should be broad sense understanding, for example, can be fixed connection, also can be detachable connection, or integrally connects, can be mechanical connection, also can be electrical connection, can be direct connection, also can indirectly connect through intermediate medium.

[0020] As Figs. 1 to 4 The utility model discloses a prevent external device SPI communication interface circuit of backflow of intelligence fusion terminal, including integrated setting on the external SPI interface and host computer unit of intelligence fusion terminal, the intelligence fusion terminal of this embodiment is the device that can be bought by oneself commonly on the market, the structure and control module of intelligence fusion terminal are not improved by the utility model, therefore do not expand the description in detail.

[0021] The external SPI interface is used for electrically connecting external SPI slave device, the external SPI interface is bidirectionally electrically connected with the host computer unit, the pin definition of the external SPI interface meets the SPI communication extension interface specification, and the working voltage of the external SPI interface is 3.3V level;The selection voltage parameter of the Schottky diode D2, the Schottky diode D5 and the transient voltage suppression diode D3 is matched with 3.3V logic level;The external SPI interface includes output clock circuit, master device output circuit, master device input circuit and chip selection circuit,

[0022] The first protection module is arranged between the output clock circuit and the master device output circuit, the first protection module includes current-limiting resistor R1, current-limiting resistor R12, clamping diode V3, clamping diode V4, unidirectional isolation diode D1 and unidirectional isolation diode D4, the unidirectional isolation diode D4 and the current-limiting resistor R12 are connected in series on the uplink output end of the output clock circuit, the unidirectional isolation diode D1 and the current-limiting resistor R1 are connected in series on the uplink output end of the master device output circuit, the unidirectional isolation diode D4 and the current-limiting resistor R12, the unidirectional isolation diode D1 and the current-limiting resistor R1 are connected in parallel with the cathodes of the clamping diode V3 and the clamping diode V4, the anodes of the clamping diode V3 and the clamping diode V4 are grounded, and the negative voltage of the output clock circuit and the master device output circuit is clamped to the ground level, the resistance value of the current-limiting resistor R1 and the current-limiting resistor R12 is 10 ohms to 100 ohms.

[0023] The output clock circuit and the master device output circuit are actively driven by the master control unit, and the direction is fixed as output. The main risks are overcurrent caused by short circuit of the peripheral device and hot plug spike. Therefore, a current limiting resistor R1 and a current limiting resistor R12 are connected in series on the output clock circuit and the master device output circuit to limit the maximum output current. At the same time, a clamping diode V3 and a clamping diode V4 are connected in parallel between the output clock circuit and the master device output circuit and the ground, and the cathode is connected to the signal line. When the peripheral SPI interface abnormally pulls the signal line to negative voltage, the clamping diode V3 and the clamping diode V4 are turned on to clamp, protecting the output stage of the master control unit. The filter capacitor C6 and the filter capacitor C7 filter the signal, the pull-up resistor R14, the pull-up resistor R5, the pull-up resistor R7 and the pull-up resistor R8 ensure that the signal is high by default, and the unidirectional isolation diode D1 and the unidirectional isolation diode D4 prevent the signal from flowing back to the master control unit.

[0024] The second protection module is arranged on the master device input circuit, and the second protection module includes a current limiting resistor R4 and a Schottky diode D2. The Schottky diode D2 and the current limiting resistor R4 are connected in series along the output end of the master device output circuit. The anode of the Schottky diode D2 is connected to the MISO pin of the peripheral SPI interface, and the cathode is connected to the MISO input pin of the master control unit.

[0025] The second protection module is configured to allow current to flow from the peripheral SPI interface to the master control unit and block reverse current. The anode of the Schottky diode D2 is connected to the MISO pin of the peripheral SPI interface, and the cathode is connected to the MISO input pin of the master control unit. The master device input circuit is the path with the highest risk of backflow, so the embodiment connects a current limiting resistor R4 and a Schottky diode D2 in series on the master device input circuit. The anode of the Schottky diode D2 faces the peripheral SPI interface, and the cathode faces the master control unit input. During normal communication, the high level (such as 3.3V) output by the peripheral SPI interface can smoothly pass through the Schottky diode D2 (only about 0.3V voltage drop) to reach the master control unit. If the peripheral SPI interface has a fault voltage higher than the terminal power supply voltage, the Schottky diode D2 is in reverse bias or zero bias because the cathode potential is lower than the anode, effectively blocking the current from flowing into the master control unit.

[0026] The chip selection circuit is provided with a third protection module, the chip selection circuit is controlled by the GPIO of the main control unit, the GPIO of the main control unit is configured as a push-pull output mode, the resistance value of the pull-down resistor R3 is much larger than the on-resistance of the GPIO output stage, so as to ensure that the chip selection circuit can be effectively driven to be high when the GPIO outputs a high level, and the chip selection circuit can be reliably pulled down when the GPIO outputs a high resistance or a low level. One end of the pull-down resistor is connected to the chip selection circuit, and the other end is grounded; the transient voltage suppression diode D3 is connected in parallel between the chip selection circuit and the ground, for clamping the abnormal high voltage peak on the chip selection circuit to a safe voltage. The third protection module includes the pull-down resistor R3 and the transient voltage suppression diode D3, the pull-down resistor R3 and the transient voltage suppression diode D3 are connected in parallel on the chip selection circuit, one end of the pull-down resistor R3 is connected to the chip selection circuit, and the other end is grounded, one end of the transient voltage suppression diode D3 is connected to the chip selection circuit, and the other end is grounded, and the transient voltage suppression diode D3 is used for clamping the abnormal high voltage peak on the chip selection circuit to a safe voltage. The chip selection circuit is bidirectionally electrically connected with the GPIO of the main control unit, and the on-resistance of the GPIO output stage of the main control unit is smaller than the resistance value of the pull-down resistor R3.

[0027] The chip selection circuit is an output, but the normal state should be a high level invalid. The embodiment adopts the design of "active pull-down + transient suppression", a current-limiting resistor R2 is connected in series between the interface between the GPIO output pin and the chip selection circuit, and the Schottky diode D5 prevents signal backflow to the main control unit. On the interface side of the chip selection circuit, the chip selection circuit is pulled down by a pull-down resistor R3 by default, so as to prevent the state uncertainty during power-on initialization or when the GPIO is configured as a high resistance. At the same time, the transient voltage suppression diode D3 absorbs high-voltage static electricity or surges.

[0028] The working principle of the utility model is:

[0029] When the normal external SPI slave device is connected, the communication current flows smoothly, the sum of the diode voltage drop and the resistance voltage drop is much smaller than the logic level noise tolerance, and the communication is normal. Assuming that the peripheral module fails and the VCC is abnormally raised to 5V, and the MISO pin is internally pulled up. At this time, the terminal main control VCC is 3.3V. The MISO (~5V) of the fault module tries to pour current into the terminal through the anode of D2. Since the cathode potential of D2 is maintained at not higher than 3.3V by the internal circuit of the terminal, D2 is in a reverse blocking state, successfully blocking the current, and protecting the MISO input pin of the main control.

[0030] The utility model discloses a unidirectional conduction isolation circuit is connected in series on the peripheral SPI interface of intelligent fusion terminal, and the level clamping and bleeding circuit is integrated on the chip selection circuit, and the unidirectional conduction isolation circuit is constituted by Schottky diode D2 and current -limiting resistance R4, ensures the drive current of signal from the terminal to the peripheral smooth passing, simultaneously blocks the abnormal current or voltage of intelligent fusion terminal from the reverse filling of peripheral, realizes level clamping and bleeding with transient voltage suppression diode D3 and pull -down resistance R3, and when chip selection circuit is idle or abnormal, its potential can be reliably pulled down, and high voltage peak is absorbed, the utility model discloses effectively prevented the signal line and slice selection line backflow caused by peripheral power supply abnormality, hot plug or short circuit, and the robustness and reliability of intelligent fusion terminal SPI interface have been improved significantly.

[0031] The utility model distinguishes the direction and risk of each signal line of peripheral SPI interface, adopts different protection strategy, especially designs unidirectional conduction circuit to the main equipment input circuit, fundamentally solves the power backflow problem.

[0032] The resistance and diode contained in the first protection module, the second protection module and the third protection module produce minimal signal attenuation and edge delay under 3.3V logic level, better meet the requirement of conventional SPI interface high speed (such as dozens of MHz) communication in the prior art. The pull-down resistance R3 ensures the chip selection circuit in the inactive state of the determination low level, meets the SPI protocol requirement, avoids the bus conflict. The embodiment used is all common discrete devices, does not need complex chip, can be added easily on the existing terminal PCB layout, almost does not increase hardware cost, is more convenient and practical.

[0033] The above embodiment is only the preferred embodiment of the utility model, and the right range of the utility model cannot be limited by this, therefore, the modification, equivalent change, improvement etc. made in the patent range of the utility model still belong to the range covered by the utility model.

Claims

1. A smart fusion terminal SPI communication interface circuit for preventing backflow from peripherals, characterized in that: The application relates to a peripheral SPI interface and a master control unit integrated on a smart fusion terminal, wherein the peripheral SPI interface is used for electrically connecting external SPI slave devices, and the peripheral SPI interface is bidirectionally electrically connected with the master control unit; the peripheral SPI interface comprises an output clock circuit, a master device output circuit, a master device input circuit and a chip selection circuit; a first protection module is arranged between the output clock circuit and the master device output circuit; a second protection module is arranged on the master device input circuit; and a third protection module is arranged on the chip selection circuit.

2. The intelligent converged terminal SPI communication interface circuit for preventing external device backflow according to claim 1, characterized in that: The first protection module comprises current-limiting resistors R1 and R12, clamping diodes V3 and V4, unidirectional isolation diodes D1 and D4; the unidirectional isolation diode D4 and the current-limiting resistor R12 are connected in series along an output end of the output clock circuit; the unidirectional isolation diode D1 and the current-limiting resistor R1 are connected in series along an output end of the master device output circuit; the unidirectional isolation diode D4 and the current-limiting resistor R12, the unidirectional isolation diode D1 and the current-limiting resistor R1 are connected in parallel with the cathodes of the clamping diodes V3 and V4; the anodes of the clamping diodes V3 and V4 are grounded, and are used for clamping the negative voltage of the output clock circuit and the master device output circuit to the ground level.

3. The intelligent converged terminal SPI communication interface circuit for preventing external device backflow according to claim 2, characterized in that: The second protection module comprises a current-limiting resistor R4 and a Schottky diode D2; the Schottky diode D2 and the current-limiting resistor R4 are connected in series along an output end of the master device output circuit; the anode of the Schottky diode D2 is connected with an MISO pin of the peripheral SPI interface, and the cathode is connected with an MISO input pin of the master control unit.

4. The intelligent converged terminal SPI communication interface circuit for preventing external device backflow according to claim 3, characterized in that: The third protection module comprises a pull-down resistor R3 and a transient voltage suppression diode D3; the pull-down resistor R3 and the transient voltage suppression diode D3 are connected in parallel on the chip selection circuit; one end of the pull-down resistor R3 is connected with the chip selection circuit, and the other end is grounded; one end of the transient voltage suppression diode D3 is connected with the chip selection circuit, and the other end is grounded; the transient voltage suppression diode D3 is used for clamping an abnormal high-voltage peak on the chip selection circuit to a safe voltage.

5. The intelligent converged terminal SPI communication interface circuit of claim 4, wherein: The chip selection circuit is bidirectionally electrically connected with a GPIO of the master control unit; the on-resistance of the GPIO output stage of the master control unit is smaller than the resistance value of the pull-down resistor R3.

6. The intelligent converged terminal SPI communication interface circuit of claim 5, wherein: The resistance values of the current-limiting resistors R1 and R12 are 10-100 ohms.

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