Data processing module

Abstract

The utility model relates to the technical field of data processing, in particular to a data processing module, which comprises a system main body, the system main body comprises a carrier plate, a daughter card, a transceiving processing module, a control management module, a transceiving switch and a clock module, the daughter card is connected with the carrier plate, the transceiving processing module is connected with the daughter card, and the control management module is connected with the transceiving processing module. The transceiving switch is connected with the transceiving processing module, the clock module is respectively connected with the transceiving processing module and the control management module, and the transceiving processing module and the transceiving switch on the daughter card can acquire, process and analyze data, so that the market blank is filled.

Description

Technical Field

[0001] This utility model relates to the field of data processing technology, and in particular to a data processing module. Background Technology

[0002] In the current field of electronic device R&D, data acquisition and processing technologies are crucial. The widely used processing modules based on System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) have revealed a series of problems that urgently need to be addressed. These traditional modules are generally quite large, which becomes a key factor hindering further product optimization and upgrades in many applications with stringent requirements for device miniaturization and integration. For example, in portable medical testing devices and wearable smart equipment, excessively large processing modules make it difficult to reduce the overall size of the device, affecting product portability and user experience.

[0003] Meanwhile, its functional metrics also fail to meet the requirements of current cutting-edge technologies. Today, many industries have higher expectations for data processing capabilities, demanding not only basic data collection and processing but also in-depth data analysis capabilities to uncover the potential value behind the data. However, traditional processing modules have significant shortcomings in terms of accuracy, efficiency, and support for complex algorithms in data analysis.

[0004] In conclusion, there is an urgent need to develop a small-sized processing module that can efficiently acquire and process data and has powerful data analysis capabilities, specifically tailored to the technical requirements, in order to fill the market gap and meet the ever-evolving technological demands. Utility Model Content

[0005] The purpose of this utility model is to provide a data processing module that addresses the urgent need to develop a small-sized processing module that can efficiently acquire and process data and has powerful data analysis capabilities to meet specific technical requirements, thereby filling a market gap and meeting the ever-evolving technological demands.

[0006] To achieve the above objectives, this utility model provides a data processing module, including a system main body. The system main body includes a carrier board, a daughter card, a transceiver processing module, a control and management module, a transceiver switch, and a clock module. The daughter card is connected to the carrier board, the transceiver processing module is connected to the daughter card, the control and management module is connected to the transceiver processing module, the transceiver switch is connected to the transceiver processing module, and the clock module is connected to both the transceiver processing module and the control and management module.

[0007] The clock module includes a clock unit and a sampling clock unit. The clock unit is connected to the transceiver processing module and the control management module, respectively. The sampling clock unit is connected to the transceiver processing module and the control management module, respectively.

[0008] The system body also includes a first interface chip, which is connected to the transceiver processing module.

[0009] The main body of the system also includes a first optical module, which is connected to the transceiver processing module.

[0010] The system body also includes a second interface chip, which is connected to the control and management module.

[0011] The main body of the system also includes a second optical module, which is connected to the control and management module.

[0012] This utility model discloses a data processing module. The carrier board mainly implements power conversion and external interface signal conversion, while the daughter card mainly implements clock management, 4-channel intermediate frequency signal acquisition / transmission, digital signal processing, and control management. In the design, the intermediate frequency signal transmission and reception are realized through the transceiver switch. The transceiver switch is a high-isolation SPDT RF switch, which integrates switching circuit, power management circuit, and logic control circuit. It features low insertion loss, high linearity, and low power consumption. The clock module provides a unified clock signal to the transceiver processing module and the control management module, ensuring that data transmission and interaction between different components can be synchronized. Thus, the transceiver processing module and the transceiver switch on the daughter card enable data acquisition, processing, and analysis capabilities, thereby filling a market gap. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0014] Figure 1 This is a schematic diagram of the data processing module of the first embodiment of this utility model.

[0015] Figure 2 This is a schematic diagram of the transceiver switch according to the first embodiment of this utility model.

[0016] Figure 3 This is a schematic diagram of the functional circuit of the protection chip according to the first embodiment of this utility model.

[0017] Figure 4 This is a schematic diagram of the LTM4613 circuit according to the first embodiment of this utility model.

[0018] Figure 5 This is a design block diagram of the VU3P system according to the first embodiment of this utility model.

[0019] Figure 6 This is a schematic diagram of the logic clock structure of the first embodiment of this utility model.

[0020] Figure 7 This is an internal bus block diagram of the first embodiment of this utility model.

[0021] Figure 8 This is a system design block diagram of the first embodiment of this utility model.

[0022] Figure 9 This is a schematic diagram of the clock reset module according to the first embodiment of this utility model.

[0023] In the diagram: 101-System main body, 102-Carrier board, 103-Daughter card, 104-Transceiver processing module, 105-Control and management module, 106-Transceiver switch, 107-Clock module, 108-First interface chip, 109-First optical module, 110-Second interface chip, 111-Second optical module, 112-Clock unit, 113-Sampling clock unit. Detailed Implementation

[0024] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.

[0025] The first embodiment of this application is as follows:

[0026] Please see Figures 1 to 9 ,in Figure 1 This is a schematic diagram of the data processing module of the first embodiment of this utility model. Figure 2 This is a schematic diagram of the transceiver switch according to the first embodiment of this utility model. Figure 3 This is a schematic diagram of the functional circuit of the protection chip according to the first embodiment of this utility model. Figure 4 This is a schematic diagram of the LTM4613 circuit according to the first embodiment of this utility model. Figure 5 This is a design block diagram of the VU3P system according to the first embodiment of this utility model. Figure 6 This is a schematic diagram of the logic clock structure of the first embodiment of this utility model. Figure 7 This is an internal bus block diagram of the first embodiment of this utility model. Figure 8 This is a system design block diagram of the first embodiment of this utility model. Figure 9 This is a schematic diagram of the clock reset module according to the first embodiment of this utility model.

[0027] This utility model provides a data processing module, including a system body 101. The system body 101 includes a carrier board 102, a daughter card 103, a transceiver processing module 104, a control and management module 105, a transceiver switch 106, a clock module 107, a first interface chip 108, a first optical module 109, a second interface chip 110, and a second optical module 111. The clock module 107 includes a clock unit 112 and a sampling clock unit 113. This solution addresses the urgent need to develop a small-sized processing module that efficiently acquires and processes data and possesses powerful data analysis capabilities to meet specific technical requirements, filling a market gap and satisfying evolving technological demands. It is understood that this solution can be used in situations where a module is required to achieve data acquisition and processing as well as possess powerful data analysis capabilities.

[0028] In this embodiment, the main system 101 primarily includes multi-channel AD / DA conversion, interface level conversion, and photoelectric / electro-optical conversion. Since the multiple modules contain four intermediate frequency signals, the modules require an overlapping design involving the carrier board 102 and the daughter card 103.

[0029] Furthermore, the daughter card 103 is connected to the carrier board 102, the transceiver processing module 104 is connected to the daughter card 103, the control management module 105 is connected to the transceiver processing module 104, the transceiver switch is connected to the transceiver processing module 104, and the clock module 107 is connected to both the transceiver processing module 104 and the control management module 105. The daughter card 103 and the carrier board 102 are interconnected via an FMC connector. The carrier board 102 mainly implements power conversion and external interface signal conversion, while the daughter card 103 mainly implements clock management, 4-channel intermediate frequency signal acquisition / transmission, digital signal processing, and... In the control and management section, the intermediate frequency signal is transmitted and received via the transceiver switch. The transceiver switch is a high-isolation SPDT RF switch, which integrates switching circuits, power management circuits, and logic control circuits. It features low insertion loss, high linearity, and low power consumption. The clock module 107 provides a unified clock signal to the transceiver processing module 104 and the control and management module 105, ensuring that data transmission and interaction between different components can be synchronized. Thus, the transceiver processing module 104 and the transceiver switch on the daughter card 103 enable data acquisition, processing, and analysis capabilities, thereby filling a market gap.

[0030] Furthermore, the clock unit 112 is connected to the transceiver processing module 104 and the control management module 105 respectively; the sampling clock unit 113 is connected to the transceiver processing module 104 and the control management module 105 respectively; the first interface chip 108 is connected to the transceiver processing module 104; the first optical module 109 is connected to the transceiver processing module 104; the second interface chip 110 is connected to the control management module 105; and the second optical module 111 is connected to the control management module 105. The clock unit 112 and the sampling clock unit 113 provide a unified clock signal for the transceiver processing module 104 and the control management module 105, ensuring that data transmission and interaction between different components can be synchronized. The first interface chip 108 is for debugging RS232, and the second interface chip 110 has four sets. The first optical module 109 performs photoelectric / electro-optical conversion to complete the functions and performance of the entire system.

[0031] Furthermore, the main body 101 of the system employs a high-voltage surge suppressor (SMAJ58CA) for input power protection. By controlling the on / off state of the external power transistor, surge spikes and load drops in the system are controlled, thereby protecting the external power transistor and the load system for safe operation. The device has an input voltage range of 4V to 80V, and the output clamping voltage can be set via an external resistor, providing highly reliable protection for vehicle-mounted and airborne power systems. The main body 101 of the system provides over-voltage, under-voltage, and short-circuit protection for a 28V power supply, with the power input range limited to 16~36V.

[0032] Furthermore, during input overvoltage, the output voltage is limited, and the internal amplifier adjusts the GATE pin voltage to maintain 1.275V on the FB pin. During this process, the external MOSFET turns on and provides current to the load. This allows the chip to operate uninterruptedly during brief overvoltage events. Simultaneously, when an overvoltage occurs, a fault timer starts counting. If the overvoltage persists, the protection device will turn off the external MOSFET after the set timeout period. The 4613 regulator can provide one 8A DC-DC wide-range power supply. The design converts the input 28V power supply to 12V to ensure the output power meets the input range of the subsequent 4650 / 4644 regulators. The 4650 regulator can provide two 25A current outputs or one 50A current output. The 4644 regulator can provide four 4A current outputs in a DC-DC power supply.

[0033] Furthermore, the FPGA logic function is designed as a complete functional program according to requirements, including design-related port declarations, port constraints, clock module 107, and related interface drivers. The main working clock inside the logic is provided by the clock fanned out by the management unit. The clock is output in multiple frequencies after passing through the MMCM inside the FPGA for use by the internal logic. The logic global reset signal is generated by the MMCM lock state signal. The reset signal is released after the clock stabilizes for a period of time. After being synchronized by the clock reset module, it is output to each module. Some functional modules are connected through an internal bus, so that a master control terminal can realize communication and control operations with each module.

[0034] Furthermore, internal status information, temperature and voltage information, other control statuses, and control commands can all be connected from each module to the soft core via a dedicated SPI bus. The SPI interface adopts the standard four-wire SPI protocol, with a 16-bit address plus 16-bit data structure. The highest bit of the address is the read / write command flag, 1 for read and 0 for write. The UART is implemented using the official AXI Uartlite IP core, with software-driven control protocol framing and data transmission / reception. The ZYNQ logic functions are customized according to requirements, and the overall design is a complete functional program, including design-related port declarations, port constraints, clock module 107, and related interface drivers.

[0035] Furthermore, the internal operating clock is a 50MHz clock input from the PS, which is then processed by a single MMCM to output a 100MHz clock for internal logic use. Clocks output to other external devices are uniformly provided via ODDR. The global logic reset signal is generated by the MMCM's locked state signal. The reset signal is released after a period of clock stabilization and is synchronized by the clock reset module before being output to each module.

[0036] When using the data processing module of this embodiment, the carrier board 102 mainly implements power conversion and external interface signal conversion, while the daughter card 103 mainly implements clock management, 4-channel intermediate frequency signal acquisition / transmission, digital signal processing, and control management. In the design, the intermediate frequency signal is transmitted and received through the transceiver switch. The transceiver switch is a high-isolation SPDT RF switch, which integrates switching circuits, power management circuits, and logic control circuits. It features low insertion loss, high linearity, and low power consumption. The clock module 107 provides a unified clock signal to the transceiver processing module 104 and the control management module 105, ensuring that data transmission and interaction between different components can be synchronized. Thus, the transceiver processing module 104 and the transceiver switch on the daughter card 103 enable data acquisition, processing, and data analysis capabilities, thereby filling a market gap.

[0037] The above-disclosed embodiments are merely one or more preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art can understand that all or part of the processes for implementing the above embodiments and equivalent changes made in accordance with the claims of this application still fall within the scope of this application.

Claims

1. A data processing module, characterized by The system body comprises a carrier board, a daughter card, a transceiving processing module, a control management module, a transceiving switch and a clock module, the daughter card is connected with the carrier board, the transceiving processing module is connected with the daughter card, the control management module is connected with the transceiving processing module, the transceiving switch is connected with the transceiving processing module, and the clock module is connected with the transceiving processing module and the control management module respectively.

2. The data processing module of claim 1, wherein, the clock module comprises a clock unit and a sampling clock unit, the clock unit is connected with the transceiving processing module and the control management module respectively, and the sampling clock unit is connected with the transceiving processing module and the control management module respectively.

3. The data processing module of claim 1, wherein, the system body further comprises a first interface chip, and the first interface chip is connected with the transceiving processing module.

4. The data processing module of claim 1, wherein, the system body further comprises a first optical module, and the first optical module is connected with the transceiving processing module.

5. The data processing module of claim 1, wherein, the system body further comprises a second interface chip, and the second interface chip is connected with the control management module.

6. The data processing module of claim 1, wherein, the system body further comprises a second optical module, and the second optical module is connected with the control management module.

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