Semiconductor device structure

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes an epitaxial structure and a semiconductor nanostructure electrically connected to the epitaxial structure. The semiconductor device structure also includes a metal gate stack extending across the semiconductor nanostructure, and the metal gate stack has a gate dielectric layer and a gate electrode. The semiconductor device structure also includes a protection structure over the metal gate stack and the epitaxial structure. A top of the gate dielectric layer is between a top surface of the protection structure and a bottom surface of the protection structure. A top of the gate dielectric layer is closer to the semiconductor nanostructure than a top of the metal gate stack.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to semiconductor technology, in particular to a semiconductor device structure with a protection structure. BACKGROUND

[0002] The semiconductor integrated circuit industry has experienced rapid growth. A steady increase in demand has created need for smaller and faster circuits. In addition, as

[0003] During the progression of integrated circuit evolution, the functionality of the circuits has increased while the geometry size (that is, the smallest component (or line) that can be produced using a process) has decreased. This scaling down process generally provides benefits in increased production efficiency and lower costs.

[0004] However, these advances increase the complexity of processing and manufacturing integrated circuits. As the dimensions of the components continue to shrink, fabrication processes become increasingly difficult. Therefore, reliable fabrication of ever smaller semiconductor devices is a challenging task. SUMMARY

[0005] The present utility model aims to provide a semiconductor device structure to solve at least one of the above problems.

[0006] The present utility model provides a semiconductor device structure. The semiconductor device structure includes an epitaxial structure and a semiconductor nanostructure electrically connected to the epitaxial structure. The semiconductor device structure further includes a metal gate stack extending across the semiconductor nanostructure, and the metal gate stack has a gate dielectric layer and a gate electrode. The semiconductor device structure further includes a protection structure above the metal gate stack and the epitaxial structure. A top portion of the gate dielectric layer is between a top surface of the protection structure and a bottom surface of the protection structure. The top portion of the gate dielectric layer is closer to the semiconductor nanostructure than a top portion of the metal gate stack.

[0007] According to one embodiment of the present utility model, further comprising: an electrically conductive contact electrically connected to the epitaxial structure, wherein the electrically conductive contact penetrates the protection structure.

[0008] According to one embodiment of the present utility model, a lower portion of the electrically conductive contact is laterally surrounded by the epitaxial structure.

[0009] According to one embodiment of the present utility model, further comprising: a dielectric layer laterally surrounding an upper portion of the electrically conductive contact; and a protection layer between the electrically conductive contact and the dielectric layer, wherein the protection layer is separated from the epitaxial structure by the protection structure.

[0010] According to one of the embodiments of the present application, the protective layer is in direct contact with the protective structure.

[0011] According to one of the embodiments of the present application, further comprising a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates the protective structure, and the dielectric structure is in direct contact with the metal gate stack and the protective structure.

[0012] According to one of the embodiments of the present application, further comprising a metal semiconductor compound element embedded in the epitaxial structure.

[0013] According to one of the embodiments of the present application, the protective structure is in direct contact with the gate electrode, the gate dielectric layer, and the epitaxial structure.

[0014] According to one of the embodiments of the present application, a bottom of the protective structure is vertically located between a top and a bottom of the epitaxial structure.

[0015] According to one of the embodiments of the present application, the protective structure has a thickness, and the thickness is in a range of 5 nanometers to 14 nanometers. BRIEF DESCRIPTION OF DRAWINGS

[0016] Various aspects of the present application will be described in connection with the appended drawings. It should be noted that the various elements of the drawings are not drawn to scale and are merely intended for use in illustrating the embodiments of the present application. In fact, the dimensions of the elements can be arbitrarily increased or decreased for the sake of clarity in illustrating the embodiments of the present application.

[0017] Figures 1A-1B is a top view showing a process for forming a portion of a semiconductor device structure at various stages, according to some embodiments.

[0018] Figures 2A-2D is a cross-sectional view showing a process for forming a portion of a semiconductor device structure at various stages, according to some embodiments.

[0019] Figures 3A-3I is a cross-sectional view showing a process for forming a portion of a semiconductor device structure at various stages, according to some embodiments.

[0020] Figures 4A-4L is a perspective view showing a process for forming a portion of a semiconductor device structure at various stages, according to some embodiments.

[0021] Figure 4J-1 and Figure 4K-1 is a cross-sectional view showing a process for forming a portion of a semiconductor device structure at various stages, according to some embodiments.

[0022] Figure 5 are cross-sectional views showing a process for forming a portion of a semiconductor device structure at various stages, in accordance with some embodiments.

[0023] Reference signs are as follows:

[0024] 100: semiconductor substrate

[0025] 101A / 101B / 101C / 101D: semiconductor fin

[0026] 102a / 102b / 102c / 104a / 104b / 104c: semiconductor layer

[0027] 104a' / 104b' / 104c': semiconductor nanostructure

[0028] 105a / 105b / 105c: edge portion

[0029] 106A / 106B: fin structure

[0030] 108: first mask layer

[0031] 110: second mask layer

[0032] 112: trench

[0033] 113: liner

[0034] 114: dielectric fill

[0035] 115: isolation structure

[0036] 116: dummy gate dielectric layer

[0037] 118: dummy gate electrode

[0038] 120 / 120A / 120B: dummy gate stack

[0039] 122 / 124: mask layer

[0040] 126 / 128: spacer layer

[0041] 126' / 128': gate spacer

[0042] 130: recess

[0043] 132: recess

[0044] 134: insulating layer

[0045] 136: inner spacer

[0046] 137: semiconductor isolation structure

[0047] 138: epitaxial structure

[0048] 138': lightly doped portion

[0049] 139: contact etch stop layer

[0050] 140: dielectric layer

[0051] 150: gate dielectric layer

[0052] 151: interface layer

[0053] 152: conductive fill

[0054] 152': work function layer

[0055] 156A / 156B / 156C: metal gate stack

[0056] 302: bottom isolation element

[0057] 304: recess

[0058] 402: protective cap

[0059] 404: protective structure

[0060] 406: dielectric structure

[0061] 408: protective liner

[0062] 410: dielectric fill

[0063] 411: etch stop layer

[0064] 412: dielectric layer

[0065] 414: mask element

[0066] 416: contact opening

[0067] 418: protective material layer

[0068] 418': protective layer

[0069] 420: metal-semiconductor compound element

[0070] 422: conductive contact

[0071] D: depth

[0072] H1 / H2: height

[0073] S: distance

[0074] T: thickness

[0075] W: width DETAILED DESCRIPTION

[0076] The following disclosure provides numerous embodiments or examples for implementing various elements of the subject matter provided. Specific examples of elements and their configurations are described below to facilitate explanation of the embodiments of the present application. Of course, these are merely examples and are not intended to limit the embodiments of the present application. For example, if a first element is described as being formed on a second element in the description, it can include an embodiment in which the first and second elements are in direct contact, and can include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present application can repeatedly refer to reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to represent the relationship between the different embodiments and / or configurations being discussed.

[0077] Furthermore, where spatially relative terms are used, such as "beneath", "below", "lower", "above", "upper", and the like, they are used for ease of describing the conceptual merits of the illustrations for clearness' sake, and the drawings are not necessarily drawn to scale. The spatially relative terms are used to encompass different orientations of the device in use or operation, and the illustrations described herein. Where the device is turned over (rotated 90 degrees or other orientation), the spatially relative descriptors will need to be interpreted accordingly.

[0078] Various embodiments of the present application can involve a Fin-like field effect transistor (FinFET) structure having fins. The fins can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines photolithography and self-alignment processes to create patterns that are smaller, for example, than the pitch obtained using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used as a mask to pattern the fins. However, other suitable processes can be used to form the fins.

[0079] Various embodiments of the present utility model can involve gate all around (GAA) transistor structures. The GAA structures can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the structures, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, than would be possible using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0080] The following describes some embodiments of the present invention, in which additional steps can be provided before, during, and / or after the stages described. Some stages described can be replaced or eliminated in various embodiments. Additional components can be added to the semiconductor device structure. Some components described can be replaced or eliminated in various embodiments. Although some embodiments are discussed with steps performed in a particular order, the steps can be performed in another logical order.

[0081] Figures 2A-2D According to some embodiments, cross-sectional views of a process for forming a portion of a semiconductor device structure are shown at various stages. As shown in Figure 2A The semiconductor substrate 100 is received or provided. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor structure, such as a semiconductor wafer. The semiconductor substrate 100 can include silicon or other elemental semiconductor material, such as germanium. The semiconductor substrate 100 can be undoped or doped (e.g., p-type, n-type, or a combination of the foregoing). In some embodiments, the semiconductor substrate 100 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer can be made of silicon, germanium, silicon germanium, other suitable material, or a combination of the foregoing.

[0082] In some embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes one or more of the following elements: Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4The defined composition is a group III-V compound semiconductor, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. All of these proportions are greater than or equal to 0, and the sum of X1, X2, X3, Y1, Y2, Y3, and Y4 is equal to 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable substrate materials, such as group II-VI compound semiconductors, may also be used.

[0083] In some embodiments, the semiconductor substrate 100 is the active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other suitable methods, or a combination thereof. In some other embodiments, the semiconductor substrate 100 includes a multilayer structure. For example, the semiconductor substrate 100 includes a silicon-germanium layer formed over a bulk silicon layer.

[0084] like Figure 2A As shown, according to some embodiments, a semiconductor stack having multiple semiconductor layers is formed over a semiconductor substrate 100. In some embodiments, the semiconductor stack includes multiple semiconductor layers 102a, 102b, and 102c. The semiconductor stack also includes multiple semiconductor layers 104a, 104b, and 104c. In some embodiments, semiconductor layers 102a-102c and semiconductor layers 104a-104c are arranged alternately, such as... Figure 2A As shown. In some embodiments, semiconductor layers 102a-102c and semiconductor layers 104a-104c together form a superlattice structure.

[0085] In some embodiments, semiconductor layers 102b-102c are used as sacrificial layers, which will be removed in a subsequent process to release semiconductor layers 104a-104c. The released semiconductor layers 104a-104c can be used as channel structures for one or more transistors.

[0086] In some embodiments, the semiconductor layers 104a-104c used to form the channel structure are made of a different material than semiconductor layers 102a-102c. In some embodiments, semiconductor layers 104a-104c are made of, or contain, the following materials: silicon, germanium, other suitable materials, or combinations thereof.

[0087] In some embodiments, the semiconductor layers 102a-102c are made of or include silicon germanium. In some other embodiments, the semiconductor layers 104a-104c are made of silicon germanium, and the semiconductor layers 102a-102c are made of silicon germanium having a different germanium atom concentration than the semiconductor layers 104a-104c. In this way, different etch selectivity and / or different oxidation rates can be achieved between the semiconductor layers 102a-102c and the semiconductor layers 104a-104c during subsequent processes.

[0088] It is contemplated that the semiconductor layers 102a-102c and the semiconductor layers 104a-104c include any combination of semiconductor materials that can provide the desired etch selectivity, the desired difference in oxidation rates, and / or the desired performance characteristics.

[0089] In some embodiments, the semiconductor layers 102a-102c and the semiconductor layers 104a-104c are formed using a plurality of epitaxial growth operations. Each of the semiconductor layers 102a-102c and the semiconductor layers 104a-104c can be formed using a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, another suitable process, or a combination thereof.

[0090] In some embodiments, the semiconductor layers 102a-102c and the semiconductor layers 104a-104c are grown in-situ in the same process chamber. In some embodiments, the growth of the semiconductor layers 102a-102c and the semiconductor layers 104a-104c is performed alternately and sequentially in the same process chamber to complete the formation of the semiconductor stack. In some embodiments, the vacuum of the process chamber is not broken before the epitaxial growth of the semiconductor layers 102a-102c and 104a-104c is completed.

[0091] Subsequently, a hard mask element is formed over the semiconductor stack to assist in

[0092] Subsequent patterning of the semiconductor stack. According to some embodiments, the semiconductor stack is patterned to include a plurality of fin structures, including fin structures 106A and 106B, using one or more photolithography processes and one or more etching processes, as shown in Figure 2B .

[0093] Fin structures 106A and 106B can be patterned by any suitable method. For example, fin structures 106A and 106B can be patterned using one or more photolithography processes, including a double patterning or multiple patterning process. Double patterning or multiple patterning processes combine photolithography processes with self-alignment processes to create patterns with smaller pitches, for example, than would be obtained using a single, direct photolithography process.

[0094] The semiconductor stack is partially removed to form trenches 112, as shown in Figure 2B Each of fin structures 106A and 106B can include individual portions of semiconductor layers 102a-102c and 104a-104c and semiconductor fins 101A and 101B. Semiconductor substrate 100 can also be partially removed during the etching process that forms fin structures 106A and 106B. The remaining protruding portions of semiconductor substrate 100 form semiconductor fins 101A and 101B. Each of semiconductor fins 101A and 101B can have a height in a range of about 35 nanometers (nm) to about 55 nm.

[0095] Each hard mask element can include a first mask layer 108 and a second mask layer 110. First mask layer 108 and second mask layer 110 can be made of different materials. In some embodiments, first mask layer 108 is made of a material that has good adhesion to semiconductor layer 104c. First mask layer 108 can be made of silicon oxide, germanium oxide, silicon germanium oxide, other suitable materials, or combinations of the foregoing. Second mask layer 110 can be made of silicon nitride, silicon oxynitride, silicon carbide, other suitable materials, or combinations of the foregoing.

[0096] Figures 1A-1B is a top view of a structure at various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments. In some embodiments, fin structures 106A and 106B are oriented lengthwise. In some embodiments, the lengthwise extension directions of fin structures 106A and 106B are substantially parallel to each other, as shown in Figure 1A . Figure 2B is a cross-sectional view of the structure taken along line 2B-2B in Figure 1A .

[0097] As shown in Figure 2CAs shown, according to some embodiments, the isolation structure 115 is formed to surround lower portions of the fin structures 106A and 106B. In some embodiments, the isolation structure 115 includes the dielectric fill 114 and a liner 113 adjacent the semiconductor fins 101A and 101B. In some embodiments, the semiconductor fins 101A and 101B protrude from a top surface of the isolation structure 115.

[0098] In some embodiments, one or more dielectric layers are deposited over the fin structures 106A and 106B and the semiconductor substrate 100 to overfill the trenches 112. The dielectric layers can be made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k materials, porous dielectric materials, other suitable materials, or combinations of the foregoing. The liner 113 can be made of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, other suitable materials, or combinations of the foregoing. The dielectric layers and the liner 113 can be deposited using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, other suitable processes, or combinations of the foregoing.

[0099] Subsequently, a planarization process is used to partially remove the dielectric layers and the liner 113. The hard mask elements (including the first mask layer 108 and the second mask layer 110) can also serve as a stop layer for the planarization process. The planarization process can include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, other suitable processes, or combinations of the foregoing.

[0100] Subsequently, one or more etch-back processes are used to partially remove the dielectric layers and the liner 113. In this way, remaining portions of the dielectric layers form the dielectric fill 114 of the isolation structure 115. Upper portions of the fin structures 106A and 106B protrude from a top surface of the isolation structure 115, as shown. Figure 2C

[0101] ​In some embodiments, the etch-back process used to form the isolation structure 115 is carefully controlled to ensure that the top surface of the isolation structure 115 is at a suitable height level. In some embodiments, the top surface of the isolation structure 115 is located below the bottom surface of the semiconductor layer 102a, which serves as a sacrificial layer, such as... Figure 2C As shown.

[0102] Subsequently, the remaining portion of the hard mask elements (including the first mask layer 108 and the second mask layer 110) is removed. Alternatively, in some other embodiments, the hard mask elements are removed or consumed during the planarization process and / or etch-back process that forms the isolation structure 115.

[0103] Subsequently, according to some embodiments, dummy gate stacks 120A and 120B are formed to extend across fin structures 106A and 106B, such as Figure 1B As shown. In some embodiments, Figure 2D It is along Figure 1B A cross-sectional view of the structure taken by 2D-2D line cut in the middle. Figures 3A-3I These are cross-sectional views of various stages of a process for forming a part of a semiconductor device structure, according to some embodiments. In some embodiments, Figure 3A It is along Figure 1B A cross-sectional view of the structure cut by line 3A-3A in the diagram.

[0104] like Figure 1B , Figure 2D ,as well as Figure 3A As shown, according to some embodiments, dummy gate stacks 120A and 120B are formed to partially cover and extend across fin structures 106A and 106B. In some embodiments, the dummy gate stacks 120A and 120B surround a portion of the fin structures 106A and 106B. Figure 1B As shown, the other portions of the fin structures 106A and 106B are exposed and not covered by the dummy gate stacks 120A and 120B.

[0105] like Figure 2D as well as Figure 3A As shown, each of the dummy gate stacks 120A and 120B includes a dummy gate dielectric layer 116 and a dummy gate electrode 118. The dummy gate dielectric layer 116 may be made of, or contain, silicon oxide or other suitable materials. The dummy gate electrode 118 may be made of, or contain polysilicon or other suitable materials.

[0106] In some embodiments, a dummy gate dielectric layer and a dummy gate electrode layer are sequentially deposited over the isolation structure 115 and the fin structures 106A and 106B. The dummy gate dielectric layer can be deposited using an ALD process, a CVD process, other suitable processes, or a combination thereof. The dummy gate electrode layer can be deposited using a CVD process. Subsequently, the dummy gate dielectric layer and the dummy gate electrode layer are patterned to form dummy gate stacks 120A and 120B.

[0107] In some embodiments, the hard mask element includes mask layers 122 and 124 for assisting in the formation of dummy gate stacks 120A and 120B during a patterning process. Using the hard mask element as an etch mask, one or more etch processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer. The remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form the dummy gate stacks 120A and 120B, including the dummy gate dielectric layer 116 and the dummy gate electrode 118.

[0108] like Figure 3B As shown, according to some embodiments, spacer layers 126 and 128 are subsequently deposited over the dummy gate stacks 120A and 120B and the fin structure 106B. The spacer layers 126 and 128 extend along the top and sidewalls of the dummy gate stacks 120A and 120B, as... Figure 3B As shown. Spacer layers 126 and 128 also extend along the top of fin structure 106B, as... Figure 3B As shown.

[0109] In some embodiments, spacer layers 126 and 128 are made of different materials. In some other embodiments, spacer layers 126 and 128 are made of the same material. Spacer layers 126 and 128 may be made of, or comprise, the following materials: silicon nitride, silicon carbide, silicon carbide, silicon oxynitride-containing carbon, silicon oxide, other suitable materials, or combinations thereof. In some embodiments, each of spacer layers 126 and 128 is a monolayer. In some other embodiments, one or both of spacer layers 126 and 128 comprises multiple sublayers. Some sublayers may be made of different materials. Some sublayers may be made of similar materials with different compositions. For example, one sublayer may have a higher carbon atom concentration than the other sublayers. Spacer layers 126 and 128 may be sequentially deposited using CVD, ALD, physical vapor deposition (PVD), other suitable processes, or combinations thereof.

[0110] like Figure 3CAs shown, according to some embodiments, spacer layers 126 and 128 are partially removed. One or more anisotropic etching processes can be used to partially remove spacer layers 126 and 128. In this way, the remaining portions of spacer layers 126 and 128 form gate spacers 126' and 128', respectively. Gate spacers 126' and 128' extend along the sidewalls of the dummy gate stacks 120A and 120B, as... Figure 3C As shown. The thickness of the gate spacers 126' and 128' can range from approximately 4 nanometers to approximately 6 nanometers.

[0111] Subsequently, fin structures 106A and 106B are partially removed to form grooves for accommodating epitaxial structures that will be formed later. For example... Figure 3C As shown, according to some embodiments, fin structures 106A and 106B are partially removed to form a recess 130. The recess 130 exposes the side surfaces of semiconductor layers 104a-104c, on which epitaxial structures (e.g., source / drain structures) will later be formed. The term "source / drain structure" may refer individually or collectively to either a source structure or a drain structure, depending on the context.

[0112] One or more etching processes can be used to form the grooves 130. In some embodiments, a dry etching process is used to form the grooves 130. Alternatively, a wet etching process can be used to form the grooves 130. In some embodiments, each groove 130 extends into the fin structure 106B. In some embodiments, the grooves 130 further extend into the semiconductor fin 101B, such as... Figure 3C As shown. In some embodiments, the gate spacers 126' and 128' and the recess 130 are formed simultaneously using the same etching process.

[0113] In some embodiments, each recess 130 has sloping sidewalls. The upper portion of the recess 130 is larger (or wider) than the lower portion of the recess 130. In these cases, due to the profile of the recess 130, the higher semiconductor layer (e.g., semiconductor layer 104c) is shorter than the lower semiconductor layer (e.g., semiconductor layer 104b).

[0114] However, embodiments of this invention have many variations. In some other embodiments, the recess 130 has substantially vertical sidewalls. In these cases, due to the profile of the recess 130, the higher semiconductor layer (e.g., semiconductor layer 104c) is substantially the same width as the lower semiconductor layer (e.g., semiconductor layer 104b).

[0115] like Figure 3D As shown, according to some embodiments, semiconductor layers 102b-102c are etched laterally. In this way, the edges of semiconductor layers 102b-102c recede from the edges of semiconductor layers 104a-104c.Figure 3D As shown, the recess 132 is formed by lateral etching of semiconductor layers 102b-102c. The recess 132 can be used to accommodate inner spacers that will be formed laterally. Semiconductor layers 102b-102c can be laterally etched using a wet etching process, a dry etching process, or a combination thereof. In some other embodiments, semiconductor layers 102a-102c are partially oxidized before being laterally etched.

[0116] In some embodiments, during the lateral etching of semiconductor layers 102b-102c, semiconductor layers 104a-104c may also be slightly etched. In this way, the edge portions of semiconductor layers 104a-104c are partially etched, thereby shrinking to form edge portions 105a-105c, such as... Figure 3D As shown. Figure 3D As shown, each edge portion 105a-105c of semiconductor layers 104a-104c is thinner than the corresponding inner portion of semiconductor layers 104a-104c. In some other embodiments, semiconductor layers 104a-104c are substantially not etched during the lateral etching of semiconductor layers 102a-102c. In this way, the edge portions 105a-105c of semiconductor layers 104a-104c do not substantially shrink. In some embodiments, each edge portion 105a-105c of semiconductor layers 104a-104c is substantially the same thickness as the corresponding inner portion of semiconductor layers 104a-104c.

[0117] like Figure 3E As shown, according to some embodiments, in such Figure 3D An insulating layer 134 is deposited over the structure shown. The insulating layer 134 covers the dummy gate stacks 120A and 120B and fills the recess 132. The insulating layer 134 may be made of, or contain, the following materials: silicon carbonitride (SiCN), silicon carbon oxynitride (SiOCN), silicon carbon oxide (SiOC), silicon oxide, silicon nitride, other suitable materials, or combinations thereof. In some embodiments, the insulating layer 134 is a single layer. In some other embodiments, the insulating layer 134 includes multiple sublayers. Some sublayers may be made of different materials and / or contain different compositions. The insulating layer 134 may be deposited using CVD processes, ALD processes, other suitable processes, or combinations thereof.

[0118] like Figure 3F As shown, according to some embodiments, an etching process is used to partially remove the insulating layer 134. The portion of the insulating layer 134 outside the recess 132 can be removed. The remaining portion of the insulating layer 134 forms the inner spacer 136, as... Figure 3FAs shown. The etching process may include dry etching, wet etching, or a combination thereof. Each inner spacer 136 may have a thickness ranging from approximately 4 nanometers to approximately 6 nanometers.

[0119] The inner spacer 136 covers the edges of semiconductor layers 102b-102c. The inner spacer 136 serves to prevent damage to subsequently formed epitaxial structures (which serve as, for example, source / drain structures) during subsequent removal processes of semiconductor layers 102b-102c. In some embodiments, the inner spacer 136 is made of a low-k material with a dielectric constant lower than that of silicon oxide. The inner spacer 136 can also be used to reduce parasitic capacitance between the subsequently formed source / drain structures and the gate stack. This improves the operating speed of the semiconductor device structure.

[0120] In some embodiments, after the etching process that forms the inner spacer 136, portions of the semiconductor fin 101B that were originally covered by the insulating layer 134 are exposed by the groove 130, such as Figure 3F As shown. The edges of semiconductor layers 104a-104c are also exposed by the groove 130, as... Figure 3F As shown.

[0121] like Figure 3G As shown, according to some embodiments, a semiconductor isolation structure 137 is formed above the bottom of the recess 130. In some embodiments, the semiconductor isolation structure 137 is an undoped epitaxial structure. In some embodiments, the semiconductor isolation structure 137 is substantially free of n-type or p-type dopants. The semiconductor isolation structure 137 helps reduce or prevent leakage current from the epitaxial structure to be formed. The semiconductor isolation structure 137 can provide a relatively flat surface to facilitate subsequent formation of the epitaxial structure.

[0122] The semiconductor isolation structures 137 can be made of, or include, silicon, silicon germanium, other suitable materials, or combinations of the foregoing. The semiconductor isolation structures 137 can be formed using a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, other suitable processes, or combinations of the foregoing. In some embodiments, the formation of the semiconductor isolation structures 137 involves one or more etching processes to fine-tune the profile of the semiconductor isolation structures 137.

[0123] Subsequently, as shown in FIG. 3B, bottom isolation elements 302 are selectively formed on the semiconductor isolation structures 137, according to some embodiments. The bottom isolation elements 302 can prevent leakage current between the semiconductor fins 101B and epitaxial structures to be formed on the bottom isolation elements 302. Each of the bottom isolation elements 302 has a thickness in a range from about 2 nanometers to about 6 nanometers. Figure 3G

[0124] In some embodiments, the bottom isolation elements 302 are made of, or include, a dielectric material. The dielectric material can include silicon oxide, silicon nitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, carbon-containing silicon oxide, aluminum oxide, hafnium oxide, other suitable materials, or combinations of the foregoing. The formation of the bottom isolation elements 302 can involve one or more deposition processes and one or more patterning processes.

[0125] However, embodiments of the present disclosure are not limited thereto. Embodiments of the present disclosure can be subject to many variations and / or modifications. In some other embodiments, the bottom isolation elements 302 are not formed.

[0126] As shown in FIG. 3B, epitaxial structures 138 are formed on the bottom isolation elements 302 and on the side surfaces of the semiconductor layers 104a-104c, according to some embodiments. In some embodiments, the top surfaces of the epitaxial structures 138 are higher than the top surface of the dummy gate dielectric layer 116, as shown in FIG. 3C. In some other embodiments, the epitaxial structures 138 are substantially as high as the top of the edge portion 105c. Figure 3G Figure 3G

[0127] ​​​In some embodiments, the epitaxial structures 138 are connected to the semiconductor layers 104a-104c. Each of the semiconductor layers 104a-104c is sandwiched between two epitaxial structures 138. In some embodiments, the epitaxial structures 138 have lightly doped portions 138' adjacent to the semiconductor layers 104a-104c. The lightly doped portions 138' have a lower doping concentration than other portions of the epitaxial structures 138.

[0128] In some embodiments, the epitaxial structures 138 are p-type doped regions. The epitaxial structures 138 can include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon, or other suitable epitaxially grown semiconductor material. The p-type dopant can include boron, other suitable elements, or combinations of the foregoing.

[0129] However, embodiments of the present application are not limited thereto. In some other embodiments, the epitaxial structures 138 are n-type doped regions. The epitaxial structures 138 can include epitaxially grown silicon, epitaxially grown silicon carbide (SiC), epitaxially grown germanium, or other suitable epitaxially grown semiconductor material. The n-type dopant can include phosphorus, arsenic, other suitable elements, or combinations of the foregoing.

[0130] In some embodiments, the epitaxial structures 138 are doped in situ during their epitaxial growth. The initial reactant gas mixture used to form the epitaxial structures 138 contains the dopant. In some other embodiments, the epitaxial structures 138 are not doped during their growth. Instead, the epitaxial structures 138 are doped in a subsequent process after the epitaxial structures 138 are formed. In some embodiments, the doping is achieved by using an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid source diffusion process, other suitable process, or combinations of the foregoing. In some embodiments, the epitaxial structures 138 are further exposed to one or more annealing processes to activate the dopant. For example, a rapid thermal annealing process is used.

[0131] In some embodiments, some of the epitaxial structures 138 are p-type doped, while other epitaxial structures 138 are n-type doped. A patterning mask can be used to assist in forming the p-type doped epitaxial structures 138 and the n-type doped epitaxial structures 138, respectively.

[0132] As Figure 3HAs shown, according to some embodiments, a contact etch stop layer 139 and a dielectric layer 140 are formed over the epitaxial structure 138 and the dummy gate stacks 120A and 120B. The contact etch stop layer 139 may be made of, or contain, the following materials: silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, aluminum oxide, other suitable materials, or combinations thereof. The contact etch stop layer 139 may have a thickness in the range of approximately 4 nanometers to approximately 5 nanometers. The dielectric layer 140 may be made of, or contain, the following materials: silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low dielectric constant (k) materials, porous dielectric materials, other suitable materials, or combinations thereof.

[0133] In some embodiments, Figure 3G An etch stop material layer and a dielectric material layer are sequentially deposited on top of the structure shown. The etch stop material layer can be deposited using CVD, ALD, PVD, other suitable processes, or combinations thereof. The dielectric material layer can be deposited using FCVD, CVD, ALD, other suitable processes, or combinations thereof.

[0134] Subsequently, a planarization process is used to partially remove the etch stop material layer and the dielectric material layer. As a result, the remaining portions of the etch stop material layer and the dielectric material layer form the contact etch stop layer 139 and the dielectric layer 140, respectively. Figure 3H As shown. Planarization processes may include CMP processes, polishing processes, etching processes, dry polishing processes, other suitable processes, or combinations thereof.

[0135] In some embodiments, mask layers 122 and 124 above the dummy gate stacks 120A and 120B are removed during the planarization process. In some embodiments, after the planarization process, the top surfaces of the contact etch stop layer 139, the dielectric layer 140, and the dummy gate electrode 118 are substantially flush with each other.

[0136] like Figure 3I As shown, according to some embodiments, the dielectric layer 140 is partially removed to form a groove 304. One or more etching processes can be used to form the groove 304. The groove 304 can be used to accommodate a protective element that will be formed later.

[0137] Figures 4A-4LThis is a perspective view showing the various stages of a process for forming a part of a semiconductor device structure, according to some embodiments. Figure 4A The structure shown can be used with Figures 2A-2D as well as Figures 3A-3I The process is the same as or similar to the one shown. In some embodiments, Figure 3I yes Figure 4A A cross-sectional view of a portion of the structure shown.

[0138] like Figure 4B As shown, according to some embodiments, a protective cap 402 is formed in the recess 304. The protective cap 402 can protect the underlying dielectric layer 140. In some embodiments, a protective material layer is deposited over the contact etch stop layer 139, the dummy gate stacks 120A and 120B, and the dielectric layer 140 to overfill the recess 304. The protective material layer may be made of, or contain, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, other suitable materials, or combinations thereof. The protective material layer can be deposited using CVD processes, ALD processes, FCVD processes, other suitable processes, or combinations thereof.

[0139] Subsequently, according to some embodiments, the protective material layer is planarized, thereby exposing the dummy gate stacks 120A and 120B. The remaining portion of the protective material layer forms a protective cap 402, as shown below. Figure 4B As shown. CMP, grinding, etching, dry polishing, other suitable processes, or combinations thereof can be used to planarize the protective material layer.

[0140] Subsequently, according to some embodiments, such as Figure 4C As shown, a gate replacement process is performed to replace dummy gate stacks 120A and 120B with metal gate stacks 156A and 156B, respectively. According to some embodiments, one or more etching processes are used to remove the dummy gate electrode 118 to form a trench. The trench may expose the dummy gate dielectric layer 116.

[0141] Subsequently, according to some embodiments, the dummy gate dielectric layer 116 and semiconductor layers 102a-102c (which serve as sacrificial layers) are removed. In some embodiments, one or more etching processes are used to remove the dummy gate dielectric layer 116 and semiconductor layers 102a-102c. This forms a groove between the inner spacers 136.

[0142] Due to the high etch selectivity, the semiconductor layers 104a-104c are only slightly etched (or substantially not etched). The remaining portions of the semiconductor layers 104a-104c form a plurality of semiconductor nanostructures 104a'-104c'. The semiconductor nanostructures 104a'-104c' are made of or from the remaining portions of the semiconductor layers 104a-104c. The semiconductor nanostructures 104a'-104c' can be used as channel structures for transistors.

[0143] In some embodiments, the etchant used to remove the semiconductor layers 102b-102c also slightly removes the semiconductor layers 104a-104c used to form the semiconductor nanostructures 104a'-104c'. As such, after the semiconductor layers 102b-102c are removed, the resulting semiconductor nanostructures 104a'-104c' become thinner. In some embodiments, each of the semiconductor nanostructures 104a'-104c' is thinner than the edge portions 105a-105c because the edge portions 105a-105c are surrounded by other elements and thus prevented from being contacted and etched by the etchant.

[0144] After the semiconductor layers 102b-102c (which are used as sacrificial layers) are removed, recesses are formed. The recesses surround each of the semiconductor nanostructures 104a'-104c'. Even though the recesses between the semiconductor nanostructures 104a'-104c' are formed, the semiconductor nanostructures 104a'-104c' are still held by the epitaxial structures 138. Thus, after the semiconductor layers 102b-102c (which are used as sacrificial layers) are removed, the released semiconductor nanostructures 104a'-104c' are prevented from falling off.

[0145] During the removal of the semiconductor layers 102b-102c (which are used as sacrificial layers), the inner spacers 136 protect the epitaxial structures 138 from being etched or damaged. The quality and reliability of the semiconductor device structure are improved.

[0146] Subsequently, according to some embodiments, metal gate stacks 156A and 156B are formed to fill the trenches and the recesses. The metal gate stacks 156A and 156B further extend into the recesses to enclose each of the semiconductor nanostructures 104a'-104c'. Each of the metal gate stacks 156A and 156B includes a plurality of metal gate stack layers. Each of the metal gate stacks 156A and 156B can include an interface layer 151, a gate dielectric layer 150, and a metal gate electrode. The metal gate electrode includes one or more work function layers 152' and a conductive filler 152.

[0147] In some embodiments, formation of the metal gate stacks 156A and 156B involves depositing a plurality of metal gate stack layers over the dielectric layer 140 to fill the trenches as well as the recesses. The metal gate stack layers extend into the recesses to wrap around each of the semiconductor nanostructures 104a'-104c'.

[0148] In some embodiments, the gate dielectric layer 150 is made of, or includes, a dielectric material having a high-k. The gate dielectric layer 150 can be made of, or include, hafnium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-k materials, or combinations of the foregoing. The gate dielectric layer 150 can be deposited using an ALD process, a CVD process, other suitable process, or combinations of the foregoing.

[0149] In some embodiments, prior to forming the gate dielectric layer 150, an interface layer 151 is formed on the surfaces of the semiconductor nanostructures 104a'-104c'. The interface layer 151 is very thin and is made of, for example, silicon oxide or germanium oxide. In some embodiments, the interface layer 151 is formed by applying an oxidizing agent on the surfaces of the semiconductor nanostructures 104a'-104c'. For example, a liquid containing hydrogen peroxide can be provided or applied on the surfaces of the semiconductor nanostructures 104a'-104c' to form the interface layer 151.

[0150] The work function layer 152' of the metal gate electrode can be used to provide a desired work function for the transistor to improve device performance, including improving threshold voltage. In some embodiments, the work function layer 152' is used to form a p-type metal-oxide semiconductor (PMOS) device. The work function layer 152' is a p-type work function layer. The p-type work function layer is capable of providing a work function value suitable for the device, such as equal to or greater than about 4.8 eV.

[0151] The p-type work function layer can include a metal, a metal carbide, a metal nitride, other suitable material, or combinations of the foregoing. For example, the p-type work function layer includes tantalum nitride, tungsten nitride, titanium nitride, other suitable material, or combinations of the foregoing.

[0152] In some embodiments, the work function layer 152' is used to form an n-type metal-oxide semiconductor (NMOS) device. The work function layer 152' is an n-type work function layer. The n-type work function layer is capable of providing a work function value suitable for the device, such as equal to or less than about 4.5 eV.

[0153] The n-type work function layer can include a metal, a metal carbide, a metal nitride, or a combination of the foregoing. In some embodiments, the n-type work function layer is an aluminum-containing layer. The aluminum-containing layer can be made of, or include, titanium aluminum carbide (TiAlC), titanium aluminum oxide (TiAlO), titanium aluminum nitride (TiAlN), other suitable materials, or a combination of the foregoing.

[0154] The work function layer 152' can also be made of, or include, hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), an aluminide, ruthenium, palladium, platinum, cobalt, nickel, a conductive metal oxide, or a combination of the foregoing. The thickness and / or composition of the work function layer 152' can be fine-tuned to adjust the work function level.

[0155] The work function layer 152' can be deposited over the gate dielectric layer 150 using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, other suitable processes, or a combination of the foregoing.

[0156] In some embodiments, a barrier layer is formed prior to the work function layer 152' to interface the gate dielectric layer 150 with the subsequently formed work function layer 152'. The barrier layer can also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed work function layer 152'. The barrier layer can be made of, or include, a metal-containing material. The metal-containing material can include titanium nitride, tantalum nitride, other suitable materials, or a combination of the foregoing. The barrier layer can be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, other suitable processes, or a combination of the foregoing.

[0157] In some embodiments, different portions of the metal gate stacks 156A and 156B wrap around the semiconductor nanowire structures 104a'-104c' of different elements, including PMOS elements and NMOS elements. The different portions of the metal gate stacks 156A and 156B thus have different types of work function layers or different combinations of work function layers. Multiple deposition processes and multiple patterning processes can be used to selectively form different work function layers at different portions of the metal gate stacks 156A and 156B.

[0158] In some embodiments, the conductive fill 152 is made of, or can include, a metal material. The metal material can include tungsten, aluminum, copper, cobalt, other suitable materials, or a combination of the foregoing. The conductive layer used to form the conductive fill 152 can be deposited over the work function layer 152' using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, a spin-on process, other suitable processes, or a combination of the foregoing.

[0159] In some embodiments, a barrier layer is formed above the work function layer 152' prior to the formation of the conductive layer used to form the conductive filler 152. The barrier layer serves to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function layer 152'. The barrier layer may be made of, or contain, tantalum nitride, titanium nitride, other suitable materials, or combinations thereof. The barrier layer may be deposited using ALD (Alternating Discharge) processes, PVD (Polydiode Deposition) processes, electroplating processes, electroless plating processes, other suitable processes, or combinations thereof.

[0160] Subsequently, according to some embodiments, a planarization process is performed to remove portions of the metal gate stack outside the trench. In this way, the remaining portions of the metal gate stack form metal gate stacks 156A and 156B, as shown. Figure 4C As shown.

[0161] exist Figure 4C During the illustrated process, multiple etching processes and one or more planarization processes are used. A protective cap 402 prevents damage to the dielectric layer 140. In some embodiments, the protective cap 402 is removed or consumed during the planarization process used to form the metal gate stacks 156A and 156B.

[0162] like Figure 4D As shown, according to some embodiments, dielectric layer 140, contact etch stop layer 139, and gate spacers 128' and 126' are partially removed. This exposes the gate dielectric layer 150 extending along the upper sidewall of the metal gate electrode. One or more etching processes can be used to partially remove dielectric layer 140, contact etch stop layer 139, and gate spacers 128' and 126'.

[0163] like Figure 4E As shown, according to some embodiments, the gate dielectric layer 150 is partially removed. One or more etching processes can be used to etch the gate dielectric layer 150. This exposes the sidewalls of the metal gate electrodes previously covered by the gate dielectric layer 150. As shown in Figure 4E, the work function layer 152' is exposed. In some embodiments, each metal gate electrode has a protrusion extending from the top surface of the gate dielectric layer 150, such as... Figure 4E As shown. In some embodiments, the protruding portion includes a portion of conductive filler 152, which is surrounded by the upper portion of work function layer 152', as shown. Figure 4E As shown. In some embodiments, the protruding portion of the metal gate electrode is not laterally surrounded by the gate dielectric layer 150, the gate spacers 126' and 128', the contact etch stop layer 139, and the dielectric layer 140.

[0164] like Figure 4FAs shown, according to some embodiments, a protective structure 404 is formed over the dielectric layer 140 and the epitaxial structure 138. The protective structure 404 laterally surrounds the protruding portion of the metal gate electrode. In some embodiments, the protective structure 404 is in direct contact with the metal gate electrode, the gate dielectric layer 150, and the epitaxial structure 138. In some embodiments, the protective structure 404 is in direct contact with the work function layer 152' and the gate dielectric layer 150, such as... Figure 4F As shown.

[0165] In some embodiments, a protective material layer is deposited over the contact etch stop layer 139, the dielectric layer 140, the metal gate stacks 156A and 156B, and the epitaxial structure 138. The protective material layer may be made of, or contain, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, other suitable materials, or combinations thereof. The protective material layer may be deposited using CVD, ALD, FCVD, other suitable processes, or combinations thereof.

[0166] Subsequently, according to some embodiments, the protective material layer is planarized, thereby exposing the conductive filler 152 of the work function layer 152' and the metal gate electrodes of the metal gate stacks 156A and 156B. The remaining portion of the protective material layer forms the protective structure 404, such as... Figure 4F As shown. CMP, grinding, etching, dry polishing, other suitable processes, or combinations thereof can be used to planarize the protective material layer.

[0167] like Figure 4G As shown, according to some embodiments, a plurality of dielectric structures 406 are formed to divide each of the metal gate stacks 156A and 156B into two or more separate portions. In some embodiments, the separate portions of the metal gate stacks 156A and 156B are physically and / or electrically isolated from each other by the dielectric structures 406. In some embodiments, the dielectric structures 406 extend through the protective structure 404, the metal gate stacks 156A and 156B, the dielectric layer 140, and the contact etch stop layer 139. In some embodiments, the dielectric structures 406 are in direct contact with the protective structure 404 and the metal gate stacks 156A and 156B. In some embodiments, the dielectric structures 406 are in direct contact with the work function layer 152' and the conductive filler 152 of the metal gate stacks 156A and 156B.

[0168] In some embodiments, each dielectric structure 406 includes a protective liner 408 and a dielectric filler 410, such as Figure 4GAs shown. The protective substrate 408 may be made of a substantially oxygen-free dielectric layer. The protective substrate 408 may be made of, or contain, silicon nitride, silicon carbonitride, other suitable materials, or combinations thereof. In some embodiments, the dielectric filler 410 has a lower dielectric constant than the protective substrate 408. The dielectric filler 410 may be made of, or contain, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbonitride, other suitable materials, or combinations thereof. The protective substrate 408 helps prevent oxygen from the dielectric filler 410 from diffusing to the nearby metal gate stacks 156A and 156B. This ensures the quality and reliability of the metal gate stacks 156A and 156B.

[0169] In some embodiments, one or more photolithography processes and one or more etching processes are used to form a plurality of trenches for accommodating the dielectric structure 406. Subsequently, a substrate material layer and a dielectric material layer are sequentially deposited to overfill the trenches. A planarization process is then used to partially remove the substrate material layer and the dielectric material layer. Thus, the remaining portions of the substrate material layer and the dielectric material layer form the dielectric filler 410 protecting the substrate 408 and the dielectric structure 406, respectively. The planarization process may include a CMP process, a polishing process, an etching process, a dry polishing process, other suitable processes, or a combination thereof.

[0170] In some embodiments, due to the presence of a planarization process, the top surfaces of the dielectric structure 406, the metal gate stacks 156A and 156B, the contact etch stop layer 139, and the protective structure 404 are substantially flush, as... Figure 4G As shown. In some embodiments, the bottom of the protective structure 404 is vertically located between the top and bottom of the extension structure 138.

[0171] like Figure 4H As shown, according to some embodiments, in Figure 4G An etch stop layer 411, a dielectric layer 412, and a mask element 414 are sequentially formed on top of the structure shown. The material and formation method of the etch stop layer 411 can be the same as or similar to the material and formation method of the contact etch stop layer 139. The material and formation method of the dielectric layer 412 can be the same as or similar to the material and formation method of the dielectric layer 140. The mask element 414 can be made of, or contain, tungsten carbide or other suitable materials. The etch stop layer 411, dielectric layer 412, and mask element 414 can be formed using CVD, ALD, other suitable processes, or combinations thereof. The mask element 414 can be patterned using one or more photolithography processes and one or more etching processes. In this way, multiple openings are formed in the mask element 414.

[0172] Subsequently, according to some embodiments, portions of the dielectric layer 412 are removed using the mask element 414 as an etch mask. In this way, a plurality of contact openings 416 are formed. The location and profile of the contact openings 416 can be the same as or similar to the location and profile of the mask element 414. The contact openings 416 expose the etch stop layer 411 above the protective structure 404. One or more etching processes can be used to form the contact openings 416. As shown, the protective structure 404 can also protect the underlying dielectric layer 140 during formation of the contact openings 416. Figure 4H

[0173] In some embodiments, an over etching process is used to ensure that the contact openings 416 completely penetrate the dielectric layer 412. In this way, the etch stop layer 411 can be partially removed during the over etching process. In this way, the protective structure 404 is exposed by the contact openings 416. In some embodiments, the protective structure 404 is also partially removed during the over etching process. In some embodiments, the protective structure 404 has a curved upper surface as a result of the over etching process.

[0174] As shown, according to some embodiments, a protective material layer 418 is formed over the dielectric layer 412. The protective material layer 418 extends along the sidewalls and bottom of the contact openings 416. The protective material layer 418 can be used to protect the dielectric layer 412 during subsequent processes. Each protective material layer 418 can have a thickness in the range of about 1 nanometer to about 3 nanometers. Figure 4I

[0175] In some embodiments, the protective material layer 418 is substantially free of oxygen. The protective material layer 418 can be made of, or include, silicon nitride, silicon nitride containing carbon, other suitable materials, or combinations of the foregoing. However, embodiments of the present application have many variations. In some other embodiments, the protective material layer 418 includes oxygen. For example, the protective material layer 418 can be made of, or include, silicon oxynitride, silicon oxynitride containing carbon, other suitable materials, or combinations of the foregoing. In some embodiments, the protective material layer 418 is deposited using a CVD process, an ALD process, other suitable processes, or combinations of the foregoing.

[0176] Figure 4J-1 and Figure 4K-1 are cross-sectional views showing a process for forming a portion of a semiconductor device structure at various stages, according to some embodiments. In some embodiments, Figure 4J-1 is a cross-sectional view of a portion of the structure shown in Figure 4J In some embodiments, Figure 4K-1 is later shown in Figure 4K ​​A cross-sectional view of a portion of the structure shown in the figure.

[0177] like Figure 4J as well as Figure 4J-1 As shown, an anisotropic etching process is used to remove a portion of the protective material layer 418 located at the bottom of the contact opening 416. This leaves the remaining portion of the protective material layer 418 forming multiple protective layers 418'. The protective layers 418' are separated from the epitaxial structure 138 by the protective structure 404.

[0178] In some embodiments, the anisotropic etching process also partially removes the protective structure 404, making the contact opening 416 deeper. In some embodiments, the contact opening 416 exposes the epitaxial structure 138. In some embodiments, the contact opening 416 extends slightly into the epitaxial structure 138, such as... Figure 4J as well as Figure 4J-1 As shown.

[0179] like Figure 4K as well as Figure 4K-1 As shown, according to some embodiments, the epitaxial structure 138 is partially removed. This results in a deeper contact opening 416. The contact opening 416 extends further into the epitaxial structure 138. The contact opening 416 exposes the inner sidewall of the epitaxial structure 138, as... Figure 4K as well as Figure 4K-1 As shown. In some embodiments, a protective layer 418' is formed before the contact opening 416 is deepened. This prevents the protective layer 418' from extending along the inner sidewall of the extension structure 138.

[0180] Subsequently, before forming metal-semiconductor compound elements on the epitaxial structure 138, a cleaning step is performed to clean the exposed surfaces of the epitaxial structure 138. During the cleaning step, the protective layer 418' prevents the dielectric layer 412 from being damaged by the chemicals used in the cleaning step. This maintains the position and outline of the contact opening 416, which facilitates the subsequent formation of conductive contacts within the contact opening 416.

[0181] like Figure 4L As shown, according to some embodiments, a metal-semiconductor compound element 420 is formed on the surface of an epitaxial structure 138 exposed by a contact opening 416. In some embodiments, the metal-semiconductor compound element 420 is embedded in the epitaxial structure 138. The metal-semiconductor compound element 420 can improve the electrical connection between the epitaxial structure 138 and the conductive contacts to be formed on the metal-semiconductor compound element 420. Each metal-semiconductor compound element 420 may have a thickness ranging from about 2 nanometers to about 6 nanometers. Each metal-semiconductor compound element 420 may have a length ranging from about 20 nanometers to about 35 nanometers.

[0182] In some embodiments, prior to forming the metal semiconductor compound element 420, the exposed epitaxial structure 138 is modified to assist in the subsequent formation of the metal semiconductor compound element 420. In some embodiments, one or more ion implantation processes are used to reduce the crystallinity of surface portions of the epitaxial structure 138, which allows a subsequently deposited metal material to more readily react with the modified surface portions. The formation of the metal semiconductor compound element 420 can thus be facilitated.

[0183] In some embodiments, the implantation process is a plasma doping process. A plasma can be introduced into the contact opening 416 to modify the exposed surface portions of the epitaxial structure 138. In some embodiments, the reactive gas used by the implantation process includes a silicon-containing gas, a germanium-containing gas, an argon-containing gas, a helium-containing gas, other suitable gas, or combinations thereof.

[0184] In some embodiments, a heating step is performed after the metal-containing material is applied (or deposited) onto the epitaxial structure 138. In some other embodiments, in accordance with some embodiments, the metal-containing material is applied (or deposited) onto the epitaxial structure 138 while the epitaxial structure 138 is being heated. In some embodiments, a CVD process, an ALD process, or combinations thereof are used to apply (or deposit) the metal-containing material.

[0185] Due to the presence of the heating step, thermal energy can help initiate a chemical reaction between the surface portions of the epitaxial structure 138 and the metal-containing material. As such, the surface portions of the epitaxial structure 138 react with the metal-containing material, and they are converted into the metal semiconductor compound element 420.

[0186] The metal semiconductor compound element 420 can be made of, or include, a metal silicide material, a silicon-germanium-metal-containing material, a germanium-metal-containing material, other suitable material, or combinations thereof. For example, the metal semiconductor compound element 420 includes titanium silicide (TiSi), molybdenum silicide (MoSi), ruthenium silicide (RuSi), zirconium silicide (ZrSi), other suitable material, or combinations thereof.

[0187] In some embodiments, during the heating step, the epitaxial structure 138 is heated to a temperature ranging from approximately 390°C to approximately 440°C. In some other embodiments, the epitaxial structure 138 is heated to a raised temperature before a metallic material is applied to (or deposited on) it. Subsequently, the epitaxial structure 138 is maintained at the raised temperature while the metallic material is applied (or deposited). The raised temperature can be in the range of approximately 390°C to approximately 440°C.

[0188] In some embodiments, when applying or depositing the metal-containing material for forming the metal semiconductor compound element 420, the metal-containing material is also applied to (or deposited on) the sidewalls and bottom surface of the contact opening 416 to form a metal layer. The metal layer may be made of, or contain, titanium, cobalt, ruthenium, molybdenum, nickel, tantalum, tungsten, platinum, other suitable materials, or combinations thereof. In some embodiments, after forming the metal semiconductor compound element 420, portions of the metal layer that have not reacted with the epitaxial structure 138 are removed. One or more etching processes may be used to remove the metal layer. A protective layer 418' may protect the dielectric layer 412 during the etching process.

[0189] However, the embodiments of this invention are not limited thereto. Many variations and / or modifications can be made to the embodiments of this invention. In some other embodiments, the metal-semiconductor compound element 420 is not formed.

[0190] like Figure 4L As shown, according to some embodiments, a conductive contact 422 is formed in a contact opening 416. In some embodiments, the conductive contact 422 completely fills the remaining portion of the contact opening 416, such as... Figure 4L As shown. In some embodiments, the conductive contact 422 penetrates the dielectric layer 412 and the protective structure 404. In some embodiments, the bottom of the conductive contact 422 is located below the top surface of the semiconductor nanostructure 104c', as shown. Figure 4L As shown.

[0191] In some embodiments, the protective layer 418' is formed prior to the formation of the metal-semiconductor compound element 420 and the conductive contact 422. In some embodiments, the presence of the protective structure 404 prevents the protective layer 418' from contacting the epitaxial structure 138. The protective layer 418' does not have a portion located between the conductive contact 422 and the epitaxial structure 138. The electrical connection between the conductive contact 422 and the epitaxial structure 138 is thus significantly improved.

[0192] In some embodiments, a layer of conductive material is deposited over the dielectric layer 412, the protective structure 404, and the metal-semiconductor compound element 420 to overfill the contact openings 416. The layer of conductive material can be made of, or include, tungsten, ruthenium, molybdenum, cobalt, titanium, tantalum, tungsten, other suitable material, or combinations of the foregoing. The layer of conductive material can be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, other suitable process, or combinations of the foregoing.

[0193] Subsequently, according to some embodiments, a planarization process is used to remove the layer of conductive material outside of the contact openings 416. In this way, the remaining portions of the layer of conductive material in the contact openings 416 form conductive contacts 422, as shown. Figure 4L The planarization process can include a CMP process, a grinding process, an etching process, a dry grinding process, other suitable process, or combinations of the foregoing. During the planarization process, portions of the dielectric layer 412 and the protective layer 418' can also be removed.

[0194] Subsequently, one or more dielectric layers and one or more conductive components can be formed over the structure shown. Figure 4L

[0195] In some embodiments, the protective structure 404 protects the underlying dielectric layer 140 during formation of the conductive contacts 422. The portions of the conductive contacts 422 that extend into the dielectric layer 140 can therefore be limited to a limited amount. The area of overlap between nearby conductive contacts 422 can therefore be reduced, which can help to reduce parasitic capacitance. The operating speed and quality of the semiconductor device structure can be improved.

[0196] In some embodiments, each of the conductive contacts 422 has a portion that is laterally surrounded by the protective structure 404 and the dielectric layer 140. The portion of the conductive contacts 422 can have a thickness in a range from about 15 nanometers to about 65 nanometers.

[0197] As shown in Figure 4L The gate dielectric layer 150 having a high dielectric constant does not laterally surround the upper portion of the metal gate electrode. Parasitic capacitance between the metal gate electrode and the conductive contacts 422 can therefore be reduced. The operating speed and quality of the semiconductor device structure can be improved.

[0198] Figure 5 FIGS. 1A-1E are cross-sectional views showing a process for forming a portion of a semiconductor device structure at various stages, according to some embodiments. In some embodiments, Figure 5 is a cross-sectional view of a structure that is the same as, or similar to, the structure shown in Figure 4L Figure 5 The metal gate stack 156C is also shown in ​​

[0199] In some embodiments, the protective layer 418' is spaced apart from the epitaxial structure 138 and is not laterally surrounded by the epitaxial structure 138, such as Figure 4L as well as Figure 5 As shown. Figure 5 As shown, each protective layer 418' is spaced apart from its underlying epitaxial structure 138 by a distance S. The distance S can range from approximately 2 nanometers to approximately 8 nanometers. In some embodiments, each protective layer 418' is in direct contact with its respective nearby protective structure 404. In some embodiments, the length of each metal-semiconductor compound element 420 ranges from approximately 20 nanometers to approximately 35 nanometers.

[0200] like Figure 5 As shown, each conductive contact 422 has an embedded portion laterally surrounded by its respective extensional structure 138. Figure 5 As shown, the embedded portion has a depth D that can range from approximately 1 nanometer to approximately 45 nanometers. In some other embodiments, the conductive contact 422 does not extend into the epitaxial structure 138. Figure 5 As shown, the embedded portion has a width W that can range from approximately 10 nanometers to approximately 16 nanometers.

[0201] like Figure 5 As shown, the gate dielectric layer 150 has a height H1 measured from the top of the gate dielectric layer 150 to the top of the topmost semiconductor nanostructure (e.g., semiconductor nanostructure 104c'). The height H1 can range from about 2 nanometers to about 8 nanometers.

[0202] like Figure 5 As shown, each of the metal gate stacks 156A-156C has a height H2 measured from the top of the metal gate stacks 156A-156C to the top of the topmost semiconductor nanostructure (e.g., semiconductor nanostructure 104c'). The height H2 can range from approximately 10 nanometers to approximately 20 nanometers. Figure 5 As shown, each protective structure 404 has a thickness T. The thickness T can range from about 5 nanometers to about 14 nanometers.

[0203] The dielectric layer 412 has a thickness ranging from approximately 10 nanometers to approximately 20 nanometers. Each dielectric structure 406 has a width ranging from approximately 21 nanometers to approximately 33 nanometers. Each dielectric structure 406 has a depth ranging from approximately 110 nanometers to approximately 160 nanometers.

[0204] Embodiments of the present application can be varied and / or modified in many ways. In some embodiments, a fin bottom isolation structure is formed between the semiconductor fin and the semiconductor substrate 100. The fin bottom isolation structure can be made of, or include, silicon nitride, carbon-containing silicon oxynitride, carbon-containing silicon nitride, carbon-containing silicon oxide, silicon oxide, other suitable materials, or combinations of the foregoing. Each fin bottom isolation structure can have a thickness in a range of about 2 nanometers to about 6 nanometers.

[0205] Embodiments of the present application can be varied and / or modified in many ways. In some embodiments, three channel structures (e.g., semiconductor nanostructures 104a'- 104c') are formed between adjacent epitaxial structures 138. However, embodiments of the present application are not limited in this regard. Embodiments of the present application can be varied and / or modified in many ways. In some embodiments, the total number of semiconductor nanostructures between adjacent epitaxial structures 138 is greater than three. In some other embodiments, the total number of semiconductor nanostructures between adjacent epitaxial structures 138 is less than three. The total number of semiconductor nanostructures (or channel structures) between adjacent epitaxial structures 138 can be fine-tuned to meet requirements. For example, the total number of semiconductor nanostructures between adjacent epitaxial structures 138 can be between 2 and 10. The semiconductor nanostructures can have many suitable profiles. The semiconductor nanostructures can include nanosheets, nanowires, or other suitable nanostructures.

[0206] Embodiments of the present application replace the dielectric elements (including high-k gate dielectric layer) surrounding the upper portion of the metal gate electrode with a protective structure. This can reduce the parasitic capacitance between the metal gate electrode and the conductive contact. The protective layer is formed between the conductive contact and the dielectric layer laterally surrounding the conductive contact. The conductive contact further extends into the epitaxial structure to increase the contact area and reduce the resistance between the conductive contact and the epitaxial structure. The protective layer is blocked by the protective structure. Thus, the protective layer is prevented from contacting the inner sidewall of the epitaxial structure and isolating the conductive contact from the epitaxial structure. Thus, a larger contact area can be maintained between the conductive contact and the epitaxial structure. This can improve the performance and reliability of the semiconductor device structure.

[0207] According to some embodiments, a method of fabricating a semiconductor device structure is provided. The method includes forming a metal gate stack that encloses a plurality of semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode, and the semiconductor nanostructures are adjacent to an epitaxial structure. The method also includes etching back the gate dielectric layer, and after the gate dielectric layer is etched back, a protruding portion of the gate electrode protrudes from a top surface of the gate dielectric layer. The method further includes forming a protective structure over the epitaxial structure, and the protective structure laterally surrounds the protruding portion of the gate electrode. In addition, the method includes forming a conductive contact that is electrically connected to the epitaxial structure and that extends through the protective structure.

[0208] In some embodiments, the method also includes forming a dielectric layer over the metal gate stack, the protective structure, and the epitaxial structure. The method further includes forming a contact opening in the dielectric layer and forming a protective layer over sidewalls of the contact opening, and after the protective layer is formed, the protective structure is partially removed to expose the epitaxial structure. The method also includes forming the conductive contact such that at least a portion of the conductive contact is located in the contact opening. In some embodiments, the method also includes deepening the contact opening such that the contact opening extends into the epitaxial structure after the protective layer is formed, and after the contact opening is deepened, the contact opening extends downward through a top portion of the semiconductor nanostructures. The method further includes forming a metal-semiconductor compound element on the epitaxial structure, and the metal-semiconductor compound element is between the conductive contact and the epitaxial structure, and the metal-semiconductor compound element is separated from the protective structure by the protective layer.

[0209] In some embodiments, the method further includes forming a fin structure over the substrate, and the fin structure has a plurality of semiconductor layers and a plurality of sacrificial layers arranged alternately. The method further includes forming a dummy gate stack extending across the fin structure. The method further includes partially removing the fin structure to form a recess, and the recess exposes a plurality of side surfaces of the semiconductor layers and the sacrificial layers. The method further includes forming an epitaxial structure in the recess. The method further includes forming a second dielectric layer laterally surrounding the epitaxial structure and the dummy gate stack. The method further includes removing the dummy gate stack and the sacrificial layers, wherein a plurality of remaining portions of the semiconductor layers form a semiconductor nanostructure. In some embodiments, the method further includes forming a plurality of gate spacers over a plurality of sidewalls of the dummy gate stack prior to forming the epitaxial structure. The method further includes partially removing the gate spacers and the second dielectric layer after forming the metal gate stack and prior to etching the gate dielectric layer, and partially exposing the gate dielectric layer after partially removing the gate spacers and the second dielectric layer. In some embodiments, the protective structure is formed in direct contact with the gate electrode and the gate dielectric layer.

[0210] According to some embodiments, a method of fabricating a semiconductor device structure is provided. The method includes forming a metal gate stack extending across a semiconductor nanostructure. The metal gate stack has a gate dielectric layer and a gate electrode, and the semiconductor nanostructure is electrically connected to an epitaxial structure. The method further includes removing the gate dielectric layer to expose sidewalls of the gate electrode previously covered by the gate dielectric layer. The method further includes forming a protective structure laterally surrounding the sidewalls of the gate electrode. In addition, the method includes forming a conductive contact electrically connected to the epitaxial structure and extending through the protective structure.

[0211] In some embodiments, the method further includes forming a dielectric layer over the metal gate stack, the protective structure, and the epitaxial structure. The method further includes partially removing the dielectric layer to form an opening exposing the protective structure. The method further includes forming a protective layer over a plurality of sidewalls and a bottom of the opening. The method further includes partially removing the protective layer and the protective structure to expose the epitaxial structure. The method further includes forming a conductive contact electrically connected to the epitaxial structure. In some embodiments, the method further includes partially removing the epitaxial structure after exposing the epitaxial structure and prior to forming the conductive contact. In some embodiments, the method further includes forming a metal-semiconductor compound element on the epitaxial structure prior to forming the conductive contact, and the metal-semiconductor compound element is between the conductive contact and the epitaxial structure. In some embodiments, the protective structure is formed in direct contact with the gate electrode, the gate dielectric layer, and the epitaxial structure.

[0212] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes an epitaxial structure and a semiconductor nanostructure electrically connected to the epitaxial structure. The semiconductor device structure also includes a metal gate stack extending across the semiconductor nanostructure, and the metal gate stack has a gate dielectric layer and a gate electrode. The semiconductor device structure also includes a protective structure over the metal gate stack and the epitaxial structure. A top of the gate dielectric layer is between a top surface of the protective structure and a bottom surface of the protective structure. The top of the gate dielectric layer is closer to the semiconductor nanostructure than a top of the metal gate stack.

[0213] In some embodiments, the semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure, and the conductive contact penetrates the protective structure. In some embodiments, the semiconductor device structure also includes a dielectric layer laterally surrounding an upper portion of the conductive contact and a protective layer between the conductive contact and the dielectric layer. The protective layer is separated from the epitaxial structure by the protective structure. In some embodiments, the semiconductor device structure also includes a dielectric structure separating the metal gate stack into two separate portions. The dielectric structure penetrates the protective structure, and the dielectric structure is in direct contact with the metal gate stack and the protective structure. In some embodiments, a metal semiconductor compound element is embedded in the epitaxial structure.

[0214] The foregoing summary of the embodiments is provided to give the skilled person in the art a better understanding of the nature and substance of the embodiments of the present application. It will be understood by those skilled in the art that they can design or modify other processes and structures based on the embodiments of the present application to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present application, and they can make various changes, substitutions and replacements without departing from the spirit and scope of the present application.

Claims

1. A semiconductor device structure, characterized by, Comprising: an epitaxial structure; a semiconductor nanostructure electrically connected to the epitaxial structure; a metal gate stack extending across the semiconductor nanostructure, wherein the metal gate stack has a gate dielectric layer and a gate electrode; and a protective structure over the metal gate stack and the epitaxial structure, wherein a top portion of the gate dielectric layer is between a top surface of the protective structure and a bottom surface of the protective structure, and the top portion of the gate dielectric layer is closer to the semiconductor nanostructure than a top portion of the metal gate stack.

2. The semiconductor device structure of claim 1, wherein, Further comprising: a conductive contact electrically connected to the epitaxial structure, wherein the conductive contact penetrates the protective structure.

3. The semiconductor device structure of claim 2, wherein, A lower portion of the conductive contact is laterally surrounded by the epitaxial structure.

4. The semiconductor device structure of claim 2, wherein, Further comprising: a dielectric layer laterally surrounding an upper portion of the conductive contact; and a protective layer between the conductive contact and the dielectric layer, wherein the protective layer is separated from the epitaxial structure by the protective structure.

5. The semiconductor device structure of claim 4, wherein, The protective layer is in direct contact with the protective structure.

6. The semiconductor device structure of claim 2, wherein, Further comprising: a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates the protective structure, and the dielectric structure is in direct contact with the metal gate stack and the protective structure.

7. The semiconductor device structure of claim 1, wherein, Further comprising a metal-semiconductor compound element embedded in the epitaxial structure.

8. The semiconductor device structure of claim 1, wherein, The protective structure is in direct contact with the gate electrode, the gate dielectric layer, and the epitaxial structure.

9. The semiconductor device structure of claim 1, wherein, A bottom portion of the protective structure is vertically between a top portion and a bottom portion of the epitaxial structure.

10. The semiconductor device structure of claim 1, wherein, The protective structure has a thickness, and the thickness is in a range of 5 nanometers to 14 nanometers.

Images