Low-resistance high-reliability trench gate silicon carbide VDMOS
By designing a masking layer and buried layer structure in silicon carbide VDMOS devices, the problem of low resistance and high reliability of the devices is solved, the gate corner is protected, and the switching speed and on-resistance performance are improved.
Patent Information
- Application Number
- CN202520146622.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2035-01-22
AI Technical Summary
Existing silicon carbide VDMOS devices have shortcomings in terms of voltage withstand capability, on-resistance, switching speed and reliability, making it difficult to achieve both low resistance and high reliability.
By designing a masking layer and a buried layer structure, the masking layer is distributed directly below the corner of the trench gate to protect the gate, and the buried layer is divided into two parts: the area directly below the gate shields the gate leakage capacitance, and the left and right sides contact the P-type well region to reduce the on-resistance.
This achieves both low resistance and high reliability in the device, protects the gate corner, improves switching speed, and reduces on-resistance.
Smart Images
Figure CN223859533U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of low-resistance high-reliability trench gate silicon carbide VDMOS. BACKGROUND
[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the performance requirements of device are different in different fields, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), lower body diode conduction loss. Low resistance and high reliability can effectively improve the efficiency and reliability of the system based on power device development, so it becomes the goal of device design constantly pursuing. SUMMARY
[0003] The technical problem to be solved by the utility model is to provide a kind of low-resistance high-reliability trench gate silicon carbide VDMOS, which realizes the combination of low resistance and high reliability of device by the design of masking layer and buried layer structure.
[0004] The utility model provides a kind of low-resistance high-reliability trench gate silicon carbide VDMOS, comprising:
[0005] Silicon carbide substrate,
[0006] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, and the first recess is provided in the drift layer;
[0007] Buried layer, the buried layer is provided in the first recess, and the through hole and the second recess are provided in the buried layer;
[0008] Masking layer, the masking layer is provided in the through hole;
[0009] P-type source region, the lower side of the P-type source region is connected to the upper side of the drift layer;
[0010] P-type well region, the lower side of the P-type well region is connected to the upper side of the drift layer and the upper side of the buried layer; the outer side of the P-type well region is connected to the inner side of the P-type source region, and the N-type source region is provided in the P-type well region;
[0011] Insulating dielectric layer, the lower part of the insulating dielectric layer is provided in the second recess, the outer side of the insulating dielectric layer is connected to the inner side of the P-type well region and the inner side of the N-type source region respectively, and the lower side of the insulating dielectric layer is connected to the masking layer and the buried layer; the trench is provided in the insulating dielectric layer;
[0012] Gate metal layer, the gate metal layer is provided in the trench;
[0013] a source metal layer connected to the N-type source region, the P-type well region and the P-type source region, respectively;
[0014] and a drain metal layer connected to the lower side of the silicon carbide substrate.
[0015] The utility model has the advantages of:
[0016] First, the masking layer of the utility model is distributed directly below the device trench gate corner, which can effectively protect the gate reliability problem caused by the concentration of electric field at the trench gate corner;
[0017] Second, the buried layer of the utility model is divided into two parts, one part is distributed in the area directly below the gate, which can shield the gate-drain capacitance, reduce the device gate-drain capacitance and improve the device switching speed, and the other part is distributed on the left and right sides of the device gate and contacts the P-type well region close to the gate insulating medium, which can effectively reduce the on-resistance of the device conduction channel region.
[0018] Third, the structure of the cross-distribution of the masking layer and the buried layer can realize the protection of the trench gate and the reduction of the on-resistance, thereby realizing the combination of low resistance and high reliability. BRIEF DESCRIPTION OF DRAWINGS
[0019] The utility model will be further described in conjunction with the embodiments with reference to the drawings.
[0020] Figure 1 It is the principle diagram of a low-resistance and high-reliability trench gate silicon carbide VDMOS of the utility model.
[0021] Figure 2 It is the process cross section of a low-resistance and high-reliability trench gate silicon carbide VDMOS of the utility model. Figure One .
[0022] Figure 3 It is the process cross section of a low-resistance and high-reliability trench gate silicon carbide VDMOS of the utility model. Figure Two .
[0023] Figure 4 It is the process cross section of a low-resistance and high-reliability trench gate silicon carbide VDMOS of the utility model. Figure Three .
[0024] Figure 5 It is the process cross section of a low-resistance and high-reliability trench gate silicon carbide VDMOS of the utility model. Figure Four .
[0025] Figure 6 It is the process cross section of a low-resistance and high-reliability trench gate silicon carbide VDMOS of the utility model. Figure Five .
[0026] Figure 7 This is a cross-sectional view of the process of a low-resistance, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure Six .
[0027] Figure 8 This is a cross-sectional view of the process of a low-resistance, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure Seven .
[0028] Figure 9 This is a cross-sectional view of the process of a low-resistance, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure Eight .
[0029] Figure 10 This is a cross-sectional view of the process of a low-resistance, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure Nine .
[0030] Figure 11 This is a cross-sectional view of the process of a low-resistance, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure Ten .
[0031] Figure 12 This is a cross-sectional view of the process of a low-resistance, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure Ten one. Detailed Implementation
[0032] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0034] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0035] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0036] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0037] like Figure 1 As shown, this application embodiment provides a low-resistance, high-reliability trench-gate silicon carbide VDMOS, comprising:
[0038] Silicon carbide substrate 101,
[0039] A drift layer 102 is connected to the upper side of the silicon carbide substrate 101, and a first recess 1021 is arranged in the drift layer 102;
[0040] A buried layer 103 is arranged in the first recess 1021, and a via hole 1031 and a second recess (not shown) are arranged in the buried layer 103;
[0041] A mask layer 104 is arranged in the via hole 1031;
[0042] A P-type source region 105 is connected to the upper side of the drift layer 102;
[0043] A P-type well region 106 is connected to the upper side of the drift layer 102 and the upper side of the buried layer 103, and the P-type well region 106 is connected to the inner side of the P-type source region 105, and an N-type source region 1061 is arranged in the P-type well region 106;
[0044] An insulating medium layer 107 is arranged in the second recess, and the outer side of the insulating medium layer 107 is connected to the inner side of the P-type well region 106 and the inner side of the N-type source region 1061, and the lower side of the insulating medium layer 107 is connected to the mask layer 104 and the buried layer 103, and a groove 1071 is arranged in the insulating medium layer 107;
[0045] A gate metal layer 108 is arranged in the groove 1071;
[0046] A source metal layer 109 is connected to the N-type source region 1061, the P-type well region 106 and the P-type source region 105;
[0047] A drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101.
[0048] Preferably, the doping concentration of the P-type source region 105 is greater than the doping concentration of the P-type well region 106, and the doping concentration of the P-type source region 105 is greater than the doping concentration of the drift layer 102.
[0049] Preferably, the doping concentration of the mask layer 104 is greater than the doping concentration of the buried layer 103.
[0050] Preferably, the lower side of the insulating medium layer 107 is connected to the upper side of the mask layer 104.
[0051] In this embodiment, preferably, the upper side of the buried layer 103 is higher than the upper side of the mask layer 104.
[0052] In this embodiment, preferably, the lower side of the gate metal layer 108 is lower than the upper side of the drift layer 102.
[0053] In this embodiment, preferably, the thickness of the P-type source region 105 is equal to that of the P-type well region 106.
[0054] As shown in Figures 1 to 12 The preparation method of the silicon carbide VDMOS includes the following steps:
[0055] Step 1, depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110, and epitaxially growing a drift layer 102 on the upper side of the silicon carbide substrate 101;
[0056] Step 2, forming a barrier layer 111 on the drift layer 102, etching the barrier layer 111 to form a via, and ion implantation to form a mask layer 104;
[0057] Step 3, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a via, and ion implantation to form a buried layer 103;
[0058] Step 4, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a via, and ion implantation to form a P-type well region 106;
[0059] Step 5, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a via, and ion implantation to form a P-type source region 105;
[0060] Step 6, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a via, and ion implantation to form an N-type source region 1061;
[0061] Step 7, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a via, and etching the drift layer 102, the P-type well region 106, the buried layer 103, and the mask layer 104 to form a first recess 1021, oxidizing to form an insulating medium layer 107, and providing a groove 1071 on the insulating medium layer 107;
[0062] Step 8, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a via, and depositing metal to form a gate metal layer 108;
[0063] Step 9, remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a via, and etch the drift layer 102 to the upper side of the P-type well region 106, deposit metal to form the source metal layer 109.
[0064] In another embodiment of the utility model, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 102 is 1-5e16cm -3 , the doping concentration of the P-type mask layer 104 is 8-12e17cm -3 , the doping concentration of the N-type buried layer 103 is 1-5e17cm -3 , the doping concentration of the P-type well region 106 is 1-5e17cm -3 , the doping concentration of the N-type source region 1061 is 2-8e18cm -3 , the doping concentration of the P-type source region 105 is 1-5e19cm -3 , and the material of the insulating medium layer 107 can be silicon dioxide.
[0065] The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 111 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse voltage resistance and the on-resistance of the device; the doping concentration of the P-type well region 106 is mainly considered in two aspects, one is to protect the gate and source structure of the device, and the doping concentration needs to be high, and the other is to ensure that the charge of the gate is small, and the doping concentration needs to be low, and a compromise is made between the two; the main function of the P-type shielding layer 104 is to protect the gate corner of the device from being broken down due to electric field concentration, and not to affect the on-state characteristics of the device, so the doping concentration of the device is relatively high; the doping concentration of the N-type buried layer 103 is mainly to reduce the on-resistance of the device and shield the gate-drain capacitance of the device, in order to reduce the process steps of the device and reduce the manufacturing cost, the doping concentration of the N-type buried layer directly below the gate and on the left and right sides of the device is the same, the doping concentration on the left and right sides of the device gate cannot be too high, otherwise the voltage resistance characteristics of the P-type well region of the device will be affected, and the increase of the doping concentration of the N-type buried layer directly below the device gate can suppress the gate-drain capacitance, and the doping concentration is selected by compromising the process cost; the N-type source region 1061 and the P-type source region 105 are to reduce the ohmic contact resistance of the source of the device without damaging the device lattice and affecting the stability of the device due to high concentration ion implantation;
[0066] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, the thickness of the N-type drift layer 102 is 30-100 μm, which is adjusted within the above range according to different requirements of the voltage resistance characteristics of the device, the thickness of the P-type mask layer 104 is 1 μm, the thickness of the N-type buried layer 103 directly below the gate is also 1 μm, the thickness of the N-type buried layer 103 on the left and right sides of the gate is 1.2 μm, the thickness of the P-type well region 106 below the N-type source region 1061 is 600 nm, the thickness of the P-type well region 106 below the source metal layer 109 is 1 μm, the thickness of the N-type source region 1061 of the device is 400 nm, the thickness of the P-type source region 105 is 1 μm, the thickness of the gate metal layer 108 is 1.22 μm, the thickness of the source metal layer 109 is 300 nm, and the bottom thickness of the insulating medium layer 107 is 80 nm, and the thickness on both sides is 50 nm; the width of the P-type well region 106 accounts for 40-60% of the total width of the device, and the width of the gate metal layer 109 accounts for 20-30% of the total width of the device, so as to ensure the current flow capacity of the parasitic diode of the device, the width of the P-type mask layer 104 of the device accounts for 40-60% of the width of the insulating medium layer 107, so as to ensure that the P-type mask layer 104 protects the gate of the device while inhibiting the parasitic capacitance of the gate to the drain of the device when the voltage of the drain of the device is impacted, and the switching speed of the device is improved; the width of the N-type buried layer 103 on the left and right sides of the gate is 500-1000 nm, which is designed according to the width of the P-type well region 106 controlled by the gate of the device, and the width continues to increase, which cannot improve the conduction characteristics of the device and will affect the voltage resistance characteristics of the device.
[0067] The P-type mask layer 104 of the utility model is distributed directly below the trench gate corner of the device, which can effectively protect the gate reliability problem caused by the electric field concentration at the trench gate corner, the utility model designs the N-type buried layer 103, the N-type buried layer 103 is divided into two parts, one part is distributed in the area directly below the gate, this area can realize the shielding of the gate to drain capacitance, reduce the gate-drain capacitance of the device and improve the switching speed of the device, the other part is distributed on the left and right sides of the gate of the device, and contacts with the P-type well region 106 of the device close to the gate insulating medium layer 107, which can effectively reduce the on-resistance of the conduction channel region of the device, and the structure of the cross-distribution of the P-type mask layer 104 and the N-type buried layer 103 of the device can realize the protection of the trench gate and the reduction of the on-resistance, thereby realizing the combination of low resistance and high reliability.
[0068] Although the specific embodiments of the utility model are described above, those skilled in the art should understand that the specific examples described by us are only illustrative, and are not used to limit the scope of the utility model, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the utility model should be covered within the scope of protection of the claims of the utility model.
Claims
1. A low resistance and high reliability trench-gate silicon carbide VDMOS, characterized in that: The application relates to a silicon carbide substrate, a drift layer connected to the upper side of the silicon carbide substrate, a first recess in the drift layer, a buried layer in the first recess, a via and a second recess in the buried layer, a masking layer in the via, a P-type source region connected to the upper side of the drift layer, a P-type well region connected to the upper side of the drift layer and the upper side of the buried layer, the outer side of the P-type well region connected to the inner side of the P-type source region, an N-type source region in the P-type well region, an insulating medium layer in the second recess, the insulating medium layer connected to the inner side of the P-type well region and the inner side of the N-type source region, the lower side of the insulating medium layer connected to the masking layer and the buried layer, a trench in the insulating medium layer, a gate metal layer in the trench, a source metal layer connected to the N-type source region, the P-type well region and the P-type source region, and a drain metal layer connected to the lower side of the silicon carbide substrate. The doping concentration of the P-type source region is greater than the doping concentration of the P-type well region, and the doping concentration of the P-type source region is greater than the doping concentration of the drift layer. The doping concentration of the masking layer is greater than the doping concentration of the buried layer. The lower side of the insulating medium layer is connected to the upper side of the masking layer. The upper side of the buried layer is higher than the upper side of the masking layer. The lower side of the gate metal layer is lower than the upper side of the drift layer. The thickness of the P-type source region is equal to the thickness of the P-type well region. 2. The low resistance and high reliability trench-gate SiC VDMOS of claim 1, wherein: 3. The low resistance and high reliability trench gate silicon carbide VDMOS of claim 1, wherein: 4. The low resistance and high reliability trench-gate SiC VDMOS of claim 1, wherein: 5. The low resistance and high reliability trench gate silicon carbide VDMOS of claim 1, wherein: 6. The low resistance and high reliability trench gate silicon carbide VDMOS of claim 1, wherein: 7. The low resistance and high reliability trench gate silicon carbide VDMOS of claim 1, wherein: the first and second body regions are formed by implanting a first dopant of a first conductivity type into the substrate; and the first and second body regions are formed by implanting a second dopant of a second conductivity type opposite the first conductivity type into the substrate.