Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device. The array substrate comprises a substrate body, sub-pixels, grid lines and data lines. The sub-pixel comprises a pixel electrode, a common electrode and a transistor, the transistor comprises a grid electrode, a first electrode and a second electrode, and the pixel electrode is electrically connected with the first electrode through a first via hole; each grid line comprises a grid line main body and a lug boss; the second electrode is electrically connected with the data line, and the second electrode comprises a U-shaped structure. The protruding part comprises a first protruding part, the U-shaped structure overlapped with the first protruding part is a first U-shaped structure, the first U-shaped structure comprises two long strips, the outline of orthographic projection of the first protruding part comprises a first edge and a second edge, the first edge is located between the second electrode of the transistor where the first protruding part is located and the first via hole, and the second edge is located between the second electrode of the transistor where the first protruding part is located and the second via hole. The extension direction of the first edge intersects with the long strip, the data line and the grid line, and the second edge passes through the orthographic projection of the data line, so that the width-to-length ratio of the transistor can be increased, and the overlapping area of the grid line and the data line is reduced.

Description

Technical Field

[0001] This utility model relates to an array substrate and a display device. Background Technology

[0002] The development of high-resolution displays in liquid crystal display devices, such as thin-film transistor liquid crystal displays (TFT LCDs), is influenced by factors such as increasing market demand, technological advancements, cost reductions, competitive pressures, and expanding application areas. Utility Model Content

[0003] This invention provides an array substrate and a display device.

[0004] The array substrate provided in this embodiment includes a substrate and a plurality of sub-pixels, a plurality of gate lines, and a plurality of data lines located on the substrate. The plurality of sub-pixels are arranged in an array along a first direction and a second direction. Each sub-pixel includes a pixel electrode, a common electrode, and at least one transistor. Each of the at least one transistor includes a gate, a first electrode, and a second electrode. The pixel electrode is electrically connected to the first electrode through a first via in an insulating layer between itself and the first electrode of a transistor. The plurality of gate lines are arranged along the second direction. Each gate line includes a gate line body extending along the first direction and a plurality of protrusions arranged along the first direction. The plurality of protrusions are located on the same side of the gate line body, and each protrusion serves as the gate of a transistor in the sub-pixel. The plurality of data lines are located on the side of the plurality of gate lines away from the substrate. The plurality of data lines are arranged along the first direction. The second electrode of a transistor in the sub-pixel is electrically connected to a corresponding data line, and the second electrode includes a U-shaped structure. The plurality of protrusions include at least one first protrusion. The U-shaped structure overlapping each first protrusion is a first U-shaped structure. The first U-shaped structure includes two strips extending along a third direction. The first direction intersects with the second direction, and the third direction intersects with both the first and second directions. The outline of the first orthographic projection of each first protrusion on the substrate includes a first side and a second side. The first side is located between the second electrode of the transistor where the first protrusion is located and the first via. The first side extends along a fourth direction, which intersects with the first direction, the second direction, and the third direction. The second side passes through the orthographic projection of the data line on the substrate and extends along the third direction.

[0005] For example, according to an embodiment of the present invention, the outline of the first orthographic projection further includes a third side, which is located between the first side and the second orthographic projection of the gate body on the substrate, and the third side extends along the second direction; the distance between the orthographic projection of the first via on the substrate and the second orthographic projection is greater than the length of the third side.

[0006] For example, according to an embodiment of the present invention, the array substrate further includes: a plurality of touch signal lines located on the side of the common electrode away from the substrate, and the pixel electrode located on the side of the plurality of touch signal lines away from the substrate, the plurality of touch signal lines being arranged along the first direction. At least a portion of the touch signal lines are electrically connected to the film layer containing the common electrode through a second via in the insulating layer between the line and the film layer containing the common electrode, the second via being located between two adjacent first protrusions, and the orthographic projection of the second via on the substrate being located between the second orthographic projection and the orthographic projection of the first via on the substrate.

[0007] For example, according to an embodiment of the present invention, the plurality of touch signal lines do not overlap with the plurality of protrusions along a direction perpendicular to the substrate.

[0008] For example, according to an embodiment of the present invention, the film layer where the common electrode is located includes a signal line connection portion, the signal line connection portion being electrically connected to the touch signal line through the second via, and a straight line extending along the second direction passing through the signal line connection portion and the orthogonal projection of the first electrode of the transistor on the substrate.

[0009] For example, according to an embodiment of the present invention, the length of the second side is greater than the length of the first side, the dimension of the first U-shaped structure in the third direction is greater than the dimension in the fourth direction, and the first U-shaped structure and the data line connected thereto are integrally formed.

[0010] For example, according to an embodiment of the present invention, the orthographic projection of the first via on the substrate is a third orthographic projection, and the straight line extending along the second direction passes through the third orthographic projection and the first edge.

[0011] For example, according to an embodiment of the present invention, the plurality of protrusions further includes at least one second protrusion, and the transistors in the plurality of sub-pixels include at least one first transistor and at least one second transistor. Each first transistor includes a first protrusion, and each second transistor includes a second protrusion. The shape of the first protrusion is different from the shape of the second protrusion, and in the second direction, the maximum size of the first protrusion is greater than the maximum size of the second protrusion.

[0012] For example, according to an embodiment of the present invention, the outline of the fourth orthographic projection of each second protrusion on the substrate includes a fourth side, which is located between the second electrode of the second transistor and the first via, and the fourth side extends along the first direction.

[0013] For example, according to an embodiment of the present invention, the pixel electrode includes a main electrode and a connecting electrode, the connecting electrode being electrically connected to a first electrode in the transistor; the distance between the first protrusion and the main electrode of the pixel electrode connected to the first transistor is a first distance, the distance between the second protrusion and the main electrode of the pixel electrode connected to the second transistor is a second distance, and the first distance is less than the second distance.

[0014] For example, according to an embodiment of the present invention, the first electrode of the first transistor is connected to the connection electrode, the second electrode of the first transistor is connected to the data line, the first electrode of the second transistor is connected to the connection electrode, and the second electrode of the second transistor is connected to the data line; the distance between the connection electrode connected to the same first transistor and the data line is a third distance, and the distance between the connection electrode connected to the same second transistor and the data line is a fourth distance, wherein the third distance is greater than the fourth distance.

[0015] For example, according to an embodiment of the present invention, the second electrode of the first transistor includes the first U-shaped structure, the opening of the first U-shaped structure facing the first via, and the second electrode of the second transistor includes a second U-shaped structure, the opening of the second U-shaped structure facing the protrusion adjacent to it.

[0016] For example, according to an embodiment of the present invention, the extension direction of the portion of the first electrode of the first transistor that does not overlap with the pixel electrode intersects with the first direction, and the portion of the first electrode of the second transistor that does not overlap with the pixel electrode includes a first electrode portion extending along the first direction and a second electrode portion extending along the second direction. Along a direction perpendicular to the substrate, the second electrode portion does not overlap with the second protrusion.

[0017] For example, according to an embodiment of the present invention, the array substrate further includes: a plurality of common electrode lines disposed in the same layer as the plurality of gate lines, the plurality of common electrode lines being arranged along the second direction. Each of at least a portion of the common electrode lines includes a common electrode line body extending along the first direction and at least one common electrode line connection portion arranged along the first direction, the common electrode line connection portion being electrically connected to the common electrode through a third via in the insulating layer between it and the common electrode; a gate line and a common electrode line are disposed between two adjacent rows of sub-pixels arranged in the second direction, the common electrode line being located on the side of the gate line body away from the protrusion, the at least one common electrode line connection portion being located on the side of the common electrode line body away from the gate line, and the straight line extending along the second direction passing through the orthographic projection of the second protrusion and the common electrode line connection portion on the substrate.

[0018] For example, according to an embodiment of the present invention, the array substrate further includes: a plurality of touch signal lines located on the side of the common electrode away from the substrate, the plurality of touch signal lines being arranged along the first direction. At least a portion of the touch signal lines are electrically connected to the film layer containing the common electrode through a second via in the insulating layer between them and the film layer containing the common electrode, the second via being disposed only between the pixel electrode and the gate line body connected to the same first transistor.

[0019] For example, according to an embodiment of the present invention, the array substrate further includes: a plurality of common electrode lines disposed in the same layer as the plurality of gate lines, the plurality of common electrode lines being arranged along the second direction. Each of at least some of the common electrode lines includes a common electrode line body extending along the first direction and at least one common electrode line connection portion arranged along the first direction. The common electrode line connection portion is electrically connected to the common electrode through a third via in the insulating layer between itself and the common electrode. The common electrode line connection portion includes a stepped structure, the stepped structure including at least a first step and a second step connected to each other. In the second direction, the size of the first step is larger than the size of the second step. The orthographic projection of the third via on the substrate includes at least two parts, the first part of which overlaps with the orthographic projection of the stepped structure on the substrate, and the second part of which does not overlap with the orthographic projection of the common electrode line on the substrate.

[0020] For example, according to an embodiment of the present invention, the orthographic projection of the common electrode on the substrate overlaps with the second portion, and the portion of the common electrode located in the third via includes a portion disposed in the same layer as the common electrode line.

[0021] For example, according to an embodiment of the present invention, the array substrate further includes: a plurality of touch signal lines located on the side of the common electrode away from the substrate, the plurality of touch signal lines being arranged along the first direction. At least a portion of the touch signal lines are electrically connected to the film layer containing the common electrode through a second via in the insulating layer between them and the film layer containing the common electrode; the film layer containing the plurality of touch signal lines includes a first common conductive layer, the film layer containing the pixel electrode includes a second common conductive layer, the first common conductive layer and the second common conductive layer are stacked and in direct contact, and the first common conductive layer and the second common conductive layer cover the portion of the common electrode and the common electrode line located in the third via.

[0022] For example, according to an embodiment of the present invention, a common electrode connection portion is provided between the common electrodes of at least two adjacent sub-pixels arranged along the second direction. The common electrode connection portion is configured to connect adjacent common electrodes. The common electrode connection portion is located between two adjacent data lines. The common electrode connection portion includes a first connection portion, a second connection portion, and a third connection portion arranged sequentially along the second direction. The first connection portion is located between the first electrode and the data line. The second connection portion is located between two adjacent protrusions. The third connection portion overlaps with the gate line body. In the first direction, the size of the first connection portion and the size of the third connection portion are both smaller than the size of the second connection portion.

[0023] For example, according to an embodiment of the present invention, the array substrate further includes: a plurality of touch signal lines located on the side of the common electrode away from the substrate, the plurality of touch signal lines being arranged along the first direction. At least a portion of the touch signal lines are electrically connected to the second connection portion through a second via in the insulating layer between them and the second connection portion.

[0024] For example, according to an embodiment of the present invention, the first connecting portion and the third connecting portion are staggered in the first direction, and a straight line extending along the second direction passes through the orthographic projection of the first pole, the second connecting portion and the third connecting portion on the substrate.

[0025] For example, according to an embodiment of the present invention, the film layer where the pixel electrode is located includes a conductive portion disposed at a distance from the pixel electrode, and the conductive portion is stacked and in direct contact with the plurality of touch signal lines.

[0026] For example, according to an embodiment of the present invention, the outline of the orthographic projection of the first via on the substrate includes a chamfer.

[0027] For example, according to an embodiment of the present invention, the outline of the orthographic projection of the second via on the substrate includes a chamfer.

[0028] For example, according to an embodiment of the present invention, the outline of the orthographic projection of the third via on the substrate includes a chamfer.

[0029] For example, according to an embodiment of the present invention, the two ends of the first side are respectively connected to the second side and the third side, and the outline of the first orthographic projection also includes a fifth side connected to the second side, the fifth side being parallel to the third side; the included angle between the second side and the fifth side is a first included angle, the included angle between the first side and the third side is a second included angle, and the first included angle is smaller than the second included angle.

[0030] Another embodiment of the present invention provides a display device, including the array substrate described in any of the above embodiments.

[0031] For example, according to an embodiment of the present invention, the display device further includes: a counter substrate disposed opposite to the array substrate; and a liquid crystal layer located between the array substrate and the counter substrate.

[0032] This invention provides an array substrate and a display device in which the second electrode of the transistor is configured to have a U-shaped structure, and the shape of the first protrusion overlapping with the U-shaped structure is configured such that the second side of its orthogonal projection passes through the orthogonal projection of the data line on the substrate. This is beneficial to increase the aspect ratio of the transistor while reducing the probability of electrostatic puncture between the first protrusion and the data line, and reducing the overlapping area of ​​the gate line and the data line. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only involve some embodiments of this utility model, and are not intended to limit this utility model.

[0034] Figure 1 This is a partial planar structure diagram of the array substrate provided according to an embodiment of the present invention.

[0035] Figure 2A This is a schematic diagram of a partial planar structure of the gate lines in a typical array substrate.

[0036] Figure 2B for Figure 1 A magnified view of a portion of region A shown.

[0037] Figure 3A This is a schematic diagram of the film layer where the grid lines are located.

[0038] Figure 3B It shows Figure 3A A magnified view of a local area of ​​the common electrode line (B).

[0039] Figures 4 to 6A for Figure 2B A partial layer stack diagram of the membrane layers in the shown area.

[0040] Figure 6B It shows Figure 6A Enlarged view C of the common electrode line and the third via.

[0041] Figures 7 to 9 for Figure 2B A partial layer stack diagram of the membrane layers in the shown area.

[0042] Figure 10 For along Figure 2B A schematic diagram of the local cross-section structure intercepted by line DD'.

[0043] Figure 11 For along Figure 2B A schematic diagram of the partial cross-sectional structure cut by line EE'.

[0044] Figure 12 for Figure 1 A magnified view of a portion of the film layer in region F shown.

[0045] Figure 13 This is a partial planar structure schematic diagram of an array substrate provided according to another example of an embodiment of the present utility model.

[0046] Figure 14 This is a partial structural schematic diagram of a display device according to another embodiment of the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the described embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0048] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0049] The features "parallel," "perpendicular," and "identical" used in this embodiment of the invention include the strictly defined meanings of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" contain a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value. Unless otherwise specified in the following embodiments of the invention, the quantity of a component is implied to mean that the component can be one or more, or can be understood as at least one. "At least one" refers to one or more, and "more" refers to at least two.

[0050] With the widespread adoption and performance improvements of electronic products such as smartphones, tablets, laptops, televisions, and emerging smart wearable devices and in-vehicle display systems, consumers are demanding increasingly higher image quality from LCD displays. High-resolution LCD screens can provide a more detailed and clearer image and video experience, satisfying users' pursuit of a high-quality visual experience.

[0051] In recent years, advancements in TFT LCD technology, such as backlighting, color management, driving circuit optimization, and materials science, have significantly improved TFT LCDs in terms of resolution, color saturation, contrast, and viewing angle. These technological advancements have made it possible for TFT LCDs to achieve even higher resolutions.

[0052] With the rapid development of emerging fields such as the Internet of Things, smart homes, and smart wearable devices, consumers have increasingly higher demands for the interactivity of smart terminal products. TFT LCD screens with integrated touch functionality can provide a more intuitive and convenient operating experience, meeting users' needs for a smart and convenient lifestyle. Especially in areas such as automotive center console screens, smart home control panels, and industrial control terminals, touch-sensitive TFT LCD displays have become the mainstream choice. A key feature is the in-cell touch technology, which embeds the touch panel function into the liquid crystal pixels, directly embedding the touch sensor inside the display screen. This reduces the number of layers in the touch screen, making it thinner and lighter. This slim design not only improves the portability of the device but also makes it more aesthetically pleasing.

[0053] In the fabrication of TFT LCDs, either a "1+4" mask process or a "0+4" mask process can be used. In the "1+4" or "0+4" mask process, "0" and "1" refer to whether a mask is used to form the first layer of indium tin oxide (1ITO), with "0" indicating no and "1" indicating yes. The "1+4" mask process refers to a mask process that forms 1ITO, a gate layer, an active layer, source / drain metal layers, a passivation layer including vias, and a second layer of indium tin oxide (2ITO). The active layer and source / drain metal layers are formed simultaneously using a halftone mask process.

[0054] Traditional "1+4" or "0+4" mask processes simplify the production process by reducing masking steps, which helps to shorten the production cycle and improve overall production efficiency. The "1+4" mask process is the mainstream manufacturing process. Due to process limitations, when using a halftone mask process to simultaneously form the active layer and source / drain metal layers, an active layer protrusion (referred to as an active tail) will exist at the edge of the active layer. Similarly, when using a halftone mask process to simultaneously form the first indium tin oxide (ITO) layer and the gate layer, a protrusion (referred to as an ITO tail) will exist at the edge of the first ITO layer.

[0055] In their research, the inventors of this application discovered that, according to general manufacturing processes, the size of the aforementioned Tail is typically around 2μm. For display devices with a high pixel density (PPI), a Tail with a size of 2μm has a relatively small impact on the aperture ratio; however, for display devices with a high PPI, the impact of a Tail with a size of 2μm on the aperture ratio cannot be ignored.

[0056] In touch and display driver integration (TDDI) display devices, a touch signal line Tx is provided in the display area. This touch signal line Tx is used to transmit the common signal Vcom during the display phase and to detect capacitance changes within the sensor during the touch phase, such as for transmitting touch signals. For display devices with high PPI, the placement of the touch line Tx must consider not only touch performance but also its impact on the aperture ratio.

[0057] This invention provides an array substrate and a display device. The array substrate includes a substrate and a plurality of sub-pixels, a plurality of gate lines, and a plurality of data lines located on the substrate. The plurality of sub-pixels are arranged in an array along a first direction and a second direction. Each sub-pixel includes a pixel electrode, a common electrode, and at least one transistor. Each of the at least one transistor includes a gate, a first electrode, and a second electrode. The pixel electrode is electrically connected to the first electrode through a first via in an insulating layer between itself and the first electrode of a transistor. The plurality of gate lines are arranged along the second direction. Each gate line includes a gate line body extending along the first direction and a plurality of protrusions arranged along the first direction. The plurality of protrusions are located on the same side of the gate line body, and each protrusion serves as the gate of a transistor in the sub-pixel. The plurality of data lines are located on the side of the plurality of gate lines away from the substrate. The plurality of data lines are arranged along the first direction. The second electrode of a transistor in the sub-pixel is electrically connected to the corresponding data line, and the second electrode includes a U-shaped structure. The plurality of protrusions include at least one first protrusion, and the U-shaped structure overlapping each first protrusion is a first U-shaped structure. The first U-shaped structure includes two strips extending along a third direction, and the third direction intersects both the first direction and the second direction. The outline of the first orthographic projection of each first protrusion on the substrate includes a first side and a second side. The first side is located between the second electrode of the transistor where the first protrusion is located and the first via. The first side extends along a fourth direction, and the fourth direction intersects the first direction, the second direction and the third direction. The second side passes through the orthographic projection of the data line on the substrate and extends along the third direction.

[0058] In the array substrate provided by this utility model, the second pole of the transistor is configured to have a U-shaped structure, and the shape of the first protrusion overlapping with the U-shaped structure is configured such that the second side of its orthogonal projection passes through the orthogonal projection of the data line on the substrate. This is beneficial to increase the aspect ratio of the transistor while reducing the probability of electrostatic puncture between the first protrusion and the data line, and reducing the overlapping area between the gate line and the data line.

[0059] The array substrate and display device provided in the embodiments of this utility model are described below with reference to the accompanying drawings.

[0060] Figure 1 This is a partial planar structure diagram of the array substrate provided according to an embodiment of the present invention. Figure 2B for Figure 1 A magnified view of a portion of region A shown. Figure 3A , Figures 4 to 6A , Figures 7 to 9 for Figure 2B The layer stack diagram of each film layer in the shown area. Figure 3A This is a schematic diagram of the film layer where the grid lines are located. Figure 3B It shows Figure 3A A magnified view of a local area of ​​the common electrode line (B).

[0061] like Figures 1 to 3A As shown, the array substrate includes a substrate 01 and a plurality of sub-pixels 100, a plurality of gate lines 200, and a plurality of data lines 300 located on the substrate 01. The plurality of sub-pixels 100 are arranged in an array along a first direction and a second direction. Each sub-pixel 100 includes a pixel electrode 110, a common electrode 120, and at least one transistor 130. Each of the at least one transistor 130 includes a gate 133, a first electrode 131, and a second electrode 132. The pixel electrode 110 is electrically connected to the first electrode 131 through a first via 141 in the insulating layer between itself and the first electrode 131 of a transistor 130.

[0062] For example, such as Figure 1 As shown, the first direction can be the X direction, and the second direction can be the Y direction, but is not limited to these; the first and second directions can be interchanged. For example, the angle between the first and second directions can be 80 to 100 degrees, such as when the first direction is perpendicular to the second direction.

[0063] For example, such as Figure 2B As shown, each sub-pixel 100 may include a pixel electrode 110, and at least two sub-pixels 100 may share a common electrode 120. For example, both the pixel electrode 110 and the common electrode 120 may be made of a light-transmitting and conductive material. For example, both the pixel electrode 110 and the common electrode 120 may be made of indium tin oxide (ITO).

[0064] For example, such as Figure 1 , Figure 2B and Figure 9 As shown, the pixel electrode 110 can be located on the side of the common electrode 120 away from the substrate 01.

[0065] Figure 2B This illustration schematically shows that each subpixel includes one transistor, but is not limited to this; each subpixel may also include two or more transistors. For example, different subpixels may include the same number of transistors.

[0066] For example, such as Figure 2B As shown, each sub-pixel 100 includes a transistor 130, which can be a thin-film transistor. The first electrode 131 of the transistor 130 can be the drain, and the second electrode 132 can be the source. The first electrode 131 is electrically connected to the pixel electrode 110, and the second electrode 132 is electrically connected to the data line 300. For example, the insulating layer including the first via 141 can be a passivation layer (PVX).

[0067] like Figure 1 and Figure 2BAs shown, multiple gate lines 300 are arranged along a second direction. Each gate line 300 includes a gate line body 210 extending along a first direction and multiple protrusions 220 arranged along the first direction. The multiple protrusions 220 are located on the same side of the gate line body 210, and each protrusion 220 serves as the gate 133 of the transistor 130 in the sub-pixel 100.

[0068] For example, such as Figure 2B and Figure 3A As shown, the gate line body 210 and the plurality of protrusions 220 are integrally formed, such as when the gate and the gate line body are integrally formed. For example, Figure 3A The gate line body 210 and the protrusion 220 in the gate line are schematically divided by dashed lines. The gate line body 210 can be an elongated structure extending along a first direction, and the protrusion 220 is a structure that protrudes relative to the edge of the elongated structure. For example, each protrusion 220 serves as the gate 133 of the transistor 130 to achieve electrical connection with the gate line 200.

[0069] like Figures 1 to 5 As shown, multiple data lines 300 are located on the side of multiple gate lines 200 away from the substrate 01. The multiple data lines 300 are arranged along a first direction. The second pole 132 of a transistor 130 in the sub-pixel 100 is electrically connected to the corresponding data line 300, and the second pole 132 includes a U-shaped structure.

[0070] For example, such as Figure 1 and Figure 2B As shown, multiple data lines 300 and multiple gate lines 200 are intersected to define the area where the sub-pixel 100 is located, and each area includes one sub-pixel 100. The gate 133 of the transistor 130 is connected to the gate line 200 to control the transistor 130 to turn on or off. The data lines 300 input the voltage signal required for displaying the image to the pixel electrode 110 through the transistor 130 to realize the display of the display device including the array substrate.

[0071] like Figures 2B to 5 As shown, the plurality of protrusions 220 include at least one first protrusion 221, and the U-shaped structure overlapping each first protrusion 221 is a first U-shaped structure 1310. The first U-shaped structure 1310 includes two strips 1300 extending along a third direction, and the third direction intersects with both the first direction and the second direction.

[0072] For example, such as Figure 5 As shown, the third direction can be the U direction, the third direction has an angle greater than 0 degrees with the first direction, and the third direction has an angle greater than 0 degrees with the second direction.

[0073] In some examples, such as Figure 5As shown, the first U-shaped structure 1310 and the data line 300 connected thereto are integrated into one structure. Figure 5 The outline of the portion of the first U-shaped structure 1310 integrated with the data line 300 is schematically shown using dashed lines. The two strips 1300 included in the first U-shaped structure 1310 can be two portions extending in a third direction other than the data line 300. For example, the two strips 1300 included in the same first U-shaped structure 1310 can have the same length or different lengths. For example, the two strips 1300 can be a first strip and a second strip, with the first strip located on the side of the second strip away from the main body of the gate line, or the length of the first strip being less than the length of the second strip. For example, the first strips included in different first U-shaped structures 1310 have the same length, and the second strips included in different first U-shaped structures 1310 have the same length.

[0074] Figure 3A This is a structural diagram of the film layer containing gate line 200. The planar shape of the film layer in this structural diagram is basically the same as the shape of its orthographic projection onto the substrate 01. Figure 3A It can also represent the orthographic projection view of the film layer where the gate line 200 is located on the substrate 01.

[0075] like Figure 2B and Figure 3A As shown, the outline of the first orthographic projection 2210 of each first protrusion 221 on the substrate 01 includes a first side 2211 and a second side 2212. The first side 2211 is located between the second electrode 132 of the transistor 130 where the first protrusion 221 is located and the first via 141. The first side 2211 extends along a fourth direction, which intersects with the first direction, the second direction and the third direction. The second side 2212 passes through the orthographic projection of the data line 300 on the substrate 01 and extends along a third direction.

[0076] Figure 2A This is a schematic diagram of a partial planar structure of gate lines in a typical array substrate. (Example:) Figure 2A As shown, the gate line includes a gate line body 020 extending along a first direction and a plurality of gates 021 located on the gate line body 020. The outline of the gate 021 projected onto the substrate 01 includes an edge 023 extending along the first direction and an edge 024 extending along a second direction, such as edge 023 being the edge close to the sub-pixel. Figure 2A The pattern of gate 021 shown can be called a regular pattern. Figure 2A When the gate pattern shown is applied to a display device with a high PPI, the vias connecting the pixel electrodes and the vias connecting the control signal lines will occupy more space, resulting in a decrease in the pixel aperture ratio.

[0077] Compared to including Figure 2AIn the array substrate of the gate shown, the array substrate provided by this utility model, by setting the shape of the first protrusion 221 to include a first side 2211 and a second side 2212 whose extension direction intersects both the first direction and the second direction, space is reserved for the vias connecting the pixel electrode 110 and the control signal line 400, which is beneficial to improving the aperture ratio of the sub-pixel 100. Furthermore, in this embodiment of the utility model, the second electrode 132 of the transistor is set to have a U-shaped structure, and the shape of the first protrusion 221 overlapping with the U-shaped structure is set such that the second side 2212 in its orthographic projection passes through the orthographic projection of the data line 300 on the substrate 01. This is beneficial to increase the aspect ratio of the transistor while reducing the probability of electrostatic puncture between the first protrusion 221 and the data line 300, and reducing the overlap area between the gate line and the data line 300.

[0078] For example, such as Figure 2B and Figure 3A As shown, the angle between the third direction and the fourth direction can be 80 to 100 degrees, such as the third direction being perpendicular to the fourth direction. However, this embodiment is not limited to this; the third direction and the fourth direction can be interchanged.

[0079] For example, such as Figure 2B and Figure 3A As shown, the orthographic projection of the data line 300 on the substrate 01 does not overlap with the first side 2211. For example, the first side 2211 and the second side 2212 can be two connected sides, and the connection point of the first side 2211 and the second side 2212 does not overlap with the orthographic projection of the data line 300 on the substrate 01 to avoid the aforementioned connection point generating a tip discharge at the location of the data line 300 and breaking down the insulating layer.

[0080] For example, such as Figure 2B and Figure 3A As shown, the orthographic projection of the first strip of the first U-shaped structure 1310 onto the substrate 01 is closer to the second side 2212 than the orthographic projection of the second strip onto the substrate 01.

[0081] In some examples, such as Figure 2B and Figure 3A As shown, the outline of the first orthographic projection 2210 also includes a third side 2213, which is located between the first side 2211 and the second orthographic projection of the gate body 210 on the substrate 01, and the third side 2213 extends along the second direction; the distance between the orthographic projection of the first via 141 on the substrate 01 and the second orthographic projection is greater than the length of the third side 2213.

[0082] By setting the length relationship, extension direction and position of the first side 2211, the second side 2212 and the third side 2213 in the orthographic projection outline of the first protrusion 221, it is beneficial to ensure the function of the gate 133 while improving the layout space utilization, such as reserving space for the vias connecting the pixel electrode 110 and the vias connecting the control signal line 400, thereby increasing the aperture ratio of the sub-pixel.

[0083] In some examples, such as Figure 2B and Figure 3A As shown, the orthographic projection of the first via 141 on the substrate 01 is the third orthographic projection, and the straight line L1 extending along the second direction passes through the third orthographic projection and the first side 2211.

[0084] Figure 2B The schematic diagram illustrates the stacked structure of each film layer in the array substrate. The third orthographic projection of the first via 141 on the substrate 01 can be compared with... Figure 2B The first via 141 shown has a substantially the same shape and can be Figure 2B The first via 141 shown can be illustrated as its third orthographic projection on the substrate 01.

[0085] By setting the relative positional relationship between the first side 2211 and the first via 141 in the orthographic projection contour of the first protrusion 221, it is beneficial to reduce the distance between the first side 2211 and the first via 141, provide space for the via of the subsequent contact control signal line 400, and increase the aperture ratio of the sub-pixel.

[0086] For example, such as Figure 2B and Figure 3A As shown, the third side 2213 connects the first side 2211 to the outline of the second orthographic projection of the gate body 210. For example, the extension of the third side 2213 passes through the orthographic projection of the first via 141 on the substrate 01.

[0087] For example, such as Figure 3A As shown, the angle between the first side 2211 and the second side 2212 is smaller than the angle between the first side 2211 and the third side 2213, which helps to make the first protrusion 221 have a larger area while avoiding affecting the position of the subsequent connection via.

[0088] In some examples, such as Figure 2B and Figure 3A As shown, the length of the second side 2212 is greater than the length of the first side 2211, and the dimension of the first U-shaped structure 1310 in the third direction is greater than the dimension in the fourth direction.

[0089] By setting the lengths of different sides of the first protrusion 221 to match the shape of the first U-shaped structure 1310 that overlaps with it, it is beneficial to improve the width-to-length ratio of the transistor channel.

[0090] In some examples, such as Figure 3A As shown, the two ends of the first side 2211 are connected to the second side 2212 and the third side 2213 respectively. The outline of the first orthographic projection 2210 also includes a fifth side 2215 connected to the second side 2212. The fifth side 2215 is parallel to the third side 2213. The angle between the second side 2212 and the fifth side 2215 is the first angle α1, and the angle between the first side 2211 and the third side 2213 is the second angle α2. The first angle α1 is smaller than the second angle α2.

[0091] By setting the first included angle to be smaller than the second included angle, it is beneficial to increase the distance between the apex of the connection between the first and second sides and the data line, thereby reducing the capacitance between the apex and the data line. The smaller the first included angle, the greater the distance between the apex and the data line.

[0092] For example, such as Figure 3A As shown, the length of the fifth side 2215 is less than the length of the third side 2213. For example, the fifth side 2215 connects the second side 2212 with the outline edge of the second orthographic projection. For example, the first included angle between the second side 2212 and the fifth side 2215 is greater than the included angle between the second side 2212 and the first side 2211.

[0093] For example, such as Figure 2B and Figure 3A As shown, multiple protrusions 220 in the same gate line 200 can all be first protrusions 221. For example, the first protrusions 221 in the same gate line can be arranged at equal intervals. For example, the same number of protrusions 220 can be provided in different gate lines 200. For example, the protrusions 220 in all gate lines 200 can be arranged in an array along a first direction and a second direction. For example, the protrusions 220 in all gate lines 200 can all be first protrusions 221.

[0094] In some examples, such as Figures 1 to 3A As shown, the array substrate also includes: multiple common electrode lines 500, which are disposed on the same layer as multiple gate lines 200, and the multiple common electrode lines 500 are arranged along the second direction.

[0095] Figure 3A The common electrode line 500 is schematically shown to have a break, with two portions of the common electrode line 500 on either side of the break configured to be electrically connected to touch signal lines 400 that transmit different touch signals. For example, the common electrode line can transmit a common signal during the display phase and a touch signal during the touch phase.

[0096] For example, such as Figure 4 As shown, after patterning the gate line 200 and the common electrode line 500, an insulating layer is covered on the gate line 200, and then a semiconductor pattern 134 is patterned on the insulating layer. The semiconductor pattern 134 serves as the active layer pattern of the transistor 130. For example, the semiconductor pattern 134 may include a generally U-shaped form.

[0097] For example, such as Figure 5 As shown, a data line 300 and a first electrode 131 and a second electrode 132 of a transistor are patterned on the side of the semiconductor pattern 134 away from the gate line 200. For example, Figure 4 Semiconductor pattern 134 and shown Figure 5 The data line 300 and the first electrode 131 and the second electrode 132 of the transistor shown are formed in the same patterning process using a halftone mask.

[0098] In some examples, such as Figures 3A to 6A As shown, each of the at least some of the common electrode lines 500 includes a common electrode line body 510 extending along a first direction and at least one common electrode line connection portion 520 arranged along the first direction. The common electrode line connection portion 520 is electrically connected to the common electrode through a third via 143 in the insulating layer between it and the common electrode 120.

[0099] For example, such as Figure 3A As shown, the common electrode line body 510 and the common electrode line connection portion 520 are integrally formed. For example, Figure 3A The common electrode line body 510 and the common electrode line connection portion 520 in the common electrode line 500 are schematically divided by dashed lines. The common electrode line body 510 can be a long strip structure extending along the first direction, and the common electrode line connection portion 520 is a structure that protrudes from the edge of the long strip structure.

[0100] In some examples, such as Figure 3A and Figure 3B As shown, the common electrode line connection portion 520 includes a stepped structure, which includes at least a first step 521 and a second step 522 connected to each other. In a second direction, the size of the first step 521 is larger than the size of the second step 522. For example, the first step 521 protrudes relative to the second step 522 in a direction away from the common electrode line body 510. Figure 3A and Figure 3B The step structure is schematically shown to include two steps, such as the first step 521 and the second step 522.

[0101] Figure 6AThe diagram illustrates vias in an organic insulating layer disposed on the side of the film layer containing the data line 300 away from the film layer containing the gate line 200. For example, the organic insulating layer contains a via 144 exposing the first electrode 131 of the transistor 130 and a third via 143 exposing the common electrode line connection portion 520. For instance, via 144 includes a portion exposing the first electrode 131 and a portion that does not overlap with the first electrode 131. This portion that does not overlap with the first electrode 131 is connected by a bridging conductive structure 423 in the film layer containing the subsequently formed touch signal line 400. Figure 9 (As shown) Coverage.

[0102] Figure 6B It shows Figure 6A Enlarged view C of the common electrode line and the third via.

[0103] In some examples, such as Figure 6A and Figure 6B As shown, the orthographic projection of the third via 143 on the substrate 01 includes at least two parts. The first part 1431 of the two parts overlaps with the orthographic projection of the stepped structure on the substrate 01, while the second part 1432 of the two parts does not overlap with the orthographic projection of the common electrode line 500 on the substrate 01.

[0104] By setting the common electrode line connection portion 520 to have a stepped structure, the portion of the common electrode line connection portion 520 exposed by the third via 143 can be effectively guaranteed. Furthermore, by setting the common electrode line 500 to include the common electrode line connection portion 520 with a stepped structure and the common electrode line body 510 with an elongated shape, the influence of the common electrode line on the opening ratio can be reduced.

[0105] Figure 6B A planar schematic diagram of the third via 143 and the common electrode line 500 is shown. The shape of this schematic diagram is approximately the same as the orthographic projection of the third via 143 and the common electrode line 500 onto the substrate 01. Figure 6B The orthographic projection relationship between the third via 143 and the common electrode line 500 can also be shown.

[0106] In some examples, such as Figure 6B As shown, the outline of the orthogonal projection of the third via 143 on the substrate 01 includes a chamfer.

[0107] By setting the third via 143 to have a chamfered shape, the smoothness at the included angle of the third via 143 is improved, preventing the conductive layer formed in the third via 143, such as the common electrode, from breaking at the included angle.

[0108] For example, such as Figure 6BAs shown, the shape of the orthographic projection of the third via 143 can be a quadrilateral with chamfers. The chamfers in the same third via 143 have the same size, and the chamfers in different third vias 143 have the same size. Figure 6B The outline of the orthographic projection of the third via 143 is schematically shown, including a straight chamfer, but it is not limited to this; the chamfer can also be a rounded chamfer.

[0109] For example, such as Figure 6B As shown, d1 and d2 are both not less than the resolution of the exposure machine, such as d1 and d2 being not less than 3 micrometers.

[0110] For example, such as Figure 7 As shown, a film layer containing the common electrode 120 is formed on the side of the organic insulating layer away from the film layer containing the data line 300. For example, the material used for this film layer can be indium tin oxide (ITO).

[0111] For example, such as Figure 7 As shown, whether the common electrode 120 in adjacent sub-pixels 100 is electrically connected depends on the position of the touch area, and the common electrode 120 of sub-pixels 100 located in different touch areas is insulated.

[0112] In some examples, such as Figure 7 As shown, the film layer where the common electrode 120 is located includes a signal line connection portion 410.

[0113] For example, such as Figure 7 As shown, when the common electrodes 120 of adjacent sub-pixels 100 arranged along the second direction are insulated, a signal line connection portion 410 is provided between the common electrodes 120 of the adjacent sub-pixels 100. For example, the signal line connection portion 410 is located between two adjacent protrusions 220. For example, the signal line connection portion 410 is located between two adjacent first protrusions 221. For example, the distance between the signal line connection portion 410 and the two first protrusions 221 located on both sides thereof is substantially equal.

[0114] For example, such as Figure 7 As shown, in the second direction, the size of the signal line connection portion 410 is smaller than the size of the first protrusion portion 221.

[0115] In some examples, such as Figure 7 As shown, the straight line L2 extending along the second direction passes through the signal line connection portion 410 and the first electrode 131 of the transistor 130 and is projected onto the substrate 01 in an orthogonal manner. For example, the straight line L2 passes through the signal line connection portion 410 and the via 144 and is projected onto the substrate 01 in an orthogonal manner.

[0116] By setting the shape of the first protrusion 221 and the relative positional relationship between the first protrusion 221, the first electrode 131 of the transistor 130 and the via exposing the first electrode 131, it is beneficial to provide space for the signal line connection portion 410, thereby improving the pixel aperture ratio.

[0117] For example, such as Figure 7 As shown, along a direction perpendicular to the substrate 01, the common electrode 120 overlaps with the third via 143. The common electrode 120 includes electrodes located in a first portion 1431 and a second portion 1432 of the third via 143 to achieve electrical connection with the common electrode line 500. For example, the portion of the common electrode 120 located in the second portion 1432 of the third via 143 is disposed on the same layer as the common electrode line 500.

[0118] By configuring the third via 143 to include a first portion 1431 that overlaps with the common electrode line 500 and a second portion 1432 that does not overlap with the common electrode line 500, it is beneficial to improve the diffusion effect of the liquid crystal alignment film and prevent poor liquid crystal alignment.

[0119] For example, such as Figure 7 As shown, the first portion 1431 of the third via 143 includes a portion that does not overlap with the common electrode 120.

[0120] For example, such as Figure 7 As shown, along the direction perpendicular to the substrate 01, the signal line connection portion 410 does not overlap with the gate line 200 and the data line 300.

[0121] For example, such as Figure 8 As shown, an insulating layer, such as a passivation layer, is formed on the side of the common electrode 120 away from the common electrode line 500. The passivation layer contains a first via 141 that exposes the first electrode 131 of the transistor 130, and an exposed common electrode connection portion 530 (e.g., ...). Figure 12 (as shown) and the second via 142 of the signal line connection portion 410 and the via 145 that exposes the common electrode line 500 and the common electrode 120.

[0122] In some examples, such as Figure 8 As shown, the outline of the first via 141 projected onto the substrate 01 includes a chamfer.

[0123] In some examples, such as Figure 8 As shown, the outline of the second via 142 projected onto the substrate 01 includes a chamfer.

[0124] By setting at least one of the first via 141 and the second via 142 to have a chamfered shape, the smoothness at the included angle of at least one of the first via 141 and the second via 142 is improved, preventing the conductive layer formed in at least one of the first via 141 and the second via 142, such as the film layer where the touch signal line 400 is located, from breaking at the included angle.

[0125] For example, such as Figure 8 As shown, the orthographic projection contours of the first via 141 and the second via 142 can both be chamfered quadrilaterals, and different chamfers of the same via have the same dimensions. For example, different orthographic projection contours of the first via 141 have the same shape and dimensions, and different orthographic projection contours of the second via 142 have the same shape and dimensions.

[0126] For example, the chamfer dimensions in the first via 141 and the second via 142 are not less than the resolution of the exposure machine, and the chamfer dimensions in the first via 141 and the second via 142 refer to... Figure 6B The dimensions of d1 and d2 in the third via 143 are shown. For example, the chamfer dimensions in the first via 141 and the second via 142 are not less than 3 micrometers.

[0127] Figure 8 The second via 142 of the exposed signal line connection portion 410 is schematically shown. When the common electrodes 120 of adjacent sub-pixels 100 arranged along the second direction are electrically connected, a common electrode connection portion 530 for connecting the common electrode is provided at the interval between the pixel electrodes 110 of the adjacent sub-pixels 100. The second via 142 exposes the common electrode connection portion 530 at this location (e.g., ...). Figure 12 (As shown).

[0128] For example, a gate insulating layer 02 (such as) is also provided between the organic insulating layer where the third via 143 is located and the gate line. Figure 10 and Figure 11 As shown), the gate insulating layer has vias exposing the gate lines, and the organic insulating layer 03 (as shown) Figure 10 and Figure 11 The third via 143 shown includes at least a portion of the via, and the orthographic projection profile of the via on the substrate 01 may also have the aforementioned chamfer.

[0129] In some examples, such as Figure 9 As shown, the array substrate also includes multiple touch signal lines 400 located on the side of the common electrode 120 away from the substrate 01. For example, the material of the touch signal lines 400 may include one or more of molybdenum, aluminum, and copper.

[0130] In some examples, such as Figure 9As shown, the signal line connection part 410 is electrically connected to the touch signal line 400 through the second via 142.

[0131] In some examples, such as Figure 2B and Figure 9 As shown, the pixel electrode 110 is located on the side of the plurality of touch signal lines 400 away from the substrate 01, and the plurality of touch signal lines 400 are arranged along a first direction. At least a portion of the touch signal lines 400 are electrically connected to the film layer containing the common electrode 120 through a second via 142 in the insulating layer between them and the film layer containing the common electrode 120. For example, a portion of the touch signal lines 400 are electrically connected to the common electrode connection portion through the second via 142, and a portion of the touch signal lines 400 are electrically connected to the signal line connection portion 410 through the second via 142.

[0132] In some examples, such as Figure 9 As shown, the second via 142 is located between two adjacent first protrusions 221, and the orthographic projection of the second via 142 on the substrate 01 is located between the second orthographic projection and the orthographic projection of the first via 141 on the substrate 01.

[0133] By setting the relative positional relationship between the gate body 210, the protrusion 220 and the first via 141, space can be reserved for the second via 142 to improve the pixel aperture ratio.

[0134] In some examples, such as Figure 1 , Figure 2B as well as Figure 9 As shown, along the direction perpendicular to the substrate 01, the multiple touch signal lines 400 and the multiple protrusions 220 do not overlap.

[0135] By setting the shape of the protrusion to reserve the position of the touch signal line 400, it is beneficial to avoid signal interference between the touch signal line 400 and the gate line 200 and the data line 300, while improving the pixel aperture ratio.

[0136] For example, such as Figure 9 As shown, along a direction perpendicular to the substrate 01, a portion of the touch signal line 400 overlaps with the data line 300, while a portion does not overlap. For example, the overlapping portion of the touch signal line 400 extends in the same direction as the data line 300. For example, the line width of the overlapping portion of the touch signal line 400 is greater than the line width of the data line 300.

[0137] For example, such as Figure 9As shown, the portion of the touch signal line 400 that does not overlap with the data line 300 bypasses the gate 133 and overlaps with the signal line connection portion 410. For example, the portion of the touch signal line 400 that is closest to the second side 2212 of the orthogonal projection of the gate 133 in the orthogonal projection on the substrate 01 extends along the U direction. For example, the portion of the touch signal line 400 that is closest to the side 2214 of the orthogonal projection of the gate 133 in the orthogonal projection on the substrate 01 extends along the Y direction. For example, the touch signal line 400 also includes a connection portion that connects the portion extending along the Y direction and the portion extending along the direction of the data line 300, such that this portion extends approximately along the V direction.

[0138] For example, such as Figure 2B and Figure 9 As shown, the film layer containing the touch signal line 400 also includes a bridging conductive structure 423. The bridging conductive structure 423 includes a portion located in the first via 141 to achieve electrical connection with the first electrode 131 of the thin-film transistor 130. For example, the pixel electrode 110 is in direct contact with the bridging conductive structure 423 to achieve electrical connection with the first electrode 131 of the thin-film transistor 130.

[0139] Figure 10 For along Figure 2B A schematic diagram of the local cross-section structure intercepted by line DD'.

[0140] In some examples, such as Figure 2B and Figure 10 As shown, the orthographic projection of the common electrode 120 on the substrate 01 overlaps with the second portion 1432 of the third via 143, and the portion of the common electrode 120 located in the third via 143 includes a portion disposed on the same layer as the common electrode line 500.

[0141] By setting the portion of the common electrode 120 located in the third via 143 to include a portion in the same layer as the common electrode line 500, it is beneficial to improve the diffusion effect of the liquid crystal alignment film and prevent poor liquid crystal alignment.

[0142] For example, such as Figure 10 As shown, the common electrode 120 includes not only the portion disposed in the same layer as the common electrode line 500, but also the portion covering the common electrode line 500, which is beneficial to improving the electrical connection effect between the common electrode and the common electrode line.

[0143] In some examples, such as Figure 10As shown, the film layer containing the multiple touch signal lines 400 includes a first common conductive layer 421, and the film layer containing the pixel electrode 110 includes a second common conductive layer 422. The first common conductive layer 421 and the second common conductive layer 422 are stacked and in direct contact, and the first common conductive layer 421 and the second common conductive layer 422 cover the portion of the common electrode 120 and the common electrode line 500 located in the third via 143.

[0144] For example, such as Figure 2B and Figure 10 As shown, the first common conductive layer 421 and the second common conductive layer 422 are electrically connected to the common electrode line 500 and the common electrode 120 through the via 145.

[0145] By configuring the common electrode line 500 to include a stepped structure, and connecting the first common conductive layer 421 and the second common conductive layer 422 in parallel, and electrically connecting them to the common electrode 120 and the common electrode line 500 located in the via, it is beneficial to reduce the via contact resistance.

[0146] For example, such as Figure 2B and Figure 10 As shown, the orthographic projections of the first common conductive layer 421 and the second common conductive layer 422 on the substrate 01 completely overlap.

[0147] For example, such as Figure 2B and Figure 10 As shown, the first common conductive layer 421 and the second common conductive layer 422 completely cover the third via 143.

[0148] For example, such as Figure 10 As shown, the array substrate includes a gate insulating layer 02 covering the common electrode line 500. An organic insulating layer 03 is disposed on the side of the gate insulating layer 02 away from the substrate 01. The third via 143 can be a via penetrating the gate insulating layer 02 and the organic insulating layer 03. For example, a passivation layer 04 is disposed on the side of the organic insulating layer 03 away from the substrate 01, and the via 145 can be a via penetrating the passivation layer 04.

[0149] Figure 11 For along Figure 2B A schematic diagram of the partial cross-sectional structure cut by line EE'.

[0150] In some examples, such as Figure 2B and Figure 11 As shown, the film layer where the pixel electrode 110 is located includes a conductive portion 600 spaced apart from the pixel electrode 110. The conductive portion 600 is stacked with and in direct contact with multiple touch signal lines 400.

[0151] By setting a conductive part 600 that is in direct contact with the touch signal line 400, the resistance of the two is connected in parallel. This helps to reduce the resistance of the touch signal line 400 to improve touch performance, while preventing the metal material of the touch signal line 400 from being exposed and corroded or oxidized.

[0152] For example, such as Figure 2B and Figure 11 As shown, in the X direction, the size of the data line 300 is smaller than the size of the touch signal line 400, and the size of the touch signal line 400 is smaller than the size of the conductive portion 600. For example, the conductive portion 600 completely covers the touch signal line 400.

[0153] For example, such as Figure 2B As shown, the conductive portion 600 also includes a portion covering the signal line connection portion 410 and the second via 142. For example, a portion of the second via 142 is filled by the touch signal line 400, and another portion is filled by the conductive portion 600.

[0154] Figure 12 for Figure 1 A magnified view of a portion of the film layer in region F shown.

[0155] In some examples, such as Figure 12 As shown, a common electrode connection portion 530 is provided between the common electrodes 120 of at least two adjacent sub-pixels 100 arranged along the second direction. This common electrode connection portion 530 is configured to connect adjacent common electrodes 120. For example, at different locations, a common electrode connection portion 530 or a signal line connection portion 410 may be provided between two adjacent sub-pixels 100 arranged along the second direction. For example, the common electrode connection portion 530 and the common electrode 120 may be an integrally formed structure. For example, the common electrode connection portion may also be considered as part of the common electrode.

[0156] In some examples, such as Figure 12 As shown, the common electrode connection portion 530 is located between two adjacent data lines 300. The common electrode connection portion 530 includes a first connection portion 531, a second connection portion 532, and a third connection portion 533 arranged sequentially along a second direction. For example, the first connection portion 531, the second connection portion 532, and the third connection portion 533 are integrally formed. Figure 12 The boundary positions where the first connecting part, the second connecting part, and the third connecting part meet each other are shown by dashed lines.

[0157] In some examples, such as Figure 12As shown, the first connecting part 531 is located between the first pole 131 and the data line 300, the second connecting part 532 is located between two adjacent protrusions 220, and the third connecting part 533 overlaps with the gate line body 210. In the first direction, the size of the first connecting part 531 and the size of the third connecting part 533 are both smaller than the size of the second connecting part 532.

[0158] By setting the shape of the common electrode connection portion 530, not only can the position of the first via 141 be bypassed to avoid short circuit between the common electrode 120 and the pixel electrode 110, but the distance between the common electrode 120 and the data line 300 can also be increased to avoid lateral parasitic capacitance while reducing the overlap area between the common electrode 120 and the gate line 200, further reducing parasitic capacitance.

[0159] For example, such as Figure 12 As shown, one edge of the first connecting portion 531 extending along the second direction is on the same straight line as one edge of the second connecting portion 532 extending along the second direction, and another edge of the second connecting portion 532 extending along the second direction is on the same straight line as one edge of the third connecting portion 533 extending along the second direction.

[0160] For example, such as Figure 12 As shown, in the first direction, the dimensions of the first connecting portion 531 and the third connecting portion 533 can be the same. However, they are not limited to this, and their dimensions can also be different.

[0161] In some examples, such as Figure 12 As shown, the first connecting portion 531 and the third connecting portion 533 are staggered in the first direction, and the straight line extending along the second direction passes through the orthographic projection of the first pole 131, the second connecting portion 532 and the third connecting portion 533 on the substrate 01.

[0162] By staggering the third connection portion 533 relative to the first connection portion 531, it is beneficial to increase the distance between the third connection portion 533 and the data line 300 and reduce the parasitic capacitance between the common electrode 120 and the data line 300.

[0163] For example, such as Figure 12 As shown, the straight line extending along the second direction and passing through the first connecting part 531 does not pass through the third connecting part 533.

[0164] In some examples, such as Figure 12 As shown, at least a portion of the touch signal line 400 is electrically connected to the second connection portion 532 through a second via 142 in the insulating layer between it and the second connection portion 532.

[0165] By setting the second via 142 to overlap with the second connection portion 532, it is beneficial to reduce the alignment accuracy of the second via 142 and improve the electrical connection effect between the touch signal line 400 and the common electrode connection portion 530.

[0166] For example, a portion of the multiple touch signal lines 400 is electrically connected to the second connection portion 532 through the second via 142 to achieve electrical connection with the common electrode 120, and another portion of the multiple touch signal lines 400 is electrically connected to the signal line connection portion 410 through the second via 142, which helps to reduce the resistance of the touch signal lines 400. For example, a straight line extending along the first direction passes through the signal line connection portion 410 and the second connection portion 532.

[0167] Figure 13 This is a partial planar structure schematic diagram of an array substrate provided according to another example of an embodiment of the present utility model. Figure 13 The array substrate shown and Figure 2B The array substrate shown differs in that the plurality of protrusions 220 also include at least one second protrusion 222.

[0168] In some examples, such as Figure 13 As shown, the plurality of protrusions 220 also include at least one second protrusion 222, and the transistors 130 in the plurality of sub-pixels 100 include at least one first transistor 1301 and at least one second transistor 1302. Each first transistor 1301 includes a first protrusion 221, and each second transistor 1302 includes a second protrusion 222. The shape of the first protrusion 221 is different from the shape of the second protrusion 222. In a second direction, the maximum size of the first protrusion 221 is greater than the maximum size of the second protrusion 222.

[0169] In some examples, such as Figure 13 As shown, the outline of the fourth orthographic projection of each second protrusion 222 on the substrate 01 includes a fourth side 2221, which is located between the second electrode 132 of the second transistor 1302 and the first via 141, and the fourth side 2221 extends along the first direction.

[0170] For example, in this example, the second protrusion 222 and Figure 2A The gates shown have the same shape. Relative to including Figure 2A The array substrate of the gate shown in this utility model provides an array substrate that, while having a second protrusion 222, also has at least one first protrusion 221, which reserves space for the via connecting the pixel electrode 110 and the via connecting the control signal line 400, which is beneficial to improving the aperture ratio of the sub-pixel.

[0171] For example, such as Figure 13As shown, the number of first protrusions 221 is greater than the number of second protrusions 222. By setting the number of first protrusions 221 to be greater than the number of second protrusions 222, it is beneficial to significantly improve the aperture ratio of sub-pixels.

[0172] In some examples, such as Figure 13 As shown, the pixel electrode 110 includes a main electrode 111 and a connection electrode 112, the connection electrode 112 being electrically connected to the first electrode 131 in the transistor 130. For example, a display panel including this array substrate may include a black matrix (not shown), and the main electrode 111 may be a portion opposite to an opening in the black matrix. For example, the main electrode 111 may include multiple domains. For example, the main electrode 111 and the connection electrode 112 may be integrally formed. For example, the connection electrode 112 may be located between the main electrode 111 and the gate 133 of the thin-film transistor.

[0173] In some examples, such as Figure 13 As shown, the distance between the first protrusion 221 and the main electrode 111 of the pixel electrode 110 connected to the first transistor 1301 is a first distance D1, and the distance between the second protrusion 222 and the main electrode 111 of the pixel electrode 110 connected to the second transistor 1302 is a second distance D2. The first distance D1 is less than the second distance D2. For example, the distance between the first protrusion 221 and the main electrode 111 closest to the first protrusion 221 is the first distance D1, and the distance between the second protrusion 222 and the main electrode 111 closest to the second protrusion 222 is the second distance D2.

[0174] When the shapes of the first protrusion 221 and the second protrusion 222 are different, by setting the distance relationship between the first protrusion 221 and the second protrusion 222 and the main electrode 111 of the pixel electrode 110, space can be reserved between the second protrusion 222 and the main electrode 111 of the pixel electrode 110 for a via connecting the pixel electrode 110 and the thin film transistor.

[0175] In some examples, such as Figure 13 As shown, the second electrode 132 of the first transistor 1301 includes a first U-shaped structure 1310, the opening of the first U-shaped structure 1310 facing the first via 141, and the second electrode 132 of the second transistor 1302 includes a second U-shaped structure 1320, the opening of the second U-shaped structure 1320 facing the protrusion adjacent to it.

[0176] U-shaped structures with different orientations are provided for protrusions 220 with different shapes so that the shape of the second electrode 132 of the transistor matches that of the gate 133, thereby ensuring the performance of different transistors.

[0177] For example, such as Figure 13As shown, the two strips 1300 of the second U-shaped structure 1320 are parallel to the fourth side 2221.

[0178] For example, such as Figure 13 As shown, in the first U-shaped structure 1310, the length of the strip 1300 closer to the pixel electrode 110 is less than the length of the strip 1300 farther from the pixel electrode 110. In the second U-shaped structure 1320, the lengths of the two strips 1300 are the same, or the length of the strip 1300 closer to the pixel electrode 110 is greater than the length of the strip 1300 farther from the pixel electrode 110.

[0179] In some examples, such as Figure 13 As shown, the first electrode 131 of the first transistor 1301 is connected to the connection electrode 112, and the second electrode 132 of the first transistor 1301 is connected to the data line 300. The first electrode 131 of the second transistor 1302 is connected to the connection electrode 112, and the second electrode 132 of the second transistor 1302 is also connected to the data line 300. The distance between the connection electrode 112 connected to the same first transistor 1301 and the data line 300 is a third distance D3, and the distance between the connection electrode 112 connected to the same second transistor 1302 and the data line 300 is a fourth distance D4. The third distance D3 is greater than the fourth distance D4. For example, the minimum distance between the connection electrode 112 connected to the second transistor 1302 and the data line 300 is the fourth distance D4.

[0180] When the orientation of different U-shaped structures is different, by setting the distance between the connection electrode 112 connected to the second transistor 1302 and the data line 300 to be less than the distance between the connection electrode 112 connected to the first transistor 1301 and the data line 300, space can be reserved for the first pole 131 of the second transistor 1302.

[0181] For example, such as Figure 13 As shown, the first protrusion 221 includes a portion located between the connecting electrode 112 and the data line 300, and the second protrusion 222 is located entirely on the side of the connecting electrode 112 away from the main electrode 111.

[0182] In some examples, such as Figure 13 As shown, the extension direction of the portion of the first electrode 131 of the first transistor 1301 that does not overlap with the pixel electrode 110 intersects with the first direction, such as extending along a third direction. The portion of the first electrode 131 of the second transistor 1302 that does not overlap with the pixel electrode 110 includes a first electrode portion 1311 extending along the first direction and a second electrode portion 1312 extending along the second direction. Along a direction perpendicular to the substrate 01, the second electrode portion 1312 does not overlap with the second protrusion 222. For example, the first electrode portion and the second electrode portion are integrally formed.

[0183] When the first protrusion 221 and the second protrusion 222 have different shapes, the shapes of the different protrusions can be better matched by setting the shape of the first electrode 131 in different transistors.

[0184] For example, such as Figure 13 As shown, the second electrode portion 1312 is located between the first electrode portion 1311 and the data line 300. For example, the first electrode portion 1311 is inserted into the U-shaped opening of the second U-shaped structure 1320. For example, the first electrode 131 of the first transistor 1301 is parallel to the strip 1300 of the first U-shaped structure 1310, and the first electrode portion 1311 of the second transistor 1302 is parallel to the strip 1300 of the second U-shaped structure 1320.

[0185] In some examples, such as Figure 13 As shown, the array substrate also includes multiple common electrode lines 500, disposed on the same layer as the multiple gate lines 200. The multiple common electrode lines 500 are arranged along a second direction. At least some of the common electrode lines 500 include a common electrode line body 510 extending along a first direction and at least one common electrode line connection portion 520 arranged along the first direction. The common electrode line connection portion 520 is electrically connected to the common electrode 120 through a third via 143 in the insulating layer between it and the common electrode 120. The common electrode lines in this example may have the same characteristics as the common electrode lines in the above examples, and will not be described again here.

[0186] In some examples, such as Figure 13 As shown, the array substrate also includes multiple touch signal lines 400 located on the side of the common electrode 120 away from the substrate 01. The multiple touch signal lines 400 are arranged along a first direction, and at least a portion of the touch signal lines 400 are electrically connected to the film layer containing the common electrode 120 through a second via 142 in the insulating layer between them. For example, some touch signal lines 400 can be electrically connected to the common electrode connection portion through the second via 142, and some touch signal lines 400 can be electrically connected to the signal line connection portion 410 through the second via 142. The touch signal lines 400 in this example and their electrical connections to the film layer containing the common electrode can have the same characteristics as the corresponding structures in the above examples, and will not be described again here.

[0187] In some examples, such as Figure 13As shown, a gate line 200 and a common electrode line 500 are provided between two adjacent rows of sub-pixels 100 arranged in the second direction. The common electrode line 500 is located on the side of the gate line body 210 away from the protrusion 220. At least one common electrode line connection portion 520 is located on the side of the common electrode line body 510 away from the gate line 200, and the straight line extending along the second direction passes through the orthographic projection of the second protrusion 222 and the common electrode line connection portion 520 on the substrate 01. The second via 142 is only provided between the pixel electrode 110 and the gate line body 210 connected to the same first transistor 1301.

[0188] For example, such as Figure 13 As shown, a second via 142 is provided between the first protrusion 221 and the data line 300, but no second via 142 is provided between the second protrusion 222 and the data line 300.

[0189] In the array substrate provided in this example, there is no second via 142 between the second protrusion 222 and the data line 300, so there is no need to design a common electrode connection or signal line connection, saving some space and allowing the shape of the second protrusion 222 to be different from the shape of the first protrusion 221.

[0190] By matching the position of the second via 142 with the different shapes of the protrusion 220, it is beneficial to achieve a close arrangement of pixels and improve the aperture ratio of sub-pixels.

[0191] For example, in other examples, the second via 142 connected to the common electrode is configured to correspond to the second protrusion 222. The distance between the pixel electrode 110 of the first sub-pixel 101 and the gate line body 210 in the gate line connected to the first transistor 1301 can be set to be greater than the distance between the pixel electrode 110 of the second sub-pixel 102 and the gate line body 210 in the gate line connected to the second transistor 1302. That is, the pixel electrode 110 is moved down to increase the aperture ratio of the sub-pixel.

[0192] Other structures in the array substrate provided in this example may have the same characteristics as the corresponding structures in the array substrate provided in the above examples, and will not be described again here.

[0193] Figure 14 This is a partial structural schematic diagram of a display device according to another embodiment of the present invention.

[0194] like Figure 14 As shown, another embodiment of the present invention provides a display device, including the array substrate 1000 provided in any of the above examples.

[0195] For example, the display device can be a liquid crystal display device.

[0196] In some examples, such as Figure 14 As shown, the display device also includes a counter substrate 2000 disposed opposite to the array substrate 1000. For example, the counter substrate 2000 may include a black matrix and a color filter layer, such as a color filter substrate.

[0197] In some examples, such as Figure 14 As shown, the display device also includes a liquid crystal layer 3000 located between the array substrate 1000 and the opposing substrate 2000. For example, a sealant 4000 is also disposed between the array substrate 1000 and the opposing substrate 2000.

[0198] For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, laptop computer, or navigator; this embodiment is not limited to this.

[0199] The following points need to be explained:

[0200] (1) The accompanying drawings of the embodiments of this utility model only involve the structures involved in the embodiments of this utility model. Other structures can be referred to the general design.

[0201] (2) Where there is no conflict, features of the same embodiment and different embodiments of the present invention can be combined with each other.

[0202] The above description is merely an exemplary embodiment of the present utility model and is not intended to limit the scope of protection of the present utility model. The scope of protection of the present utility model is determined by the appended claims.

Claims

1. An array substrate, characterized in that, include: Substrate; Multiple sub-pixels are located on the substrate and are arranged in an array along a first direction and a second direction. Each sub-pixel includes a pixel electrode, a common electrode, and at least one transistor. Each of the at least one transistor includes a gate, a first electrode, and a second electrode. The pixel electrode is electrically connected to the first electrode through a first via in an insulating layer between itself and the first electrode of a transistor. Multiple gate lines are located on the substrate and are arranged along the second direction. Each gate line includes a gate line body extending along the first direction and multiple protrusions arranged along the first direction. The multiple protrusions are located on the same side of the gate line body, and each protrusion serves as the gate of a transistor in the sub-pixel. Multiple data lines are located on the side of the multiple gate lines away from the substrate. The multiple data lines are arranged along the first direction. The second electrode of a transistor in the sub-pixel is electrically connected to the corresponding data line, and the second electrode includes a U-shaped structure. The plurality of protrusions include at least one first protrusion, and the U-shaped structure overlapping each first protrusion is a first U-shaped structure. The first U-shaped structure includes two strips extending along a third direction, the first direction intersecting with the second direction, and the third direction intersecting with both the first direction and the second direction. The outline of the first orthographic projection of each first protrusion on the substrate includes a first side and a second side. The first side is located between the second electrode of the transistor where the first protrusion is located and the first via. The first side extends along a fourth direction, which intersects the first direction, the second direction and the third direction. The second side passes through the orthographic projection of the data line on the substrate and extends along the third direction.

2. The array substrate according to claim 1, characterized in that, The outline of the first orthographic projection also includes a third side, which is located between the first side and the second orthographic projection of the gate line body on the substrate, and the third side extends along the second direction; The distance between the orthographic projection of the first via on the substrate and the orthographic projection of the second via is greater than the length of the third side.

3. The array substrate according to claim 1, characterized in that, Also includes: Multiple touch signal lines are located on the side of the common electrode away from the substrate, and the pixel electrode is located on the side of the multiple touch signal lines away from the substrate. The multiple touch signal lines are arranged along the first direction. At least a portion of the touch signal lines are electrically connected to the film layer containing the common electrode through a second via in the insulating layer between the line and the film layer containing the common electrode. The second via is located between two adjacent first protrusions, and the orthographic projection of the second via on the substrate is located between the orthographic projection of the second via and the orthographic projection of the first via on the substrate.

4. The array substrate according to claim 3, characterized in that, Along a direction perpendicular to the substrate, the multiple touch signal lines do not overlap with the multiple protrusions.

5. The array substrate according to claim 3, characterized in that, The film layer containing the common electrode includes a signal line connection portion, which is electrically connected to the touch signal line through the second via. A straight line extending along the second direction passes through the signal line connection portion and the orthogonal projection of the first electrode of the transistor onto the substrate.

6. The array substrate according to claim 2, characterized in that, The length of the second side is greater than the length of the first side, the dimension of the first U-shaped structure in the third direction is greater than the dimension in the fourth direction, and the first U-shaped structure and the connected data line are an integrated structure.

7. The array substrate according to claim 1, characterized in that, The orthographic projection of the first via on the substrate is the third orthographic projection, and the straight line extending along the second direction passes through the third orthographic projection and the first edge.

8. The array substrate according to claim 1, characterized in that, The plurality of protrusions further include at least one second protrusion, and the transistors in the plurality of sub-pixels include at least one first transistor and at least one second transistor, each first transistor including a first protrusion and each second transistor including a second protrusion; The shape of the first protrusion is different from that of the second protrusion, and in the second direction, the maximum size of the first protrusion is greater than the maximum size of the second protrusion.

9. The array substrate according to claim 8, characterized in that, The outline of the fourth orthographic projection of each second protrusion on the substrate includes a fourth side located between the second electrode of the second transistor and the first via, and the fourth side extends along the first direction.

10. The array substrate according to claim 8, characterized in that, The pixel electrode includes a main electrode and a connecting electrode, and the connecting electrode is electrically connected to the first electrode in the transistor. The distance between the first protrusion and the main electrode of the pixel electrode connected to the first transistor is a first distance, and the distance between the second protrusion and the main electrode of the pixel electrode connected to the second transistor is a second distance, wherein the first distance is less than the second distance.

11. The array substrate according to claim 10, characterized in that, The first terminal of the first transistor is connected to the connection electrode, the second terminal of the first transistor is connected to the data line, the first terminal of the second transistor is connected to the connection electrode, and the second terminal of the second transistor is connected to the data line; The distance between the connection electrode and the data line connected to the same first transistor is a third distance, and the distance between the connection electrode and the data line connected to the same second transistor is a fourth distance, wherein the third distance is greater than the fourth distance.

12. The array substrate according to claim 8, characterized in that, The second electrode of the first transistor includes the first U-shaped structure, the opening of the first U-shaped structure facing the first via, and the second electrode of the second transistor includes a second U-shaped structure, the opening of the second U-shaped structure facing the protrusion adjacent to it.

13. The array substrate according to claim 8, characterized in that, The extension direction of the portion of the first electrode of the first transistor that does not overlap with the pixel electrode intersects with the first direction. The portion of the first electrode of the second transistor that does not overlap with the pixel electrode includes a first electrode portion extending along the first direction and a second electrode portion extending along the second direction. The second electrode portion does not overlap with the second protrusion in a direction perpendicular to the substrate.

14. The array substrate according to claim 8, characterized in that, Also includes: Multiple common electrode lines are arranged in the same layer as the multiple gate lines, and the multiple common electrode lines are arranged along the second direction. Each of the at least some common electrode lines includes a common electrode line body extending along the first direction and at least one common electrode line connection portion arranged along the first direction, wherein the common electrode line connection portion is electrically connected to the common electrode through a third via in the insulating layer between it and the common electrode. A gate line and a common electrode line are provided between two adjacent rows of sub-pixels arranged in the second direction. The common electrode line is located on the side of the gate line body away from the protrusion. At least one common electrode line connection is located on the side of the common electrode line body away from the gate line. The straight line extending along the second direction passes through the orthographic projection of the second protrusion and the common electrode line connection on the substrate.

15. The array substrate according to claim 8, characterized in that, Also includes: Multiple touch signal lines are located on the side of the common electrode away from the substrate, and the multiple touch signal lines are arranged along the first direction. At least a portion of the touch signal lines are electrically connected to the film layer containing the common electrode through a second via in the insulating layer between the common electrode and the film layer containing the common electrode. The second via is only provided between the pixel electrode and the gate line body connected to the same first transistor.

16. The array substrate according to claim 1, characterized in that, Also includes: Multiple common electrode lines are arranged in the same layer as the multiple gate lines, and the multiple common electrode lines are arranged along the second direction. Each of the at least some common electrode lines includes a common electrode line body extending along the first direction and at least one common electrode line connection portion arranged along the first direction, wherein the common electrode line connection portion is electrically connected to the common electrode through a third via in the insulating layer between it and the common electrode. The common electrode line connection portion includes a stepped structure, the stepped structure including at least a first step and a second step connected to each other, in the second direction, the size of the first step is larger than the size of the second step, the orthographic projection of the third via on the substrate includes at least two parts, the first part of the two parts overlaps with the orthographic projection of the stepped structure on the substrate, and the second part of the two parts does not overlap with the orthographic projection of the common electrode line on the substrate.

17. The array substrate according to claim 16, characterized in that, The orthographic projection of the common electrode on the substrate overlaps with the second portion, and the portion of the common electrode located in the third via includes a portion disposed in the same layer as the common electrode line.

18. The array substrate according to claim 17, characterized in that, Also includes: Multiple touch signal lines are located on the side of the common electrode away from the substrate, and the multiple touch signal lines are arranged along the first direction. Among them, at least a portion of the touch signal lines are electrically connected to the film layer containing the common electrode through a second via in the insulating layer between them and the film layer containing the common electrode; The film layer containing the multiple touch signal lines includes a first common conductive layer, and the film layer containing the pixel electrode includes a second common conductive layer. The first common conductive layer and the second common conductive layer are stacked and in direct contact, and the first common conductive layer and the second common conductive layer cover the portion of the common electrode and the common electrode line located in the third via.

19. The array substrate according to claim 1, characterized in that, A common electrode connection portion is provided between the common electrodes of at least two adjacent sub-pixels arranged along the second direction, and the common electrode connection portion is configured to connect adjacent common electrodes; The common electrode connection is located between two adjacent data lines. The common electrode connection includes a first connection, a second connection, and a third connection arranged sequentially along the second direction. The first connection is located between the first electrode and the data line. The second connection is located between two adjacent protrusions. The third connection overlaps with the gate line body. In the first direction, the size of the first connection and the size of the third connection are both smaller than the size of the second connection.

20. The array substrate according to claim 19, characterized in that, Also includes: Multiple touch signal lines are located on the side of the common electrode away from the substrate, and the multiple touch signal lines are arranged along the first direction. At least a portion of the touch signal lines are electrically connected to the second connection portion through a second via in the insulating layer between them and the second connection portion.

21. The array substrate according to claim 19, characterized in that, The first connecting portion and the third connecting portion are staggered in the first direction, and a straight line extending along the second direction passes through the orthogonal projection of the first pole, the second connecting portion and the third connecting portion on the substrate.

22. The array substrate according to claim 3, characterized in that, The film layer containing the pixel electrode includes conductive portions spaced apart from the pixel electrode, and the conductive portions are stacked and in direct contact with the multiple touch signal lines.

23. The array substrate according to claim 1, characterized in that, The outline of the first via's orthographic projection on the substrate includes a chamfer.

24. The array substrate according to claim 3, characterized in that, The outline of the second via's orthographic projection on the substrate includes a chamfer.

25. The array substrate according to claim 14, characterized in that, The outline of the orthographic projection of the third via on the substrate includes a chamfer.

26. The array substrate according to claim 2, characterized in that, The two ends of the first side are connected to the second side and the third side respectively, and the outline of the first orthographic projection also includes a fifth side connected to the second side, the fifth side being parallel to the third side; The angle between the second side and the fifth side is the first angle, and the angle between the first side and the third side is the second angle. The first angle is smaller than the second angle.

27. A display device, characterized in that, Includes the array substrate as described in any one of claims 1-26.

28. The display device according to claim 27, characterized in that, Also includes: The opposing substrate is disposed opposite to the array substrate; A liquid crystal layer is located between the array substrate and the opposing substrate.

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