Circuit for preventing impact current

Abstract

The utility model provides an anti-impact current circuit, which relates to the technical field of power electronics and comprises an impact current suppression circuit, a fast recovery impact current suppression circuit and a filtering suppression circuit. Under the action of a voltage-regulator tube D2 in the impact current suppression circuit, the gate-source voltage of the MOS tube Q1 is stabilized within a safe value, so that the MOS tube Q1 is prevented from being burnt due to over-high gate-source voltage, and the risk to equipment is avoided. In the rapid recovery impact current suppression circuit, when the voltage at the two ends of a time delay capacitor C1 reaches the gate-source voltage required by conduction of an MOS tube again, the MOS tube is turned on again to work, and before this, the current of a loop can only flow back to the negative end of a power supply through a current limiting resistor R4, so that the performance of suppressing the impact current again is realized. Common-mode disturbance is led into the ground through the filtering suppression circuit and cannot enter a test end or other equipment, so that normal work of the other equipment is ensured.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, specifically a circuit for preventing surge current. Background Technology

[0002] The inrush current that occurs when the equipment is powered on can pose a potential threat to the normal operation of downstream equipment. Therefore, it is necessary to suppress the generation of inrush current, quickly restore the inrush current suppression function, suppress electromagnetic interference generated when the driver is working, and reduce the impact on the equipment.

[0003] To cope with complex and ever-changing working environments, ensure the safe use of equipment, and meet the relevant requirements of GJB181B-2012 "Aircraft Power Supply Characteristics" and GJB151B-2013 "Electromagnetic Emission and Sensitivity Requirements and Measurements for Military Equipment and Subsystems", a circuit for preventing inrush current is proposed. This circuit has the function of suppressing inrush current, can quickly recover from inrush current suppression, and effectively suppress electromagnetic interference generated during driver operation. Utility Model Content

[0004] (a) Technical problems to be solved

[0005] To address the shortcomings of existing technologies, this invention provides a circuit that prevents surge current, solving the problem of balancing charging speed and adapter size while providing clean, interference-free power supply for military equipment.

[0006] (II) Technical Solution

[0007] To achieve the above objectives, this utility model is implemented through the following technical solution: a circuit for preventing surge current, comprising a surge current suppression circuit, a fast recovery surge current suppression circuit, and a filter suppression circuit.

[0008] The input terminal of the inrush current suppression circuit is connected to the input terminal of the device, and the output terminal of the filter suppression circuit is connected to the output terminal of the device.

[0009] Preferably, the inrush current suppression circuit includes a rectifier diode D1, a Zener diode D2, a voltage divider resistor R1, a current-limiting resistor R2, a voltage divider resistor R3, a current-limiting resistor R4, a delay capacitor C1, and a MOSFET Q1, wherein:

[0010] The positive terminal of the device output is connected to a rectifier diode D1. The output of the rectifier diode D1 is divided into two paths. The first path outputs to the positive terminal of the filter suppression circuit, and the second path is connected to a voltage divider resistor R1. One output of the voltage divider resistor R1 is connected to a current limiting resistor R2. The output of the current limiting resistor R2 is connected to a delay capacitor C1, a voltage divider resistor R3, and the gate of a MOS transistor Q1.

[0011] The output of the voltage divider resistor R1 is connected to the negative terminal of the Zener diode D2. The positive terminal of the Zener diode D2 is connected to the delay capacitor C1, the voltage divider resistor R3, the source of the MOSFET, the current limiting resistor R4, and the negative terminal of the device input. The other end of the current limiting resistor R4 is connected to the drain of the MOSFET and the negative terminal of the filter suppression circuit.

[0012] Preferably, the fast recovery inrush current suppression circuit includes voltage divider resistors R5 and R6, transistor Q2, and some components for the inrush current suppression circuit, wherein:

[0013] One end of the voltage divider resistor R5 is connected to the positive terminal of the device input terminal, and the other end of the voltage divider resistor R5 is connected to the resistor R6 and the collector of the transistor Q2. The other end of the voltage divider resistor R6 is connected to the base of the transistor Q2, and the emitter of the transistor Q2 is connected to the gate of the MOS transistor Q1.

[0014] Preferably, the filtering and suppression circuit includes differential-mode capacitor CX1, differential-mode capacitor CX2, differential-mode inductor L1, common-mode inductor L2, common-mode capacitor CY1, and common-mode capacitor CY2, wherein:

[0015] The input terminal of the differential mode inductor L1 is connected to the output terminal of the rectifier diode D1. The drain of the MOSFET is connected to the differential mode inductor L1 through a differential mode capacitor CX1. The drain of the MOSFET is connected to the output terminal of the differential mode inductor L1 through a differential mode capacitor CX2. The two ends of the differential mode capacitor CX2 are connected to the input terminal of the common mode inductor L2. The output terminal of the common mode inductor L2 is connected to the first terminal of the common mode capacitor CY1 and the first terminal of the common mode capacitor CY2, respectively. The second terminals of the common mode capacitor CY1 and the second terminal of the common mode capacitor CY2 are both connected to the chassis ground. The output terminal of the common mode inductor L2 is set as the device output terminal.

[0016] (III) Beneficial Effects

[0017] This invention provides a circuit for preventing surge current. It has the following advantages:

[0018] 1. In this utility model, the voltage divider resistor R3, voltage divider resistor R1, and current limiting resistor R2 in the inrush current suppression circuit are proportionally divided to ensure the reliable conduction of MOSFET Q1 and prevent MOSFET Q1 from failing to turn on normally due to excessively low voltage. The function of Zener diode D2 is to stabilize the gate-source voltage of MOSFET Q1 within a safe value, preventing MOSFET Q1 from being burned out due to excessively high gate-source voltage, thus avoiding risks to the equipment.

[0019] 2. In this utility model, when the power supply is interrupted and then restored in the fast recovery inrush current suppression circuit, the voltage across the delay capacitor C1 reaches the gate-source voltage required for the MOSFET to turn on again, and the MOSFET turns on again. Before this, the current in the circuit can only flow back to the negative terminal of the power supply through the current limiting resistor R4, thereby achieving the performance of suppressing the inrush current again.

[0020] 3. In this utility model, the common-mode inductor L2 in the filtering and suppression circuit effectively suppresses high-frequency interference and reduces the energy carried by the high-frequency interference. The common-mode capacitors CY1 and CY2 provide a low-impedance path for the high-frequency interference, change the path of the interference, and guide the common-mode interference to the ground, preventing it from entering the test terminal or other equipment, thereby ensuring the normal operation of other equipment. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a circuit for preventing surge current according to the present invention. Detailed Implementation

[0022] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0023] As shown in the figure, the circuit for preventing surge current provided by this utility model includes a surge current suppression circuit, a fast recovery surge current suppression circuit, and a filter suppression circuit. The input terminal of the surge current suppression circuit is connected to the device input terminal, and the output terminal of the filter suppression circuit is connected to the device output terminal.

[0024] The inrush current suppression circuit includes a rectifier diode D1, a Zener diode D2, a voltage divider resistor R1, a current-limiting resistor R2, a voltage divider resistor R3, a current-limiting resistor R4, a delay capacitor C1, and a MOSFET Q1. The positive terminal of the power input is connected to the rectifier diode D1. The output of the rectifier diode D1 is split into two paths. The first path outputs to the positive terminal of the filter suppression circuit, and the second path is connected to the voltage divider resistor R1. One output of the voltage divider resistor R1 is connected to the current-limiting resistor R2. The output of the current-limiting resistor R2 is connected to the delay capacitor C1, the voltage divider resistor R3, and the gate of the MOSFET Q1. The other output of the voltage divider resistor R1 is connected to the negative terminal of the Zener diode D2. The positive terminal of the Zener diode D2 is connected to the delay capacitor C1, the voltage divider resistor R3, the source of the MOSFET, the current-limiting resistor R4, and the negative terminal of the power input. One end of the current-limiting resistor R4 and the drain of the MOSFET are connected to the negative terminal of the filter suppression circuit.

[0025] When the equipment is powered on normally, all capacitances between the positive and negative lines are approximately short-circuited. Current flows out through the positive line, through the rectifier diode D1, and then back to the negative power supply line through the current-limiting resistor R4. Due to the constant current effect of the resistor, the current is limited to the design value. Before the MOSFET Q1 is turned on, the loop current can only flow back to the negative power supply terminal through the current-limiting resistor. When the voltage across the delay capacitor C1 reaches the gate-source voltage required for the MOSFET to turn on, the MOSFET Q1 turns on. The capacitance of resistors R1, R2, and C1, together with the capacitance of the capacitances between the positive and negative lines, determines the charging time of the delay capacitor. The voltage divider resistor R3, along with the voltage divider resistor R1 and the current-limiting resistor R2, divides the voltage proportionally to ensure the reliable conduction of the MOSFET Q1 and prevent the MOSFET Q1 from failing to turn on due to excessively low voltage. The Zener diode D2 stabilizes the gate-source voltage of the MOSFET Q1 within a safe value, preventing the MOSFET Q1 from burning out due to excessively high gate-source voltage, thus avoiding risks to the equipment.

[0026] The fast recovery surge current suppression circuit mainly consists of three additional components: voltage divider resistor R5, voltage divider resistor R6, transistor Q2, and some components of the surge current suppression circuit. One end of voltage divider resistor R5 is connected to the positive terminal of the input power supply, and the other end is connected to the collector of voltage divider resistor R6 and transistor Q2 respectively. The other end of voltage divider resistor R6 is connected to the base of transistor Q2, and the emitter of transistor Q2 is connected to the gate of MOSFET Q1.

[0027] When powered on, the base voltage of transistor Q2 is higher than the emitter voltage, the emitter junction is reverse biased, causing transistor Q2 to be cut off, and the delay capacitor C1 charges normally. When the power supply is interrupted, the base voltage is lower than the emitter voltage, the emitter junction is forward biased, and the transistor is in amplification mode with extremely low internal resistance. It is approximately equivalent to directly shorting the two ends of the delay capacitor C1. The charge of the delay capacitor C1 is consumed in a very short time, causing the voltage across the gate and source of MOSFET Q1 to drop rapidly to 0 volts, and MOSFET Q1 is turned off. Therefore, from the time the power supply is interrupted until it is powered on again, when the voltage across the delay capacitor C1 reaches the gate and source voltage required for MOSFET to conduct again, the MOSFET turns on again. Before this, the current in the circuit can only flow back to the negative terminal of the power supply through the current limiting resistor R4, thereby achieving the performance of suppressing the inrush current again.

[0028] The filtering and suppression circuit includes differential-mode capacitor CX1, differential-mode capacitor CX2, differential-mode inductor L1, common-mode inductor L2, common-mode capacitor CY1, and common-mode capacitor CY2. Differential-mode capacitors CX1 and CX2 between the positive and negative lines provide a low-impedance path, diverting low-frequency interference back to the driver. Differential-mode inductor L1 dissipates the energy carried by low-frequency interference through heat generation, thereby reducing the energy carried by low-frequency interference and lowering the energy received by the test receiver to meet test standards. Common-mode inductor L2 effectively suppresses high-frequency interference, reducing the energy carried by high-frequency interference. Common-mode capacitors CY1 and CY2 provide a low-impedance path for high-frequency interference, changing the interference flow path and diverting common-mode interference to ground, preventing it from entering the test terminal or other equipment, thus ensuring the normal operation of other equipment.

[0029] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A circuit for preventing surge current, characterized in that: Includes inrush current suppression circuit, fast recovery inrush current suppression circuit, and filter suppression circuit; The input terminal of the inrush current suppression circuit is connected to the input terminal of the device, and the output terminal of the filter suppression circuit is connected to the output terminal of the device.

2. The circuit for preventing surge current according to claim 1, characterized in that: The inrush current suppression circuit includes a rectifier diode D1, a Zener diode D2, a voltage divider resistor R1, a current-limiting resistor R2, a voltage divider resistor R3, a current-limiting resistor R4, a delay capacitor C1, and a MOSFET Q1, wherein: The positive terminal of the device output is connected to a rectifier diode D1. The output of the rectifier diode D1 is divided into two paths. The first path outputs to the positive terminal of the filter suppression circuit, and the second path is connected to a voltage divider resistor R1. One output of the voltage divider resistor R1 is connected to a current limiting resistor R2. The output of the current limiting resistor R2 is connected to a delay capacitor C1, a voltage divider resistor R3, and the gate of a MOS transistor Q1, respectively. The output of the voltage divider resistor R1 is connected to the negative terminal of the Zener diode D2. The positive terminal of the Zener diode D2 is connected to the delay capacitor C1, the voltage divider resistor R3, the source of the MOSFET, the current limiting resistor R4, and the negative terminal of the device input. The other end of the current limiting resistor R4 is connected to the drain of the MOSFET and the negative terminal of the filter suppression circuit.

3. The circuit for preventing surge current according to claim 2, characterized in that: The fast recovery inrush current suppression circuit includes voltage divider resistors R5 and R6, transistor Q2, and some components for the inrush current suppression circuit, wherein: One end of the voltage divider resistor R5 is connected to the positive terminal of the device input terminal, and the other end of the voltage divider resistor R5 is connected to the resistor R6 and the collector of the transistor Q2. The other end of the voltage divider resistor R6 is connected to the base of the transistor Q2, and the emitter of the transistor Q2 is connected to the gate of the MOS transistor Q1.

4. The circuit for preventing surge current according to claim 3, characterized in that: The filtering and suppression circuit includes differential-mode capacitor CX1, differential-mode capacitor CX2, differential-mode inductor L1, common-mode inductor L2, common-mode capacitor CY1, and common-mode capacitor CY2, wherein: The input terminal of the differential mode inductor L1 is connected to the output terminal of the rectifier diode D1. The drain of the MOSFET is connected to the differential mode inductor L1 through a differential mode capacitor CX1. The drain of the MOSFET is connected to the output terminal of the differential mode inductor L1 through a differential mode capacitor CX2. The two ends of the differential mode capacitor CX2 are connected to the input terminal of the common mode inductor L2. The output terminal of the common mode inductor L2 is connected to the first terminal of the common mode capacitor CY1 and the first terminal of the common mode capacitor CY2, respectively. The second terminals of the common mode capacitor CY1 and the second terminal of the common mode capacitor CY2 are both connected to the chassis ground. The output terminal of the common mode inductor L2 is set as the device output terminal.

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