Bus capacitor voltage balancing circuit and photovoltaic inverter

Abstract

The utility model provides a bus capacitor voltage balancing circuit and a photovoltaic inverter. The bus capacitor voltage balancing circuit comprises a first power switch tube, a second power tube, a first inductor and a driving signal interlocking module. The first power switch tube is connected with the anode of the first bus capacitor; the second power switch tube is connected with the first power switch tube and the negative electrode of the second bus capacitor; the first inductor is connected with the first power switch tube and the cathode of the first bus capacitor. The driving signal interlocking module comprises a first NOT gate, a second NOT gate, a first AND gate and a second AND gate, the first input end of the first AND gate receives a first signal, the second input end of the first AND gate is connected with the output end of the second NOT gate, and the output end of the first AND gate is connected with the first power switch tube; the first input end of the second AND gate receives a second signal, the second input end is connected with the output end of the first NOT gate, and the output end is connected with the second power switch tube. According to the circuit, the problem that the upper power switch tube and the lower power switch tube can be conducted at the same time is solved, and the stability of a power system is improved.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a bus capacitor voltage balancing circuit and a photovoltaic inverter. Background Technology

[0002] In power systems, the stability of the DC bus voltage is crucial. The bus capacitor balancing bridge circuit dynamically adjusts the charging and discharging of the DC bus capacitor to ensure that the DC bus voltage remains within a set range, thereby maintaining the stable operation of the power system.

[0003] Existing DC bus voltage balancing technology uses two power switches to regulate the voltage values ​​of the upper and lower DC bus segments. However, these switches are modulated by a program set in an embedded processor. If the program malfunctions during operation, both switches may conduct simultaneously, causing the DC bus capacitor to release an extremely high current instantaneously, which could damage the entire power equipment. Therefore, a novel bus capacitor voltage balancing circuit is needed to prevent the simultaneous conduction of the two power switches. Utility Model Content

[0004] This application provides a bus capacitor voltage balancing circuit and a photovoltaic inverter to solve the problem of simultaneous conduction of the upper and lower power switching transistors, thereby improving the stability of the power system.

[0005] On one hand, this application provides a bus capacitor voltage balancing circuit, including:

[0006] The first power switch has a first power terminal, a second power terminal and a control terminal, wherein the first power terminal of the first power switch is connected to the positive terminal of the first bus capacitor;

[0007] The second power switch has a first power terminal, a second power terminal and a control terminal. The first power terminal of the second power switch is connected to the second power terminal of the first power switch, and the second power terminal of the second power switch is connected to the negative terminal of the second bus capacitor.

[0008] The first inductor has one end connected to the second power terminal of the first power switch transistor and the other end connected to the negative terminal of the first bus capacitor.

[0009] The drive signal interlock module includes:

[0010] A first NOT gate has a first input terminal and an output terminal for receiving a first signal, the first signal being used to drive the first power switch transistor.

[0011] The second NOT gate has a first input terminal and an output terminal for receiving a second signal, the second signal being used to drive the second power switch transistor.

[0012] The first AND gate receives the first signal at its first input terminal, its second input terminal is connected to the output terminal of the second NOT gate, and the output terminal of the first AND gate is connected to the control terminal of the first power switch.

[0013] The second AND gate receives the second signal at its first input terminal, its second input terminal is connected to the output terminal of the first NOT gate, and the output terminal of the second AND gate is connected to the control terminal of the second power switch.

[0014] Optionally, the drive signal interlock module further includes: a signal delayer having an input terminal and an output terminal, the signal delayer including a first resistor, a first capacitor and a first diode; the cathode of the first diode is connected to the input terminal of the signal delayer, and the anode of the first diode is connected to the output terminal of the signal delayer; one end of the first resistor is connected to the cathode of the first diode, the other end of the first resistor is connected to the anode of the first diode, one end of the first capacitor is connected to the anode of the first diode, and the other end of the first capacitor is grounded;

[0015] The output of the first NOT gate is connected to the second input of the second AND gate via a signal delay circuit.

[0016] The output of the second NOT gate is connected to the second input of the first AND gate via a signal delay unit.

[0017] Optionally, the drive signal interlock module further includes a third AND gate and a fourth AND gate, wherein the output of the first AND gate is connected to the control terminal of the first power switch through the third AND gate; and the output of the second AND gate is connected to the control terminal of the second power switch through the fourth AND gate.

[0018] The first input terminal of the third AND gate is connected to the output terminal of the first AND gate, the second input terminal of the third AND gate receives a drive enable signal, and the output terminal of the third AND gate is connected to the control terminal of the first power switch.

[0019] The first input terminal of the fourth AND gate is connected to the output terminal of the second AND gate, the second input terminal of the fourth AND gate receives a drive enable signal, and the output terminal of the fourth AND gate is connected to the control terminal of the second power switch.

[0020] Optionally, it further includes: an isolation driving module having a signal input terminal and a signal output terminal; the output terminal of the third AND gate is connected to the control terminal of the first power switch via the isolation driving module; the output terminal of the fourth AND gate is connected to the control terminal of the second power switch via the isolation driving module.

[0021] Optionally, the isolation driving module includes a second resistor, a second diode, and an optocoupler isolation gate driver. One end of the second resistor is connected to the signal output terminal of the isolation driving module, and the other end of the second resistor is connected to the output terminal of the optocoupler isolation gate driver. The cathode of the second diode is connected to the output terminal of the optocoupler isolation gate driver, and the anode of the second diode is connected to the signal output terminal of the isolation driving module. The input terminal of the optocoupler isolation gate driver is connected to the signal input terminal of the isolation driving module.

[0022] Optionally, the isolation driving module further includes a third resistor, a fourth resistor, and a second capacitor; one end of the third resistor is connected to the signal output terminal of the isolation driving module, the other end of the third resistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the ground terminal of the optocoupler isolation gate driver; one end of the fourth resistor is connected to the input terminal of the optocoupler isolation gate driver, and the other end of the fourth resistor is connected to the signal input terminal of the isolation driving module.

[0023] Optionally, it further includes: a current sensor, one end of the first inductor being connected to the second power terminal of the first power switch via the current sensor.

[0024] Optionally, the current sensor is a Hall current sensor.

[0025] Optionally, it further includes: an impedance matching module, one end of which is connected to the positive terminal of the first bus capacitor; the other end of which is connected to the negative terminal of the first bus capacitor;

[0026] The impedance matching module is used to adjust the total impedance between the positive terminal of the DC bus voltage and the midpoint of the DC bus voltage, so that the total impedance between the positive terminal of the DC bus voltage and the midpoint of the DC bus voltage is matched with the total impedance between the midpoint of the DC bus voltage and the negative terminal of the DC bus voltage.

[0027] Optionally, the impedance matching module includes at least one resistor.

[0028] Optionally, it also includes: a fifth electrical element and a sixth resistor;

[0029] One end of the fifth resistor is connected to the positive terminal of the first bus capacitor, and the other end of the fifth resistor is connected to the negative terminal of the first bus capacitor; one end of the sixth resistor is connected to the positive terminal of the second bus capacitor, and the other end of the sixth resistor is connected to the negative terminal of the second bus capacitor.

[0030] In a second aspect, this application provides a photovoltaic inverter, including: a bus capacitor voltage balancing circuit as described in any of the first aspects.

[0031] The bus capacitor voltage balancing circuit and photovoltaic inverter provided in this application, by adding a drive signal interlock module, realize hardware circuit interlock for the first power switch and the second power switch, ensuring that when the first power switch receives a turn-on signal, the second power switch receives a turn-off signal. This effectively prevents the first power switch and the second power switch from being turned on at the same time, thus protecting the operational safety of the photovoltaic inverter. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0033] Figure 1 This is a schematic diagram illustrating an application scenario involved in an embodiment of this application;

[0034] Figure 2 This is a schematic diagram of a bus capacitor voltage balancing circuit provided in an embodiment of this application;

[0035] Figure 3 A schematic diagram of the discharge current of a bus capacitor voltage balancing circuit provided in an embodiment of this application;

[0036] Figure 4 A schematic diagram of the charging current of a bus capacitor voltage balancing circuit provided in an embodiment of this application;

[0037] Figure 5 This is a schematic diagram of the structure of a drive signal interlock module provided in an embodiment of this application;

[0038] Figure 6 This is a schematic diagram of the structure of an isolation driver module provided in an embodiment of this application;

[0039] Figure 7 This is a partial structural schematic diagram of the second type of bus capacitor voltage balancing circuit provided in the embodiments of this application;

[0040] Figure 8 This is a partial structural schematic diagram of the third type of bus capacitor voltage balancing circuit provided in the embodiments of this application;

[0041] Figure 9 This is a schematic diagram of an impedance matching module provided in an embodiment of this application.

[0042] Explanation of reference numerals in the attached figures:

[0043] C1M - First bus capacitor; C2M - Second bus capacitor; Q1 - First power switch; Q2 - Second power switch; L1 - First inductor; 1 - Drive signal interlock module; U1F - First NOT gate; U2F - Second NOT gate; U1Y - First AND gate; U2Y - Second AND gate; U3Y - Third AND gate; U4Y - Fourth AND gate; 11 - Signal delay unit; R1 - First resistor; C1 - First capacitor; D1 - First diode; 2 - Isolation drive module; R2 - Second resistor; D2 - Second diode; 21 - Optocoupler isolated gate driver; R3 - Third resistor; R4 - Fourth resistor; C2 - Second capacitor; 3 - Current sensor; 4 - Impedance matching module; R5 - Fifth resistor; R6 - Sixth resistor.

[0044] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0046] Example 1:

[0047] One of the functions of a photovoltaic (PV) inverter is to convert direct current (DC) to alternating current (AC). The PV inverter receives DC power from photovoltaic panels or energy storage batteries and feeds it to power switching transistors, which can include any of the following: Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), also known as a MoSpin transistor, or Insulated-Gate Bipolar Transistor (IGBT). The inverter circuit, composed of these power switching transistors, converts the DC power to AC power before supplying it to the load or the power grid. The inverter circuit can be a T-type inverter, an H-bridge, or other topologies. PV inverters have a DC bus, which is defined as the common DC circuit path connected between the PV input side or the DC / DC boost circuit and the inverter circuit. Maintaining a stable DC bus voltage is crucial for PV inverters; therefore, all PV inverters are equipped with a DC bus capacitor.

[0048] Figure 1 This is a schematic diagram illustrating an application scenario involved in an embodiment of this application, such as... Figure 1 As shown, a DC-to-DC boost converter (DC / DC) is connected to the left side of the DC bus capacitor, and a DC-to-AC inverter (DC / AC) is connected to the right side. The output voltage of the photovoltaic panel varies drastically with sunlight and temperature, and this voltage is typically lower than the DC bus voltage required for grid connection. The DC-to-DC boost converter (DC / DC) boosts this voltage to a stable and sufficiently high DC voltage to ensure that the subsequent inverter (DC / AC) can effectively output a sine wave to the grid. Figure 1 The load in this context can refer to the power grid or electrical equipment. The DC bus capacitor includes several first bus capacitors C1M and several second bus capacitors C2M. The positive terminals of the first bus capacitors C1M are all connected to the positive terminal P of the DC bus voltage, and the negative terminals of the second bus capacitors C2M are all connected to the negative terminal N of the DC bus voltage. The negative terminals of the first bus capacitors C1M and the positive terminals of the second bus capacitors C2M are connected together. Figure 1 The diagram uses a single first bus capacitor C1M to represent several first bus capacitors C1M. Figure 1The same applies to the second bus capacitor C2M. The connection point of the first bus capacitor C1M and the second bus capacitor C2M constitutes the midpoint of the DC bus capacitor (also the midpoint O of the DC bus voltage). The presence of the DC bus capacitor allows the DC bus to operate stably, and it can play a role in energy storage, buffering, filtering, and voltage regulation. The inverter circuit can achieve three-level output through the DC bus capacitor. Because the DC bus capacitor must maintain neutral point balance, the voltage difference between the positive terminal P of the DC bus voltage and the midpoint O of the DC bus voltage (which can be called the upper half bus voltage) should be basically consistent with the voltage difference between the midpoint O of the DC bus voltage and the negative terminal N of the DC bus voltage (which can be called the lower half bus voltage). A large difference between the upper half bus voltage and the lower half bus voltage indicates that the neutral point of the DC bus capacitor is unbalanced. An unbalanced neutral point of the DC bus capacitor will lead to many problems such as output voltage waveform distortion, increased current distortion rate, and uneven voltage withstand by the power switching transistors. Therefore, it is necessary to set up power switching transistors to regulate the voltage of the upper and lower busbars.

[0049] Figure 2 This is a schematic diagram of a bus capacitor voltage balancing circuit provided in an embodiment of this application.

[0050] in, Figure 2 In this context, HV-HV refers to the positive terminal P of the DC bus voltage, H_GND refers to the negative terminal N of the DC bus voltage, and O refers to the midpoint O of the DC bus voltage.

[0051] like Figure 2As shown, this embodiment includes a first power switch Q1 and a second power switch Q2. Both the first power switch Q1 and the second power switch Q2 have a first power terminal, a second power terminal, and a control terminal. The first power terminal of the first power switch Q1 is connected to the positive terminal of the first bus capacitor C1M. The first power terminal of the second power switch Q2 is connected to the second power terminal of the first power switch Q1, and the second power terminal of the second power switch Q2 is connected to the negative terminal of the second bus capacitor C2M. The connection point between the second power terminal of the first power switch Q1 and the first power terminal of the second power switch Q2 is correspondingly connected to the connection point of the first bus capacitor C1M and the second bus capacitor C2M. For example, if the first power switch Q1 and the second power switch Q2 are N-type MOSFETs (with a body diode, also called a freewheeling diode), then the first power terminal is the drain, the second power terminal is the source, and the control terminal is the gate. If the first power switch Q1 and the second power switch Q2 are IGBT modules (insulated-gate bipolar transistors with a body diode, also called a freewheeling diode), then the first power terminal is the collector C, the second power terminal is the emitter E, and the control terminal is the gate G. In this embodiment, both the first power switch Q1 and the second power switch Q2 are IGBTs with body diodes. Even if a MOSFET or IGBT package without a body diode is used, but a freewheeling diode is connected in parallel in the circuit, it should still be considered as a power switch as described in this application.

[0052] like Figure 2 As shown, this embodiment includes a first inductor L1. One end of the first inductor L1 is connected to the second power terminal of the first power switch Q1 (and this end of the first inductor L1 is also connected to the first power terminal of the second power switch Q2), and the other end of the first inductor L1 is used to connect to the negative terminal of the first bus capacitor C1M (and this end of the first inductor L1 is also connected to the positive terminal of the second bus capacitor C2M). For example, the first power switch Q1 and the second power switch Q2 are packaged as an IGBT module with a body diode.

[0053] Figure 3 A schematic diagram of the discharge current of a bus capacitor voltage balancing circuit provided in this application embodiment; as shown Figure 3 As shown,

[0054] If the upper bus voltage is too high, the first bus capacitor C1M needs to be discharged. At this time, the first power switch Q1 is turned on, and the second power switch Q2 is turned off. The discharge of the first bus capacitor C1M charges the first inductor L1. During this process, the electric field energy stored in the first bus capacitor C1M is converted into magnetic field energy stored in the first inductor L1. Figure 3The arrows in the diagram represent the direction of movement of positive charges in the circuit. At this time, the polarity of the first inductor L1 is negative on the left and positive on the right (the side closer to the first power switch Q1 is positive).

[0055] Figure 4 A schematic diagram of the charging current of a bus capacitor voltage balancing circuit provided in this application embodiment; as shown Figure 4 As shown,

[0056] When the upper bus voltage drops, the first power switch Q1 turns off, and the second power switch Q2 turns on. At this time, the first inductor L1, to impede current changes, exhibits polarity of positive on the left and negative on the right (the side closer to the first power switch Q1 is negative). The first inductor L1 can then charge the second bus capacitor C2M, causing the lower bus voltage to rise, thereby reducing the absolute value of the voltage difference between the upper and lower bus voltages. If the lower bus voltage is too high, the second bus capacitor C2M needs to be discharged. In this case, the first power switch Q1 turns off, and the second power switch Q2 turns on. Figure 4 The arrows in the diagram represent the direction of movement of positive charges in the circuit.

[0057] Similarly, the second bus capacitor C2M charges the first inductor L1. At this time, the polarity of the first inductor L1 is positive on the left and negative on the right (the side closer to the first power switch Q1 is negative). When the lower half bus voltage drops, the second power switch Q2 is turned off and the first power switch Q1 is turned on. In order to impede the change in current, the first inductor L1 presents a polarity of negative on the left and positive on the right (the side closer to the first power switch Q1 is positive). The first inductor L1 charges the first bus capacitor C1M, and the upper half bus voltage begins to rise, thereby reducing the absolute value of the voltage difference between the upper half bus voltage and the lower half bus voltage.

[0058] The switching on of the first power switch Q1 and the second power switch Q2 is controlled by PWM waves emitted by the embedded processor of the photovoltaic inverter. That is, the switching on or off of the first power switch Q1 is controlled by one PWM wave, and the switching on or off of the second power switch Q2 is controlled by another PWM wave. How to modulate the switching on or off of the first power switch Q1 and the second power switch Q2 using PWM waves is existing technology and will not be elaborated in this embodiment. The embedded processor includes any of the following: ARM microcontroller, DSP (Digital Signal Processor), etc.

[0059] Therefore, to prevent the first power switch Q1 and the second power switch Q2 from being turned on simultaneously, a software dead time is added to the modulation strategy, meaning there is a brief period where both the first power switch Q1 and the second power switch Q2 are off. During this time, the first inductor L1 will charge the first bus capacitor C1M through the body diode of the first power switch Q1, or charge the second bus capacitor C2M through the body diode of the second power switch Q2.

[0060] The program controls the first power switch Q1 and the second power switch Q2 to prevent them from conducting simultaneously. However, the program may malfunction or crash. Therefore, it is necessary to introduce hardware circuitry to ensure that the first power switch Q1 and the second power switch Q2 cannot conduct simultaneously. Thus, as shown in Figure 2, this embodiment also includes a drive signal interlock module 1. The drive signal interlock module 1 includes a first NOT gate U1F and a second NOT gate U2F, which are NOT gates in logic. The first NOT gate U1F and the second NOT gate U2F can be provided by one or more NOT gate chips. The first NOT gate U1F has a first input terminal and an output terminal for receiving a first signal. The first NOT gate U1F inverts the first signal and outputs an inverted signal (defined as the first inverted signal). The second NOT gate U2F has a first input terminal and an output terminal for receiving a second signal. The second NOT gate U2F inverts the second signal and outputs an inverted signal (defined as the second inverted signal). An inverted signal is a signal that is completely opposite in phase (180 degrees out of phase) and logically opposite (such as 0 and 1) to the original signal, representing a direct inversion of the logical value. Both the first and second signals are PWM waves generated by the embedded processor.

[0061] like Figure 2 As shown, the drive signal interlock module 1 also includes a first AND gate U1Y and a second AND gate U2Y. Both the first AND gate U1Y and the second AND gate U2Y are AND gates of logic gates. The first AND gate U1Y and the second AND gate U2Y can be provided by one or more AND gate chips. The first input terminal of the first AND gate U1Y receives a first signal, the second input terminal of the first AND gate U1Y is connected to the output terminal of the second NOT gate U2F, and the output terminal of the first AND gate U1Y is connected to the control terminal of the first power switch Q1. The first input terminal of the second AND gate U2Y receives a second signal, the second input terminal of the second AND gate U2Y is connected to the output terminal of the first NOT gate U1F, and the output terminal of the second AND gate U2Y is connected to the control terminal of the second power switch Q2.

[0062] The first signal is used to drive the first power switch Q1, and the second signal is used to drive the second power switch Q2.

[0063] When the upper bus voltage is too high, the first power switch Q1 needs to be turned on while the second power switch Q2 is turned off. At this time, the first signal should be high, the second signal should be low, the first inverted signal should be low, and the second inverted signal should be high. The first AND gate U1Y outputs a first drive signal after performing a logical AND operation between the first signal and the second inverted signal. This first drive signal drives the first power switch Q1. When the first drive signal is high, the first power switch Q1 is turned on; when it is low, it is turned off. If the second signal remains low, the first drive signal effectively becomes the first signal, changing with the first signal. If the second signal output fluctuates and reaches a high level, the first drive signal will be quickly pulled low, turning off the first power switch Q1. This prevents the first and second power switches Q1 from being turned on simultaneously.

[0064] Similarly, when the voltage on the lower bus is too high, the second AND gate U2Y outputs a second drive signal after performing a logical AND operation between the second signal and the first inverted signal. This second drive signal is used to drive the second power switch Q2. If the first signal remains low at this time, the second drive signal is essentially the second signal, and it changes with the second signal. Likewise, if the first signal output fluctuates and becomes low, the second drive signal will be quickly pulled low, and the second power switch Q2 will turn off.

[0065] By adding the drive signal interlock module 1, the simultaneous conduction of the first power switch Q1 and the second power switch Q2 is effectively prevented, thus protecting the safe operation of the photovoltaic inverter.

[0066] The embedded processor can use existing technology to determine the voltage difference between the upper half bus voltage and the lower half bus voltage, and then control the conduction and shutdown of the first power switch Q1 and the second power switch Q2 based on the voltage difference. Therefore, this embodiment will not elaborate further.

[0067] In summary, the bus capacitor voltage balancing circuit provided in this application, by adding a drive signal interlock module, achieves hardware circuit interlock for the first power switch and the second power switch, ensuring that when the first power switch receives a turn-on signal, the second power switch receives a turn-off signal. This effectively prevents the first and second power switches from turning on simultaneously, protecting the operational safety of the photovoltaic inverter.

[0068] Example 2:

[0069] This embodiment is a further optimization based on implementation one.

[0070] Figure 5This is a schematic diagram of the structure of a drive signal interlock module provided in an embodiment of this application, as shown below. Figure 5 As shown, the drive signal interlock module 1 also includes a signal delay unit 11. The signal delay unit 11 has an input terminal and an output terminal. The signal delay unit 11 includes a first resistor R1, a first capacitor C1, and a first diode D1. The cathode of the first diode D1 is connected to the input terminal of the signal delay unit 11, and the anode of the first diode D1 is connected to the output terminal of the signal delay unit 11. One end of the first resistor R1 is connected to the cathode of the first diode D1, and the other end of the first resistor R1 is connected to the anode of the first diode D1. One end of the first capacitor C1 is connected to the anode of the first diode D1, and the other end of the first capacitor C1 is grounded. The signal delay unit 11 is essentially an RC filter with a reverse diode connected in parallel. The cathode of this diode is connected to the output terminal of a NAND gate, and the anode of this diode is connected to an input terminal of an AND gate. When the signal output by the NOT gate flips from a low level to a high level, the diode is reverse-biased and cut off. After passing through signal delay unit 11, the rise time of the signal is extended. This is because the signal enters from the input of signal delay unit 11, passes through a resistor, and then charges a capacitor. The capacitor is charged until the potential at the junction of the capacitor and the resistor reaches a certain threshold (enough for the input of the AND gate to recognize it as high). The time it takes for the capacitor to reach this threshold is the signal delay time. When the signal output from the NOT gate flips from high to low, the capacitor begins to discharge, the diode is forward-biased and conducts, accelerating the discharge, thus causing minimal delay.

[0071] The output of the first NOT gate U1F is connected to the second input of the second AND gate U2Y via a signal delay unit 11. The first inverted signal output by the first NOT gate U1F is sent to the second input of the second AND gate U2Y via the signal delay unit 11. The output of the second NOT gate U2F is connected to the second input of the first AND gate U1Y via a signal delay unit 11. The second inverted signal output by the second NOT gate U2F is sent to the second input of the first AND gate U1Y via the signal delay unit 11. In this embodiment, signal delay units 11 are provided at the outputs of both the first NOT gate U1F and the second NOT gate U2F to delay the time for the low level to flip to the high level. For example, when adjusting the upper half bus voltage, the first power switch Q1 is turned off, and the second power switch Q2 needs to be turned on. When the first signal changes from high to low, the corresponding first inverted signal changes from low to high. The signal delay unit 11 delays the time it takes for the second input terminal of the second power switch Q2 to receive the high-level first inverted signal, thus delaying the time it takes for the second drive signal to become high, and consequently delaying the turn-on time of the second power switch Q2. In this embodiment, the drive signal interlock module 1 creates a hardware dead time, which, in conjunction with the software dead time set in the program, greatly avoids the simultaneous conduction of the first power switch Q1 and the second power switch Q2, improving the safety of the bus voltage balancing circuit and ensuring the stable operation of the photovoltaic inverter.

[0072] Example 3:

[0073] This embodiment is a further optimization based on Embodiment 2. For example... Figure 5 As shown, the drive signal interlock module 1 also includes a third AND gate U3Y and a fourth AND gate U4Y. The output of the first AND gate U1Y is connected to the control terminal of the first power switch Q1 through the output of the third AND gate U3Y; the output of the second AND gate U2Y is connected to the control terminal of the second power switch Q2 through the output of the fourth AND gate U4Y.

[0074] The first input of the third AND gate U3Y is connected to the output of the first AND gate U1Y. The second input of the third AND gate U3Y receives the drive enable signal, and the output of the third AND gate U3Y is connected to the control terminal of the first power switch Q1. The first input of the fourth AND gate U4Y is connected to the output of the second AND gate U2Y. The second input of the fourth AND gate U4Y receives the drive enable signal, and the output of the fourth AND gate U4Y is connected to the control terminal of the second power switch Q2. When the drive enable signal is high, the signal output by the third AND gate U3Y is the first drive signal, and the signal output by the fourth AND gate U4Y is the second drive signal. When the drive enable signal is low, the signal output by the third AND gate U3Y is low and does not change regardless of the first drive signal; similarly, the signal output by the fourth AND gate U4Y is low and does not change regardless of the second drive signal. The drive enable signal can be issued by the embedded processor or threshold detection circuit of the photovoltaic inverter. If the photovoltaic inverter experiences an abnormal situation, such as excessive current output requiring an emergency shutdown, the embedded processor issues a low-level drive enable signal, or the detection circuit detects that the current has reached a certain threshold and outputs a drive enable signal. This turns off both the first power switch Q1 and the second power switch Q2, which are used to regulate the DC bus voltage. Simultaneously, this drive enable signal also shuts down other circuits of the photovoltaic inverter, effectively protecting the inverter in abnormal situations and ensuring the safety of maintenance personnel. How the drive enable signal is generated is existing technology and will not be elaborated upon in this application.

[0075] Example 4:

[0076] This embodiment is a further optimization based on Embodiment 3.

[0077] Figure 6 This is a schematic diagram of the structure of an isolated driver module provided in an embodiment of this application, as shown below. Figure 6 As shown, it also includes an isolation driver module 2 with signal input and signal output terminals; the output terminal of the third AND gate U3Y is connected to the control terminal of the first power switch Q1 via the isolation driver module 2; the output terminal of the fourth AND gate U4Y is connected to the control terminal of the second power switch Q2 via the isolation driver module 2. The function of the isolation driver module 2 is to achieve electrical safety isolation, separating the low-voltage control circuit from the high-voltage main power circuit, preventing high voltage from entering the control circuit and causing damage. The type of isolation driver module 2 can be optocoupler isolation, magnetic isolation, capacitive isolation, etc. This embodiment uses optocoupler isolation.

[0078] The isolation drive module 2 in this embodiment includes a second resistor R2, a second diode D2, and an optocoupler isolation gate driver 21. One end of the second resistor R2 is connected to the signal output terminal of the isolation drive module 2, and the other end is connected to the output terminal of the optocoupler isolation gate driver 21. The cathode of the second diode D2 is connected to the output terminal of the optocoupler isolation gate driver 21, and the anode of the second diode D2 is connected to the signal output terminal of the isolation drive module 2. The input terminal of the optocoupler isolation gate driver 21 is connected to the signal input terminal of the isolation drive module 2. The input terminal of the optocoupler isolation gate driver 21 receives a first drive signal or a second drive signal, and the optocoupler isolation gate driver 21 outputs a drive signal for turning on or off the power switch transistor. This drive signal is consistent with the first drive signal or the second drive signal. The aforementioned drive signal enters the gate of the first power switch transistor Q1 or the second power switch transistor Q2 through the second resistor R2, and the second resistor R2 serves as a current limiter. Because power switching transistors (MOSFETs, IGBTs, etc.) have parasitic capacitance, the power switching transistor needs to be discharged to a certain extent to turn off. Therefore, the second diode D2 provides a low-impedance discharge path for the power switching transistor, accelerates the discharge of parasitic capacitance, and shortens the turn-off time of the power switching transistor.

[0079] The isolation driver module 2 in this embodiment also includes a third resistor R3, a fourth resistor R4, and a second capacitor C2. One end of the third resistor R3 is connected to the signal output terminal of the isolation driver module 2, and another end of the third resistor R3 is connected to one end of the second capacitor C2. The other end of the second capacitor C2 is connected to the ground terminal of the optocoupler isolated gate driver 21. The function of the third resistor R3 and the second capacitor C2 is to suppress high-frequency oscillation of the gate voltage of the power switch and to prevent false turn-on caused by the Miller effect. One end of the fourth resistor R4 is connected to the input terminal of the optocoupler isolated gate driver 21, and the other end of the fourth resistor R4 is connected to the signal input terminal of the isolation driver module 2. The fourth resistor R4 serves as a current limiter. Existing technology can be used to connect the power supply voltage and ground to the optocoupler isolated gate driver 21. It is worth noting that, as... Figure 6 (a) and Figure 7 As shown, the ground (referred to as S-H5) of the optocoupler isolated gate driver 21 used to receive the first drive signal is the midpoint of the connected DC bus capacitor, which is the second power terminal (source E) of the first power switch Q1. This is to ensure that the first power switch can be driven normally, which is the existing theory, so it will not be described again in this embodiment.

[0080] like Figure 6The optocoupler-isolated gate driver 21, which receives the first drive signal, outputs a drive signal G-H5 to the first power switch Q1, and the optocoupler-isolated gate driver 21, which receives the second drive signal, outputs a drive signal G-H6 to the second power switch Q2. In the figure, VCC refers to the power supply voltage, which is generally 15V.

[0081] The optocoupler isolated gate driver 21 selected in this embodiment can be a TLP152.

[0082] Example 5:

[0083] This embodiment is a further optimization based on Embodiment 4.

[0084] Figure 7 This is a partial structural schematic diagram of the second type of bus capacitor voltage balancing circuit provided in the embodiments of this application, as shown below. Figure 7 As shown, it also includes a current sensor 3. One end of the first inductor L1 is connected to the second power terminal of the first power switch Q1 through the current sensor 3. The current sensor 3 is a Hall current sensor, and the signal of the Hall current sensor can use VAC_4646-X661-83 or STK-32PL. The Hall current sensor can provide isolation between the current of the bus capacitor voltage balancing circuit and the current of the low-voltage control circuit. By installing the Hall current sensor between the connection point of the first inductor L1 and the two power switches, the balancing current flowing through the first inductor L1 can be directly measured. Since the flow of the above-mentioned balancing current is bidirectional (flowing from the first bus capacitor C1M to the second bus capacitor C2M, or from the second bus capacitor C2M to the first bus capacitor C1M), the Hall current sensor can output corresponding positive and negative voltage signals by measuring the current flow direction, providing the embedded processor with the determination of the current direction and the detection of the current magnitude flowing through the first power switch Q1 or the second power switch Q2. If the current flowing through the first power switch Q1 or the second power switch Q2 is too large, the embedded processor of the photovoltaic inverter will adjust the duty cycle of the first power switch Q1 or the second power switch Q2 to protect the first power switch Q1, the second power switch Q2, and the entire photovoltaic inverter. This installation simplifies the circuit design and eliminates the need for an additional sampling resistor. In this embodiment, the Hall current sensor is powered by 5V (H+5V in the figure). Its REF terminal outputs a Balcan-CUR_REF signal, and its OUT terminal outputs a Balcan-CUR signal. The Balcan-CUR_REF signal and the Balcan-CUR signal are passed to the next stage sampling amplification circuit. This sampling amplification circuit can use existing technology, so it will not be described in detail in this embodiment.

[0085] The methods by which the Hall current sensor converts the current flowing through it into a sampling signal and transmits it to the embedded processor for processing, and how the embedded processor outputs a first signal and a second signal based on the sampling signal, are existing technologies and will not be elaborated in this embodiment.

[0086] Example 6:

[0087] This embodiment is a further optimization based on any one of the embodiments from Embodiment 1 to Embodiment 5.

[0088] Figure 8 This is a partial structural schematic diagram of the third type of bus capacitor voltage balancing circuit provided in the embodiments of this application, as shown below. Figure 8 As shown, it also includes an impedance matching module 4, one end of which is connected to the positive terminal of the first bus capacitor C1M; the other end of the impedance matching module 4 is connected to the negative terminal of the first bus capacitor C1M.

[0089] Impedance matching module 4 is used to adjust the total impedance between the positive terminal P of the DC bus voltage and the midpoint O of the DC bus voltage, so that the total impedance between the positive terminal P of the DC bus voltage and the midpoint O of the DC bus voltage is matched with the total impedance between the midpoint O of the DC bus voltage and the negative terminal N of the DC bus voltage.

[0090] In practical applications, to monitor the stability of the power system, it is necessary to detect the output voltage at the output point of the inverter circuit of the photovoltaic inverter. Therefore, it is also necessary to sample the voltage at the midpoint O of the DC bus voltage to obtain the sampling voltage at the midpoint O of the DC bus voltage. For a three-phase photovoltaic inverter, the output voltages of the R-phase inverter circuit, S-phase inverter circuit, and T-phase inverter circuit need to be sampled to obtain the R-phase sampling voltage, S-phase sampling voltage, and T-phase sampling voltage, respectively. For example, the R-phase sampling voltage is connected to the non-inverting input of a differential operational amplifier, and the DC bus voltage midpoint O sampling voltage is connected to the inverting input of the same differential operational amplifier. The output signal of the differential operational amplifier is then processed by an embedded processor. The sampling of the DC bus voltage midpoint O is achieved by connecting several resistors in series. That is, the DC bus voltage midpoint O is connected to the inverting input of the differential operational amplifier through multiple series-connected large resistors, which are defined as the R-phase sampling resistor network. Since the signal ground of the differential operational amplifier is connected to the negative terminal N of the DC bus voltage (i.e., the power ground of the DC bus) in practical applications (not directly connected), this sampling is not necessary. Therefore, the R-phase sampling resistor network is equivalent to being connected in parallel with the second bus capacitor C2M, which changes the total impedance between the DC bus voltage midpoint O and the DC bus voltage negative terminal N. This causes the total impedance between the DC bus voltage positive terminal P and the DC bus voltage midpoint O to be inconsistent with the impedance between the DC bus voltage positive terminal P and the DC bus voltage midpoint O. This leads to the frequent activation of the bus capacitor voltage balancing circuit to adjust the voltage of the first bus capacitor C1M and the second bus capacitor C2M, resulting in power loss and reduced system efficiency. Similarly, there are also S-phase and T-phase sampling resistor networks. The S-phase and T-phase sampling resistor networks are connected in parallel with the second bus capacitor C2M. Therefore, for the DC bus voltage midpoint O and the DC bus voltage negative terminal N, the equivalent impedance after the parallel connection of the R-phase, S-phase, and T-phase sampling resistor networks is increased.

[0091] Figure 9 This is a schematic diagram of the structure of an impedance matching module provided in an embodiment of this application, as shown below. Figure 9 As shown,

[0092] The impedance matching module includes one resistor. The resistance value of this resistor must match the equivalent impedance described above. If the impedance matching module 4 includes two resistors, the total resistance of these two resistors connected in series or parallel must match the equivalent impedance described above. If the impedance matching module 4 includes at least three resistors, the total resistance of these at least three resistors connected in series or parallel must match the equivalent impedance described above. This ensures that the total impedance between the positive terminal P of the DC bus voltage and the midpoint O of the DC bus voltage, and the total impedance between the midpoint O of the DC bus voltage and the negative terminal N of the DC bus voltage, are matched. Figure 9 The resistor in impedance matching module 4 is represented by RX.

[0093] The bus capacitor voltage balancing circuit also includes a fifth resistor R5 and a sixth resistor R6. One end of the fifth resistor R5 is connected to the positive terminal of the first bus capacitor C1M, and the other end is connected to the negative terminal of the first bus capacitor C1M. One end of the sixth resistor R6 is connected to the positive terminal of the second bus capacitor C2M, and the other end is connected to the negative terminal of the second bus capacitor C2M. If the photovoltaic inverter needs to be shut down for maintenance, the first bus capacitor C1M and the second bus capacitor C2M need to be discharged to ensure the safety of maintenance personnel. In this case, the fifth resistor R5 forms the discharge circuit for the first bus capacitor C1M, and the sixth resistor R6 forms the discharge circuit for the second bus capacitor C2M.

[0094] Example 7:

[0095] A photovoltaic inverter includes a bus capacitor voltage balancing circuit according to any one of embodiments one through six. The photovoltaic inverter of this embodiment can regulate the DC bus voltage and effectively ensure that the first power switch Q1 and the second power switch Q2 of the balancing circuit do not conduct simultaneously, thus ensuring the stable operation of the photovoltaic inverter.

[0096] It is worth emphasizing that the connection in this application should be understood to include direct electrical connection as well as indirect electrical connection including but not limited to conventional intermediate components such as isolation devices, driving devices, and buffer devices. As long as the signal is transmitted from component A to component B, it falls within the protection scope of this application.

[0097] In addition, in the accompanying drawings of this application, lines crossing each other with a dot indicate that these lines are connected together. Lines without a dot indicate that they are not connected. Refer to the circuit schematic design.

[0098] The use of Chinese and English symbols on circuit connection lines (such as first signal, first drive signal, G-H5, S-H5, Balance-CUR_REF representing signal input and output points; the appearance of the same Chinese and English symbols in different diagrams indicates that they are connected) is a common practice in circuit schematics, so this application will not elaborate further.

[0099] The above embodiments are merely preferred embodiments of the present utility model and are not intended to limit the scope of protection of the present utility model. Therefore, all equivalent changes made to the structure, shape, and principle of the present utility model should be covered within the scope of protection of the present utility model.

[0100] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and are not intended to limit the scope of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this invention, should still fall within the scope of the disclosed technical content. Furthermore, the terms "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of this invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this invention.

[0101] It should also be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on the other component or may be connected to an intermediary component. When a component is referred to as being "connected to" another component, it can be directly connected to the other component or indirectly connected to the other component through an intermediary component.

[0102] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

Claims

1. A bus capacitor voltage balancing circuit, characterized in that, include: The first power switch (Q1) has a first power terminal, a second power terminal and a control terminal. The first power terminal of the first power switch (Q1) is connected to the positive terminal of the first bus capacitor (C1M). The second power switch (Q2) has a first power terminal, a second power terminal and a control terminal. The first power terminal of the second power switch (Q2) is connected to the second power terminal of the first power switch (Q1), and the second power terminal of the second power switch (Q2) is connected to the negative terminal of the second bus capacitor (C2M). The first inductor (L1) has one end connected to the second power terminal of the first power switch (Q1) and the other end connected to the negative terminal of the first bus capacitor (C1M). The drive signal interlock module (1) includes: The first NOT gate (U1F) has a first input terminal and an output terminal for receiving a first signal, the first signal being used to drive the first power switch (Q1). The second NOT gate (U2F) has a first input terminal and an output terminal for receiving a second signal, which is used to drive the second power switch (Q2). The first AND gate (U1Y) receives the first signal at its first input terminal, and its second input terminal is connected to the output terminal of the second NOT gate (U2F). The output terminal of the first AND gate (U1Y) is connected to the control terminal of the first power switch (Q1). The second AND gate (U2Y) receives the second signal at its first input terminal and is connected to the output terminal of the first NOT gate (U1F). The output terminal of the second AND gate (U2Y) is connected to the control terminal of the second power switch (Q2).

2. The bus capacitor voltage balancing circuit according to claim 1, characterized in that, The drive signal interlock module (1) further includes: a signal delayer (11) having an input terminal and an output terminal, the signal delayer (11) including a first resistor (R1), a first capacitor (C1) and a first diode (D1); the cathode of the first diode (D1) is connected to the input terminal of the signal delayer (11), and the anode of the first diode (D1) is connected to the output terminal of the signal delayer (11); one end of the first resistor (R1) is connected to the cathode of the first diode (D1), the other end of the first resistor (R1) is connected to the anode of the first diode (D1), one end of the first capacitor (C1) is connected to the anode of the first diode (D1), and the other end of the first capacitor (C1) is grounded; The output of the first NOT gate (U1F) is connected to the second input of the second AND gate (U2Y) via a signal delay unit (11); The output of the second NOT gate (U2F) is connected to the second input of the first AND gate (U1Y) via a signal delay unit (11).

3. The bus capacitor voltage balancing circuit according to claim 2, characterized in that, The drive signal interlock module (1) further includes a third AND gate (U3Y) and a fourth AND gate (U4Y). The output terminal of the first AND gate (U1Y) is connected to the control terminal of the first power switch (Q1) through the third AND gate (U3Y); the output terminal of the second AND gate (U2Y) is connected to the control terminal of the second power switch (Q2) through the fourth AND gate (U4Y). The first input terminal of the third AND gate (U3Y) is connected to the output terminal of the first AND gate (U1Y), the second input terminal of the third AND gate (U3Y) receives the drive enable signal, and the output terminal of the third AND gate (U3Y) is connected to the control terminal of the first power switch (Q1). The first input terminal of the fourth AND gate (U4Y) is connected to the output terminal of the second AND gate (U2Y), the second input terminal of the fourth AND gate (U4Y) receives the drive enable signal, and the output terminal of the fourth AND gate (U4Y) is connected to the control terminal of the second power switch (Q2).

4. The bus capacitor voltage balancing circuit according to claim 3, characterized in that, Also includes: An isolation drive module (2) has a signal input terminal and a signal output terminal; the output terminal of the third AND gate (U3Y) is connected to the control terminal of the first power switch (Q1) via the isolation drive module (2); the output terminal of the fourth AND gate (U4Y) is connected to the control terminal of the second power switch (Q2) via the isolation drive module (2).

5. The bus capacitor voltage balancing circuit according to claim 4, characterized in that, The isolation drive module (2) includes a second resistor (R2), a second diode (D2), and an optocoupler isolation gate driver (21). One end of the second resistor (R2) is connected to the signal output terminal of the isolation drive module (2), and the other end of the second resistor (R2) is connected to the output terminal of the optocoupler isolation gate driver (21). The cathode of the second diode (D2) is connected to the output terminal of the optocoupler isolation gate driver (21), and the anode of the second diode (D2) is connected to the signal output terminal of the isolation drive module (2). The input terminal of the optocoupler isolation gate driver (21) is connected to the signal input terminal of the isolation drive module (2).

6. The bus capacitor voltage balancing circuit according to claim 5, characterized in that, The isolation drive module (2) further includes a third resistor (R3), a fourth resistor (R4), and a second capacitor (C2); one end of the third resistor (R3) is connected to the signal output terminal of the isolation drive module (2), the other end of the third resistor (R3) is connected to one end of the second capacitor (C2), and the other end of the second capacitor (C2) is connected to the ground terminal of the optocoupler isolation gate driver (21); one end of the fourth resistor (R4) is connected to the input terminal of the optocoupler isolation gate driver (21), and the other end of the fourth resistor (R4) is connected to the signal input terminal of the isolation drive module (2).

7. The bus capacitor voltage balancing circuit according to claim 6, characterized in that, Also includes: A current sensor (3) is provided, and one end of the first inductor (L1) is connected to the second power terminal of the first power switch (Q1) through the current sensor (3).

8. The bus capacitor voltage balancing circuit according to claim 7, characterized in that, The current sensor (3) is a Hall current sensor.

9. The bus capacitor voltage balancing circuit according to any one of claims 1-8, characterized in that, Also includes: Impedance matching module (4), one end of which is connected to the positive terminal of the first bus capacitor (C1M); the other end of which is connected to the negative terminal of the first bus capacitor (C1M). The impedance matching module (4) is used to adjust the total impedance between the positive terminal of the DC bus voltage and the midpoint of the DC bus voltage so that the total impedance between the positive terminal of the DC bus voltage and the midpoint of the DC bus voltage is matched with the total impedance between the midpoint of the DC bus voltage and the negative terminal of the DC bus voltage.

10. The bus capacitor voltage balancing circuit according to claim 9, characterized in that, The impedance matching module (4) includes at least one resistor.

11. The bus capacitor voltage balancing circuit according to claim 9, characterized in that, Also includes: The fifth resistor (R5) and the sixth resistor (R6); One end of the fifth resistor (R5) is connected to the positive terminal of the first bus capacitor (C1M), and the other end of the fifth resistor (R5) is connected to the negative terminal of the first bus capacitor (C1M); one end of the sixth resistor (R6) is connected to the positive terminal of the second bus capacitor (C2M), and the other end of the sixth resistor (R6) is connected to the negative terminal of the second bus capacitor (C2M).

12. A photovoltaic inverter, characterized in that, Includes the bus capacitor voltage balancing circuit as described in any one of claims 1-11.

Images