Power amplifier and radio frequency front-end module

Abstract

The utility model relates to the technical field of radio frequency, in particular to a power amplifier and a radio frequency front-end module. The power amplifier comprises at least two stages of power amplification circuits and an inter-stage matching circuit, the inter-stage matching circuit comprises a plurality of matching inductors, and at least one matching inductor is configured to be of a first inductor structure or a second inductor structure; wherein the first inductor structure comprises at least one bonding wire, the first end of the bonding wire is connected to the first bonding pad, and the second end of the bonding wire is connected to the second bonding pad; the second inductor structure comprises a plurality of metal wires, the first ends of at least two metal wires in the plurality of metal wires are connected to the first node, and the second ends of at least two metal wires in the plurality of metal wires are connected to the second node. The matching inductor provided by the utility model can have a relatively high Q value while realizing a relatively small inductance value, and the loss of a radio-frequency signal is reduced.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a power amplifier and a radio frequency front-end module. Background Technology

[0002] In a power amplifier with multi-stage power amplifier circuits, an interstage impedance matching circuit is usually set between the previous stage power amplifier circuit and the next stage power amplifier circuit. The interstage impedance matching circuit generally includes components such as inductors and capacitors. The Q value (quality factor) of components such as capacitors and inductors will affect the loss of radio frequency signals. Therefore, power amplifiers require these components to have a high Q value.

[0003] Power amplifier circuits and interstage impedance matching circuits are usually integrated within the chip. However, when inductors are wound inside the chip, it is difficult to achieve a high Q value with a small inductance. Utility Model Content

[0004] In view of the above problems, this application provides a power amplifier and a radio frequency front-end module to solve the above technical problems.

[0005] This application provides a power amplifier, including:

[0006] At least two stages of power amplifier circuitry, wherein the two stages of power amplifier circuitry include a first power amplifier circuit and a second power amplifier circuit; and

[0007] An interstage matching circuit is connected between the first power amplifier circuit and the second power amplifier circuit. The interstage matching circuit includes a plurality of matching inductors, at least one of the matching inductors being configured as a first inductor structure or a second inductor structure.

[0008] The first inductor structure includes at least one bonding wire, a first end of which is connected to a first pad, a second end of which is connected to a second pad, and at least one of the first pad and the second pad is connected to the connection path between the first power amplifier circuit and the second power amplifier circuit.

[0009] The second inductor structure includes a plurality of metal traces, at least two of which have their first ends connected to a first node, and at least two of which have their second ends connected to a second node. At least one of the first node and the second node is connected to the connection path.

[0010] Optionally, both the first power amplifier circuit and the second power amplifier circuit are configured as differential amplifier circuits, with the first output terminal of the first power amplifier circuit connected to the first input terminal of the second power amplifier circuit, and the second output terminal of the first power amplifier circuit connected to the second input terminal of the second power amplifier circuit.

[0011] The first pad is disposed on the connection path between the first output terminal of the first power amplifier circuit and the first input terminal of the second power amplifier circuit;

[0012] The second pad is disposed on the connection path between the second output terminal of the first power amplifier circuit and the second input terminal of the second power amplifier circuit.

[0013] Optionally, the power amplifier is disposed within a chip, and the chip is disposed on a substrate;

[0014] Both the first power amplifier circuit and the second power amplifier circuit are configured as single-ended amplifier circuits, and the output terminal of the first power amplifier circuit is connected to the input terminal of the second power amplifier circuit.

[0015] The first pad is disposed on the connection path between the output terminal of the first power amplifier circuit and the input terminal of the second power amplifier circuit, and the second pad is disposed on the substrate and grounded.

[0016] Optionally, the first inductor includes a plurality of bonding wires connected in parallel, with a first end of each bonding wire connected to a corresponding first pad and a second end of each bonding wire connected to a corresponding second pad.

[0017] Optionally, when the operating frequency band of the power amplifier is higher than the first preset frequency band, the interstage matching circuit includes the first inductor structure and / or the second inductor structure;

[0018] When the operating frequency band of the power amplifier is lower than the second preset frequency band, the interstage matching circuit includes at least the second inductor structure;

[0019] Wherein, the second preset frequency band is lower than or equal to the first preset frequency band.

[0020] Optionally, the inductance value of the first inductor structure is 0.1-0.4nH.

[0021] Optionally, the inductance value of the second inductor structure is 0.1-1nH.

[0022] Optionally, the first node and the second node are spaced apart on a first straight line;

[0023] The at least two metal traces include a first metal trace and a second metal trace, wherein the first metal trace and the second metal trace are located on the same side or different sides of the first straight line.

[0024] Optionally, the first metal trace and the second metal trace are arranged symmetrically about the first straight line.

[0025] Optionally, the first node and the second node are spaced apart on a first straight line;

[0026] The first metal trace is symmetrical about the second straight line, and the second metal trace is symmetrical about the second straight line, wherein the second straight line intersects the first straight line.

[0027] Optionally, the middle portions of the first metal trace and the middle portions of the second metal trace converge at at least one third node;

[0028] Alternatively, the middle sections of the first metal trace and the second metal trace do not merge.

[0029] Optionally, at least one of the matching inductors is configured as a third inductor structure, the inductance of which is greater than or equal to 0.8nH.

[0030] Optionally, the third inductor structure is configured as a spiral coil structure, and at least one end of the third inductor structure is connected to the connection path.

[0031] Optionally, two of the plurality of matching inductors include a first matching inductor and a second matching inductor, wherein the inductance value of the first matching inductor is greater than the inductance value of the second matching inductor;

[0032] The first matching inductor is connected in series between the first power amplifier circuit and the second power amplifier circuit, and the second matching inductor is connected in parallel between the first matching inductor and the second power amplifier circuit.

[0033] Optionally, the first matching inductor is configured as the third inductor structure, and the second matching inductor is configured as either the first inductor structure or the second inductor structure.

[0034] Optionally, the first matching inductor is configured as the second inductor structure, and the second matching inductor is configured as either the first inductor structure or the second inductor structure.

[0035] Optionally, the interstage matching circuit further includes a first matching capacitor and a second matching capacitor, wherein the first matching capacitor is connected in parallel between the first power amplifier circuit and the first matching inductor, and the second matching capacitor is connected in series between the second matching inductor and the second power amplifier circuit.

[0036] Optionally, two of the plurality of matching inductors include a third matching inductor and a fourth matching inductor, wherein the inductance value of the third matching inductor is greater than the inductance value of the fourth matching inductor;

[0037] The third matching inductor is connected in parallel between the first power amplifier circuit and the second power amplifier circuit, and the fourth matching inductor is connected in parallel between the third matching inductor and the second power amplifier circuit.

[0038] Optionally, the third matching inductor is configured as the third inductor structure, and the fourth matching inductor is configured as the first inductor structure or the second inductor structure.

[0039] Optionally, the third matching inductor is configured as the second inductor structure, and the fourth matching inductor is configured as either the first inductor structure or the second inductor structure.

[0040] Optionally, both the first power amplifier circuit and the second power amplifier circuit are configured as single-ended amplifier circuits, and the interstage matching circuit further includes a first matching capacitor and a second matching capacitor.

[0041] Wherein, the first end of the third matching inductor is connected to the output end of the first power amplifier circuit, and the second end of the third matching inductor is grounded;

[0042] The first end of the fourth matching inductor is connected to the first end of the third matching inductor through the first matching capacitor and to the first input terminal of the second power amplifier circuit through the second matching capacitor. The second end of the fourth matching inductor is grounded.

[0043] Optionally, both the first power amplifier circuit and the second power amplifier circuit are configured as differential amplifier circuits, and the interstage matching circuit further includes a first matching capacitor, a second matching capacitor, a third matching capacitor and a fourth matching capacitor.

[0044] Wherein, the first end of the third matching inductor is connected to the first output terminal of the first power amplifier circuit, and the second end of the third matching inductor is connected to the second output terminal of the first power amplifier circuit;

[0045] The first end of the fourth matching inductor is connected to the first end of the third matching inductor through the first matching capacitor and to the first input terminal of the second power amplifier circuit through the second matching capacitor. The second end of the fourth matching inductor is connected to the second end of the third matching inductor through the third matching capacitor and to the second input terminal of the second power amplifier circuit through the fourth matching capacitor.

[0046] Optionally, the first matching capacitor and the third matching capacitor are arranged symmetrically about a third straight line, and the second matching capacitor and the fourth matching capacitor are arranged symmetrically about the third straight line.

[0047] Wherein, the second matching capacitor and the fourth matching capacitor are located on opposite sides of the first matching capacitor and the third matching capacitor; or, the second matching capacitor is located between the first matching capacitor and the second power amplifier circuit, and the fourth matching capacitor is located between the third matching capacitor and the second power amplifier circuit.

[0048] Optionally, the power amplifier is integrated within a chip, wherein the second power amplifier circuit is disposed near a first edge of the chip, the first power amplifier circuit includes a first transistor and a second transistor, the second power amplifier circuit includes a third transistor and a fourth transistor, the first transistor and the second transistor are symmetrically disposed about a third line perpendicular to the first edge, the third transistor and the fourth transistor are symmetrically disposed about the third line, the first matching capacitor and the third matching capacitor are symmetrically disposed about the third line, and the second matching capacitor and the fourth matching capacitor are symmetrically disposed about the third line.

[0049] The power amplifier provided in this application includes at least two power amplifier circuits, wherein the two power amplifier circuits include a first power amplifier circuit and a second power amplifier circuit; and an interstage matching circuit connected between the first power amplifier circuit and the second power amplifier circuit. The interstage matching circuit includes a plurality of matching inductors, at least one of which is configured as either a first inductor structure or a second inductor structure. The first inductor structure includes at least one bonding wire, a first end of which is connected to a first pad, and a second end of which is connected to a second pad. At least one of the first pad and the second pad is connected to a connection path between the first power amplifier circuit and the second power amplifier circuit. The second inductor structure includes a plurality of metal traces, at least two of which have their first ends connected to a first node, and at least two of which have their second ends connected to a second node. Both the first node and the second node are disposed on the connection path. In this manner, the first inductor structure includes at least one bonding wire, with a first end connected to a first pad and a second end connected to a second pad. This first inductor structure achieves a relatively small inductance value while maintaining a high Q value (quality factor), thus reducing RF signal loss. The second inductor structure includes multiple parallel metal traces, enabling it to achieve a relatively small inductance value while also maintaining a high Q value, further reducing RF signal loss.

[0050] This application provides a power amplifier, including:

[0051] At least two stages of power amplifier circuitry, wherein the two stages of power amplifier circuitry include a first power amplifier circuit and a second power amplifier circuit; and

[0052] An interstage matching circuit is connected between the first power amplifier circuit and the second power amplifier circuit, and the interstage matching circuit includes at least two matching inductors with different structures.

[0053] Optionally, the two matching inductors in the interstage matching circuit are configured as two of a first inductor structure, a second inductor structure, and a third inductor structure;

[0054] The first inductor structure includes at least one bonding wire, the first end of which is disposed on the first pad, and the second end of which is disposed on the second pad. At least one of the first pad and the second pad is connected to the connection path between the first power amplifier circuit and the second power amplifier circuit.

[0055] The second inductor structure includes multiple metal traces, at least two of the multiple metal traces have their first ends connected to a first node, and at least two of the multiple metal traces have their second ends connected to a second node, with both the first node and the second node disposed on the connection path;

[0056] The third inductor structure is constructed as a spiral coil structure, and at least one end of the third inductor structure is connected to the connection path.

[0057] The power amplifier provided in this application includes at least two power amplifier stages and an interstage matching circuit. The two power amplifier stages are a first power amplifier stage and a second power amplifier stage. The interstage matching circuit is connected between the first and second power amplifier stages and includes at least two matching inductors with different structures. Through this method, the structure of the matching inductors can be set according to their inductance values, thereby enabling matching inductors with smaller inductance values ​​to have higher Q values ​​and reducing RF signal loss.

[0058] This application provides a radio frequency front-end module, including the power amplifier provided in any of the above embodiments.

[0059] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0060] Figure 1 A structural block diagram of a power amplifier provided in an embodiment of this application is shown.

[0061] Figure 2 A schematic diagram of the first inductor structure in the power amplifier provided in an embodiment of this application is shown.

[0062] Figure 3 A schematic diagram of the second inductor structure in the power amplifier provided in an embodiment of this application is shown.

[0063] Figure 4 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0064] Figure 5 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0065] Figure 6 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0066] Figure 7 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0067] Figure 8 A schematic diagram of the third inductor structure in the power amplifier provided in this application embodiment is shown.

[0068] Figure 9 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0069] Figure 10 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0070] Figure 11 A circuit diagram of a power amplifier provided in an embodiment of this application is shown.

[0071] Figure 12 A circuit diagram of a power amplifier provided in an embodiment of this application is shown.

[0072] Figure 13 A circuit diagram of a power amplifier provided in an embodiment of this application is shown.

[0073] Figure 14 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0074] Figure 15 A structural block diagram of a power amplifier provided in an embodiment of this application is shown.

[0075] Figure 16 A structural block diagram of the radio frequency front-end module provided in an embodiment of this application is shown.

[0076] Figure 17 A structural block diagram of the radio frequency front-end module provided in an embodiment of this application is shown. Detailed Implementation

[0077] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0078] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0079] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0080] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0081] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0082] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0083] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0084] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0085] One embodiment of this application provides a power amplifier 100, including a power amplification circuit and an interstage matching circuit 120. The power amplification circuit has at least two stages, including a first power amplification circuit 110a and a second power amplification circuit 110b. Please refer to... Figure 1 As shown, the interstage matching circuit 120 is connected between the first power amplifier circuit 110a and the second power amplifier circuit 110b. The interstage matching circuit 120 includes a plurality of matching inductors, at least one of which is configured to... Figure 2 The first inductor structure 130 shown is or Figure 3 The second inductor structure 140 is shown.

[0086] like Figure 2 As shown in (2a) to (2c), the first inductor structure 130 includes at least one bonding wire 131, with a first end connected to a first pad 151 and a second end connected to a second pad 152. At least one of the first pad 151 and the second pad 152 is connected to the connection path between the first power amplifier circuit 110a and the second power amplifier circuit 110b. Exemplarily, when both the first power amplifier circuit 110a and the second power amplifier circuit 110b are single-ended power amplifier circuits, one of the first pad 151 and the second pad 152 is disposed on the connection path between the first power amplifier circuit 110a and the second power amplifier circuit 110b, while the other of the first pad 151 and the second pad 152 is grounded or disposed at another node of the circuit according to the design of the matching circuit. When both the first power amplifier circuit 110a and the second power amplifier circuit 110b are differential power amplifier circuits, the first pad 151 and the second pad 152 are both disposed on the connection path between the first power amplifier circuit 110a and the second power amplifier circuit 110b. For example, the first pad 151 is disposed on the connection path between the first output terminal of the first power amplifier circuit 110a and the first input terminal of the second power amplifier circuit 110b, and the second pad 152 is disposed on the connection path between the second output terminal of the first power amplifier circuit 110a and the second input terminal of the second power amplifier circuit 110b.

[0087] like Figure 3As shown in (3a) to (3e), the second inductor structure 140 includes a plurality of metal traces 141. The first ends of at least two of the metal traces 141 are connected to a first node 142, and the second ends of at least two of the metal traces 141 are connected to a second node 143. At least one of the first node 142 and the second node 143 is connected to a connection path. For example, when both the first power amplifier circuit 110a and the second power amplifier circuit 110b are single-ended power amplifier circuits, one of the first node 142 and the second node 143 is connected to the connection path between the first power amplifier circuit 110a and the second power amplifier circuit 110b, while the other of the first node 142 and the second node 143 is grounded or located at another node in the circuit according to the design of the matching circuit. When both the first power amplifier circuit 110a and the second power amplifier circuit 110b are differential power amplifier circuits, the first node 142 and the second node 143 are both connected to the connection path between the first power amplifier circuit 110a and the second power amplifier circuit 110b. For example, the first node 142 is connected to the connection path between the first output terminal of the first power amplifier circuit 110a and the first input terminal of the second power amplifier circuit 110b, and the second node 143 is connected to the connection path between the second output terminal of the first power amplifier circuit 110a and the second input terminal of the second power amplifier circuit 110b.

[0088] In this embodiment, the first inductor structure 130 includes at least one bonding wire 131. A first end of the bonding wire 131 is connected to a first pad 151, and a second end of the bonding wire 131 is connected to a second pad 152. The first inductor structure 130 achieves a relatively small inductance value while also having a high Q value (quality factor), thus reducing RF signal loss. The second inductor structure 140 includes multiple parallel metal traces 141, which allows the second inductor structure 140 to achieve a relatively small inductance value while also reducing line loss resistance, thereby also achieving a high Q value and reducing RF signal loss.

[0089] In some implementations, at least one matching inductor is configured as a first inductor structure 130. The first inductor structure 130 achieves a small inductance value while having a high Q value, and the first inductor structure 130 can also reduce insertion loss, thereby maximizing the performance of high-frequency application scenarios.

[0090] As one implementation method, please refer to Figure 4The first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as differential amplifier circuits to improve output power. Specifically, the first output terminal of the first power amplifier circuit 110a is connected to the first input terminal of the second power amplifier circuit 110b, and the second output terminal of the first power amplifier circuit 110a is connected to the second input terminal of the second power amplifier circuit 110b. A first pad 151 is disposed on the connection path between the first output terminal of the first power amplifier circuit 110a and the first input terminal of the second power amplifier circuit 110b. A second pad 152 is disposed on the connection path between the second output terminal of the first power amplifier circuit 110a and the second input terminal of the second power amplifier circuit 110b. The first end of the bonding wire 131 is connected to the first pad 151, and the second end of the bonding wire 131 is connected to the second pad 152. Since the bonding wire 131 is equivalent to a small-diameter metal wire, it can exhibit inductive characteristics for radio frequency signals. Therefore, in this embodiment, the inductance equivalent to the bonding wire 131 is used as the matching inductor, which not only achieves a small inductance value but also has a high Q value, and reduces the area occupied by the power amplifier 100.

[0091] In one implementation, the first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as single-ended amplifier circuits, which helps to simplify the circuit structure and reduce the area occupied by the power amplifier 100. Please refer to... Figure 5 The power amplifier 100 is disposed within the chip 200, which is disposed on the substrate 300. Specifically, the output terminal of the first power amplifier circuit 110a is connected to the input terminal of the second power amplifier circuit 110b. A first pad 151 is disposed on the connection path between the output terminal of the first power amplifier circuit 110a and the input terminal of the second power amplifier circuit 110b, and a second pad 152 is disposed on the substrate 300 and grounded. The first end of the bonding wire 131 is connected to the first pad 151, and the second end of the bonding wire 131 is connected to the second pad 152. Since the bonding wire 131 is equivalent to a small-diameter metal wire, it can exhibit inductive characteristics for radio frequency signals. Therefore, in this embodiment, the inductance equivalent to the bonding wire 131 is used as a matching inductor, which not only achieves a small inductance value while having a high Q value, but also reduces the area occupied by the power amplifier 100.

[0092] When using the first inductor structure, please refer to some implementation methods. Figure 2 As shown in (2b) to (2c), the first inductor structure 130 includes a plurality of parallel bonding wires 131, the first end of each bonding wire 131 being connected to a corresponding first pad 151, and the second end of each bonding wire 131 being connected to a corresponding second pad 152.

[0093] When the required inductance is small, but the distance between the first pad 151 and the second pad 152 is large (i.e., the length of the bonding wire 131 is long), if the first inductor structure 130 includes only one bonding wire 131, the equivalent inductance value of the first inductor structure 130 may exceed the required inductance. To ensure that the first inductor structure 130 still has a small inductance value even when the distance between the first pad 151 and the second pad 152 is large, in this embodiment, the first inductor structure 130 is configured as a structure with multiple bonding wires 131 connected in parallel. This further reduces the inductance value of the first inductor structure 130 while ensuring that the first inductor structure 130 still has a high Q value.

[0094] As one implementation method, please refer to Figure 2 As shown in (2b), when the first inductor structure 130 includes a plurality of parallel bonding wires 131, the first pad 151 and the second pad 152 can be set to a smaller size. The number of the first pad 151 and the number of the second pad 152 can be equal to the number of bonding wires 131 in the first inductor structure 130. The first pad 151 is connected to the first end of the bonding wire 131 in a one-to-one correspondence, and the second pad 152 is connected to the second end of the bonding wire 131 in a one-to-one correspondence.

[0095] As one implementation method, please refer to Figure 2 As shown in (2c), when the first inductor structure 130 includes a plurality of parallel bonding wires 131, the first pad 151 and the second pad 152 can be long strip-shaped large pads, the first end of all bonding wires 131 is connected to the same first pad 151, and the second end of all bonding wires 131 is connected to the same second pad 152.

[0096] In some embodiments, the inductance value of the first inductor structure 130 is 0.1-0.4nH. Exemplarily, the inductance value of the first inductor structure 130 can be, but is not limited to, 0.1nH, 0.15nH, 0.2nH, 0.25nH, 0.3nH, 0.35nH, or 0.4nH. In this embodiment, the length and height of the bonding wire 131 can be set within commonly used ranges, without excessively extending the length and height of the bonding wire, thus avoiding the bonding wire 131 being too long or too high and affecting the layout and packaging of the RF front-end module.

[0097] In some embodiments, the inductance value of the second inductor structure 140 is 0.1-1nH. Exemplarily, the inductance value of the second inductor structure 140 can be, but is not limited to, 0.1nH, 0.25nH, 0.4nH, 0.6nH, 0.75nH, 0.9nH, or 1nH. In this embodiment, the second inductor structure 140 has a wider applicability than the first inductor structure 130. When the inductance of the matching inductor exceeds 0.4nH but does not exceed 1nH, the matching inductor can be set as the second inductor structure 140 to obtain a higher Q value than the conventional inductor structure with the same inductance.

[0098] In some embodiments, when the operating frequency band of the power amplifier 100 is higher than a first preset frequency band, the interstage matching circuit 120 includes a first inductor structure 130 and a second inductor structure 140; or, the interstage matching circuit 120 includes either the first inductor structure 130 or the second inductor structure 140. When the operating frequency band of the power amplifier 100 is lower than a second preset frequency band, the interstage matching circuit 120 includes at least the second inductor structure 140. The second preset frequency band is lower than or equal to the first preset frequency band.

[0099] During the operation of the matching circuit, the higher the operating frequency, the smaller the required inductance; the lower the operating frequency, the larger the required inductance. In this embodiment, if the required inductance is small, the matching inductor can be configured as either the first inductor structure 130 or the second inductor structure 140. However, if the required inductance is large, using the first inductor structure would require extending the length or height of the bonding wire. In this case, configuring the matching inductor as the second inductor structure 140 can prevent the bonding wire 131 from being too high and affecting the packaging of the RF front-end module.

[0100] As one implementation method, please refer to Figure 6 The first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as differential amplifier circuits to improve output power. Specifically, the first output terminal of the first power amplifier circuit 110a is connected to the first input terminal of the second power amplifier circuit 110b, and the second output terminal of the first power amplifier circuit 110a is connected to the second input terminal of the second power amplifier circuit 110b. When a second inductor structure is used, the first node 142 is disposed on the connection path between the first output terminal of the first power amplifier circuit 110a and the first input terminal of the second power amplifier circuit 110b. The second node 143 is disposed on the connection path between the second output terminal of the first power amplifier circuit 110a and the second input terminal of the second power amplifier circuit 110b.

[0101] As one implementation method, please refer to Figure 7The first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as single-ended amplifier circuits, which helps to simplify the circuit structure and reduce the area occupied by the power amplifier 100. Specifically, the power amplifier 100 is disposed within the chip 200, which is disposed on the substrate 300. The output terminal of the first power amplifier circuit 110a is connected to the input terminal of the second power amplifier circuit 110b. When a second inductor structure is used, the first node 142 is connected to the connection path between the output terminal of the first power amplifier circuit 110a and the input terminal of the second power amplifier circuit 110b, and the second node 143 is disposed within the chip 200 and connected to the pads for setting bonding wires or conductive bumps, so as to connect to the substrate and ground through the bonding wires or conductive bumps.

[0102] In some embodiments, the first node 142 and the second node 143 are spaced apart on the first straight line X. At least two metal traces 141 include a first metal trace 141a and a second metal trace 141b. As one embodiment, please refer to... Figure 3 In (3a) to (3e), the first metal trace 141a and the second metal trace 141b can also be located on different sides of the first straight line X, which can reduce the parasitic capacitance between them and improve heat dissipation. It should be noted that in other embodiments, the first metal trace 141a and the second metal trace 141b can be located on the same side of the first straight line X, which can make the structure of the power amplifier 100 more compact.

[0103] In some implementation methods, please refer to Figure 3 In (3a) to (3e), the first metal trace 141a and the second metal trace 141b can be arranged symmetrically about the first straight line X. When applied in a differential power amplifier, this is beneficial to improving the balance of the power amplifier.

[0104] In some implementation methods, please refer to Figure 3 In sections (3a) to (3e), the first node 142 and the second node 143 are spaced apart on the first straight line X. At least two metal traces 141 include a first metal trace 141a and a second metal trace 141b. The first metal trace 141a is symmetrically arranged about a second straight line Y intersecting the first straight line, and the second metal trace 141b is symmetrically arranged about the second straight line Y. For example, the second straight line Y can be perpendicular to the first straight line X, which can further improve the symmetry of the layout and the balance of the power amplifier.

[0105] As one implementation method, please refer to Figure 3As shown in (3a) to (3b), the middle part of the first metal trace 141a and the middle part of the second metal trace 141b do not need to merge, which makes the structure simpler, reduces parasitic capacitance, and improves heat dissipation.

[0106] As one implementation method, please refer to Figure 3 As shown in (3c) to (3e), the middle portions of the first metal trace 141a and the second metal trace 141b can converge at at least one third node 144, making it easier to adjust the inductance value of the second inductor structure 140 as needed. It is understood that when there are at least two third nodes 144, the first and second metal traces can be connected in parallel between two adjacent third nodes 144, or they can be configured as a single metal trace (i.e., the first and second metal traces overlap), thereby making the inductance value of the second inductor structure 140 adjustable.

[0107] For example, please refer to Figure 3 As shown in (3d) to (3e), the middle portions of the first metal trace 141a and the second metal trace 141b can converge at a third node 144. Please refer to... Figure 3 As shown in (3c), the middle portion of the first metal trace 141a and the middle portion of the second metal trace 141b can converge at two third nodes 144. It should be noted that in other embodiments, the middle portion of the first metal trace 141a and the middle portion of the second metal trace 141b can converge at three or more third nodes, which can be set according to the actual situation, and will not be elaborated here.

[0108] In some embodiments, the interstage matching circuit includes multiple matching inductors, wherein some of the matching inductors adopt a first inductor structure or a second inductor structure, while other matching inductors may adopt other inductor structures.

[0109] In one implementation, the inter-stage matching circuit may include a third inductor structure 160 in addition to the first or second inductor structure. That is, at least one matching inductor is configured as the third inductor structure 160, and the inductance value of the third inductor structure 160 is greater than or equal to 0.8nH. Exemplarily, the inductance value of the third inductor structure 160 may be, but is not limited to, 0.8nH, 0.9nH, 1.0nH, 1.1nH, 1.2nH, or 1.3nH. It is understood that the inductance value of the third inductor structure 160 may also be larger as needed, such as 2nH, 3nH, etc. This application does not limit the maximum inductance value of the third inductor structure 160.

[0110] As one implementation method, please refer to Figure 8 The third inductor structure 160 is constructed as a spiral coil structure. At least one end of the third inductor structure 160 is connected to the connection path.

[0111] In this embodiment, the third inductor structure 160 is constructed as a spiral coil structure, which not only allows the third inductor structure 160 to have a larger inductance value, but also reduces the area occupied by the third inductor structure 160, making the structure of the power amplifier 100 more compact.

[0112] For example, please refer to Figure 9 The first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as differential amplifier circuits to improve output power. Specifically, the first output terminal of the first power amplifier circuit 110a is connected to the first input terminal of the second power amplifier circuit 110b, and the second output terminal of the first power amplifier circuit 110a is connected to the second input terminal of the second power amplifier circuit 110b. The first terminal of the third inductor structure 160 is disposed on the connection path between the first output terminal of the first power amplifier circuit 110a and the first input terminal of the second power amplifier circuit 110b. The second terminal of the third inductor structure 160 is disposed on the connection path between the second output terminal of the first power amplifier circuit 110a and the second input terminal of the second power amplifier circuit 110b.

[0113] For example, please refer to Figure 10 The power amplifier 100 is disposed within the chip 200, which is mounted on the substrate 300. The first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as single-ended amplifier circuits, which simplifies the circuit structure and reduces the area occupied by the power amplifier 100. Specifically, the output terminal of the first power amplifier circuit 110a is connected to the input terminal of the second power amplifier circuit 110b. The first end of the third inductor structure 160 is disposed on the connection path between the output terminal of the first power amplifier circuit 110a and the input terminal of the second power amplifier circuit 110b. The second end of the third inductor structure 160 is disposed within the chip 200, and then the second end of the third inductor structure 160 is connected to the substrate and grounded via a bonding wire or a conductive bump.

[0114] In some implementation methods, please refer to Figure 11 Two of the multiple matching inductors include a first matching inductor L1 and a second matching inductor L2, where the inductance value of the first matching inductor L1 is greater than the inductance value of the second matching inductor L2. The first matching inductor L1 is connected in series between the first power amplifier circuit 110a and the second power amplifier circuit 110b, and the second matching inductor L2 is connected in parallel between the first matching inductor L1 and the second power amplifier circuit 110b. Taking a single-ended power amplifier circuit as an example... Figure 11 As shown, one end of the second matching inductor L2 is connected to the path between the first matching inductor L1 and the second power amplifier circuit 110b, and the other end of the second matching inductor L2 is grounded.

[0115] If both the first power amplifier circuit 110a and the second power amplifier circuit 110b are configured as differential amplifier circuits, the interstage matching circuit may include two first matching inductors L1. One first matching inductor L1 is connected in series between the first output terminal of the first power amplifier circuit 110a and the first input terminal of the second power amplifier circuit 110b, and the other first matching inductor L1 is connected in series between the second output terminal of the first power amplifier circuit 110a and the second input terminal of the second power amplifier circuit 110b. One end of the second matching inductor L2 is connected in the path between one first matching inductor L1 and the first input terminal of the second power amplifier circuit 110b, and the other end of the second matching inductor L2 is connected in the path between the other first matching inductor L1 and the second input terminal of the second power amplifier circuit 110b.

[0116] In this embodiment, the interstage matching circuit includes two stages of impedance matching units. The first stage impedance matching unit includes a first matching inductor L1, and the other stage impedance matching unit includes a second matching inductor L2. By setting two stages of impedance matching units, the output impedance of the first power amplifier circuit 110a and the input impedance of the second power amplifier circuit 110b are better matched, thereby reducing the loss of radio frequency signals during interstage transmission.

[0117] As one implementation method, please refer to Figure 11 The first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as single-ended amplifier circuits, which helps to simplify the circuit structure and reduce the area occupied by the power amplifier 100. Specifically, the output terminal of the first power amplifier circuit 110a is connected to the input terminal of the second power amplifier circuit 110b. The first terminal of the first matching inductor L1 is connected to the output terminal of the first power amplifier circuit 110a, and the second terminal of the first matching inductor L1 is connected to the input terminal of the second power amplifier circuit 110b. The first terminal of the second matching inductor L2 is connected in the connection path between the second terminal of the first matching inductor L1 and the input terminal of the second power amplifier circuit 110b. The second terminal of the second matching inductor L2 can be connected to the substrate through a bonding wire or a conductive bump to ground through the substrate.

[0118] For example, the first matching inductor L1 can be configured as the third inductor structure 160, and the second matching inductor L2 can be configured as the first inductor structure 130. The power amplifier 100 in this embodiment can be applied to WireBond technology.

[0119] For example, the first matching inductor L1 can be configured as the third inductor structure 160, and the second matching inductor L2 can be configured as the second inductor structure 140. The power amplifier 100 in this embodiment is applicable not only to WireBond technology but also to FlipShip technology.

[0120] For example, the first matching inductor L1 can be configured as the second inductor structure 140, and the second matching inductor L2 can be configured as the first inductor structure 130. The power amplifier 100 in this embodiment can be applied to the WireBond process.

[0121] For example, the first matching inductor L1 can be configured as the second inductor structure 140, and the second matching inductor L2 can be configured as the second inductor structure 140. The power amplifier 100 in this embodiment is applicable not only to WireBond technology but also to FlipShip technology.

[0122] As one implementation method, please refer to Figure 11 The interstage matching circuit 120 also includes a first matching capacitor C1 and a second matching capacitor C2. The first matching capacitor C1 is connected in parallel between the first power amplifier circuit 110a and the first matching inductor L1, and the second matching capacitor C2 is connected in series between the second matching inductor L2 and the second power amplifier circuit 110b. The first matching capacitor C1 and the first matching inductor L1 form one stage of impedance matching, while the second matching capacitor C2 and the second matching inductor L2 form another stage. By setting two stages of impedance matching, the impedances of the first power amplifier circuit 110a and the second power amplifier circuit 110b are more matched, thereby reducing the loss of radio frequency signals during interstage transmission. Furthermore, each stage of impedance matching includes a matching capacitor and a matching inductor, and the resonance between the matching capacitor and the matching inductor can be used to suppress noise and harmonics, further improving the performance of the power amplifier.

[0123] In some implementation methods, please refer to Figure 12 and Figure 13 Two of the multiple matching inductors include a third matching inductor L3 and a fourth matching inductor L4, where the inductance value of the third matching inductor L3 is greater than that of the fourth matching inductor L4. The third matching inductor L3 is connected in parallel between the first power amplifier circuit 110a and the second power amplifier circuit 110b, and the fourth matching inductor L4 is connected in parallel between the third matching inductor L3 and the second power amplifier circuit 110b.

[0124] like Figure 12As shown, if both the first power amplifier circuit 110a and the second power amplifier circuit 110b are configured as single-ended power amplifier circuits, then one end of the third matching inductor L3 is connected to the path between the first power amplifier circuit 110a and the second power amplifier circuit 110b, and the other end of the third matching inductor L3 is grounded. One end of the fourth matching inductor L4 is connected to the path between the third matching inductor L3 and the second power amplifier circuit 110b, and the other end of the fourth matching inductor L4 is grounded.

[0125] like Figure 13 As shown, if both the first power amplifier circuit 110a and the second power amplifier circuit 110b are configured as differential amplifier circuits, then the first terminal of the third matching inductor L3 is connected to the first output terminal of the first power amplifier circuit 110a, and the second terminal of the third matching inductor L3 is connected to the second output terminal of the first power amplifier circuit 110a. The first terminal of the fourth matching inductor L4 is connected in the path between the first terminal of the third matching inductor L3 and the first input terminal of the second power amplifier circuit 110b, and the second terminal of the fourth matching inductor L4 is connected in the path between the second terminal of the third matching inductor L3 and the second input terminal of the second power amplifier circuit 110b.

[0126] In this embodiment, the interstage matching circuit includes two stages of impedance matching units. The first stage impedance matching unit includes a third matching inductor L3, and the other stage impedance matching unit includes a fourth matching inductor L4. By setting two stages of impedance matching units, the impedances of the first power amplifier circuit 110a and the second power amplifier circuit 110b are better matched, thereby reducing the loss of radio frequency signals during interstage transmission.

[0127] For example, the third matching inductor L3 can be configured as the third inductor structure 160, and the fourth matching inductor L4 can be configured as the first inductor structure 130. The power amplifier 100 in this embodiment can be adapted to the WireBond process.

[0128] For example, the third matching inductor L3 can be configured as the third inductor structure 160, and the fourth matching inductor L4 can be configured as the second inductor structure 140. The power amplifier 100 in this embodiment is applicable not only to WireBond technology but also to FlipShip technology.

[0129] For example, the third matching inductor L3 can be configured as the second inductor structure 140, and the fourth matching inductor L4 can be configured as the first inductor structure 130. The power amplifier 100 in this embodiment can be adapted to the WireBond process.

[0130] For example, the third matching inductor L3 can be configured as the second inductor structure 140, and the fourth matching inductor L4 can be configured as the second inductor structure 140. The power amplifier 100 in this embodiment is applicable not only to WireBond technology but also to FlipShip technology.

[0131] As one implementation method, please refer to Figure 12 The first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as single-ended amplifier circuits, which simplifies the circuit structure and reduces the area occupied by the power amplifier 100. The interstage matching circuit 120 also includes a first matching capacitor C1 and a second matching capacitor C2. The first terminal of the third matching inductor L3 is connected to the output terminal of the first power amplifier circuit 110a, and the second terminal of the third matching inductor L3 is grounded. The first terminal of the fourth matching inductor L4 is connected to the first terminal of the third matching inductor L3 through the first matching capacitor C1, and the first terminal of the fourth matching inductor L4 is also connected to the first input terminal of the second power amplifier circuit 110b through the second matching capacitor C2. The second terminal of the fourth matching inductor L4 is grounded. This embodiment can achieve input and output impedance matching over a wide frequency range, thereby ensuring effective signal transmission between different circuit stages.

[0132] As one implementation method, please refer to Figure 13 The first power amplifier circuit 110a and the second power amplifier circuit 110b can be configured as differential amplifier circuits to improve output power. The inter-stage matching circuit 120 further includes a first matching capacitor C1, a second matching capacitor C2, a third matching capacitor C3, and a fourth matching capacitor C4. The first terminal of the third matching inductor L3 is connected to the first output terminal of the first power amplifier circuit 110a, and the second terminal of the third matching inductor L3 is connected to the second output terminal of the first power amplifier circuit 110a. The first terminal of the fourth matching inductor L4 is connected to the first terminal of the third matching inductor L3 through the first matching capacitor C1. The first terminal of the fourth matching inductor L4 is also connected to the first input terminal of the second power amplifier circuit 110b through the second matching capacitor C2. The second terminal of the fourth matching inductor L4 is connected to the second terminal of the third matching inductor L3 through the third matching capacitor C3, and the second terminal of the fourth matching inductor L4 is also connected to the second input terminal of the second power amplifier circuit 110b through the fourth matching capacitor C4. This embodiment can achieve input and output impedance matching over a wide frequency range, thereby ensuring effective signal transmission between different circuit stages.

[0133] For example, please refer to Figure 14The first matching capacitor C1 and the third matching capacitor C3 are arranged symmetrically about the third straight line Z, and the second matching capacitor C2 and the fourth matching capacitor C4 are also arranged symmetrically about the third straight line Z. The second matching capacitor C2 is located between the first matching capacitor C1 and the second power amplifier circuit 110b, and the fourth matching capacitor C4 can be located between the third matching capacitor C3 and the second power amplifier circuit 110b. Alternatively, the second matching capacitor C2 and the fourth matching capacitor C4 can be located on opposite sides of the first matching capacitor C1 and the third matching capacitor C3.

[0134] As one implementation method, please refer to Figure 14 A power amplifier 100 is integrated within a chip 200, wherein a second power amplifier circuit 110b is disposed near the first edge 210 of the chip 200. The first power amplifier circuit 110a includes a first transistor Q1 and a second transistor Q2, and the second power amplifier circuit 110b includes a third transistor Q3 and a fourth transistor Q4. The first transistor Q1 and the second transistor Q2 are symmetrically arranged about a third line Z, the third transistor Q3 and the fourth transistor Q4 are symmetrically arranged about the third line Z, the first matching capacitor C1 and the third matching capacitor C3 are symmetrically arranged about the third line Z, and the second matching capacitor C2 and the fourth matching capacitor C4 are symmetrically arranged about the third line Z. The third line Z is perpendicular to the first edge 210.

[0135] For example, the first power amplifier circuit 110a may include a plurality of first transistors Q1 and a plurality of second transistors Q2, which are arranged side by side along the same straight line, and the arrangement direction of the plurality of first transistors Q1 and the plurality of second transistors Q2 is perpendicular to the third straight line Z. The first transistors Q1 are connected in parallel with each other, and the second transistors Q2 are connected in parallel with each other. The plurality of first transistors Q1 may be located on the first side of the third straight line Z, and the plurality of second transistors Q2 may be located on the second side of the third straight line Z, that is, the plurality of first transistors Q1 and the plurality of second transistors Q2 are symmetrically arranged about the third straight line Z. Similarly, the second power amplifier circuit 110b may include a plurality of third transistors Q3 and a plurality of fourth transistors Q4, which are arranged side by side along another straight line perpendicular to the third straight line Z, and the plurality of first transistors Q1 and the plurality of second transistors Q2 are symmetrically arranged about the third straight line Z. This improves the balance of the power amplifier 100 and makes the layout of the power amplifier 100 more compact.

[0136] In this embodiment, the first power amplifier circuit 110a is symmetrically arranged about the third straight line Z, and the second power amplifier circuit 110b is symmetrically arranged about the third straight line Z. This can improve the common-mode rejection ratio, reduce output imbalance, and improve the stability of the power amplifier 100.

[0137] In this embodiment, the transistor is a heterojunction bipolar transistor (HBT). For example, the transistor can be a heterojunction bipolar transistor fabricated using GaAs (gallium arsenide) technology.

[0138] In other embodiments, the transistor can also be other types of transistors, such as a bipolar junction transistor (BJT) or a field-effect transistor (FET). Optionally, the FET can be a metal-semiconductor FET based on GaN (gallium nitride) or SiC (silicon carbide), or a metal-oxide-semiconductor FET based on a Si (silicon) substrate.

[0139] One embodiment of this application provides a power amplifier 400, including at least two stages of power amplifier circuitry, wherein the two stages of power amplifier circuitry include a first power amplifier circuit 410a and a second power amplifier circuit 410b. Please refer to... Figure 15 The power amplifier 400 also includes an interstage matching circuit 420, which is connected between the first power amplifier circuit 410a and the second power amplifier circuit 410b. The interstage matching circuit 420 includes at least two matching inductors with different structures.

[0140] In some implementations, the two matching inductors in the interstage matching circuit 420 are configured as follows: Figure 2 The first inductor structure 130 shown is Figure 3 The second inductor structure 140 shown and Figure 8 The third inductor structure 160 shown comprises two of the following: The first inductor structure 130 includes at least one bonding wire 131, with the first end of each bonding wire 131 disposed on a first pad 151 and the second end of each bonding wire 131 disposed on a second pad 152. At least one of the first pad 151 and the second pad 152 is connected to a connection path between the first power amplifier circuit 110a and the second power amplifier circuit 110b. The second inductor structure 140 includes a plurality of metal traces 141, with the first end of at least two of the metal traces 141 connected to a first node 142 and the second end of at least two of the metal traces 141 connected to a second node 143. Both the first node 142 and the second node 143 are disposed on the connection path. The third inductor structure 160 is constructed as a helical coil structure, with at least one end of the third inductor structure 160 connected to the connection path.

[0141] In this embodiment, the structure of the matching inductor can be set according to the inductance value of the matching inductor, so that the matching inductor with a smaller inductance value can also have a higher Q value, thereby reducing the loss of radio frequency signal.

[0142] One embodiment of this application provides a radio frequency front-end module 500, including a power amplifier 100 or a power amplifier 400 as provided in any of the above embodiments. Please refer to... Figure 16 and Figure 17 As shown.

[0143] The above description is merely an embodiment of this application. It should be noted that those skilled in the art can make improvements without departing from the inventive concept of this application, but these improvements all fall within the protection scope of this application.

Claims

1. A power amplifier, characterized in that, include: At least two stages of power amplifier circuitry, wherein the two stages of power amplifier circuitry include a first power amplifier circuit and a second power amplifier circuit; and An interstage matching circuit is connected between the first power amplifier circuit and the second power amplifier circuit. The interstage matching circuit includes a plurality of matching inductors, at least one of the matching inductors being configured as a first inductor structure or a second inductor structure. The first inductor structure includes at least one bonding wire, a first end of which is connected to a first pad, a second end of which is connected to a second pad, and at least one of the first pad and the second pad is connected to the connection path between the first power amplifier circuit and the second power amplifier circuit. The second inductor structure includes a plurality of metal traces, at least two of which have their first ends connected to a first node, and at least two of which have their second ends connected to a second node. At least one of the first node and the second node is connected to the connection path.

2. The power amplifier as described in claim 1, characterized in that, Both the first power amplifier circuit and the second power amplifier circuit are configured as differential amplifier circuits. The first output terminal of the first power amplifier circuit is connected to the first input terminal of the second power amplifier circuit, and the second output terminal of the first power amplifier circuit is connected to the second input terminal of the second power amplifier circuit. The first pad is disposed on the connection path between the first output terminal of the first power amplifier circuit and the first input terminal of the second power amplifier circuit; The second pad is disposed on the connection path between the second output terminal of the first power amplifier circuit and the second input terminal of the second power amplifier circuit.

3. The power amplifier as described in claim 1, characterized in that, The power amplifier is disposed within the chip, and the chip is disposed on the substrate; Both the first power amplifier circuit and the second power amplifier circuit are configured as single-ended amplifier circuits, and the output terminal of the first power amplifier circuit is connected to the input terminal of the second power amplifier circuit. The first pad is disposed on the connection path between the output terminal of the first power amplifier circuit and the input terminal of the second power amplifier circuit, and the second pad is disposed on the substrate and grounded.

4. The power amplifier as described in claim 1, characterized in that, The first inductor includes a plurality of bonding wires connected in parallel, with a first end of each bonding wire connected to a corresponding first pad and a second end of each bonding wire connected to a corresponding second pad.

5. The power amplifier as described in claim 1, characterized in that, When the operating frequency band of the power amplifier is higher than the first preset frequency band, the interstage matching circuit includes the first inductor structure and / or the second inductor structure; When the operating frequency band of the power amplifier is lower than the second preset frequency band, the interstage matching circuit includes at least the second inductor structure; Wherein, the second preset frequency band is lower than or equal to the first preset frequency band.

6. The power amplifier as described in claim 1, characterized in that, The inductance value of the first inductor structure is 0.1-0.4nH.

7. The power amplifier as claimed in claim 1, characterized in that, The inductance value of the second inductor structure is 0.1-1nH.

8. The power amplifier as described in claim 1, characterized in that, The first node and the second node are spaced apart on the first straight line; The at least two metal traces include a first metal trace and a second metal trace, wherein the first metal trace and the second metal trace are located on the same side or different sides of the first straight line.

9. The power amplifier as described in claim 8, characterized in that, The first metal trace and the second metal trace are arranged symmetrically about the first straight line.

10. The power amplifier as claimed in claim 8, characterized in that, The first metal trace is symmetrical about the second straight line, and the second metal trace is symmetrical about the second straight line, wherein the second straight line intersects the first straight line.

11. The power amplifier as claimed in claim 8, characterized in that, The middle portions of the first metal trace and the middle portions of the second metal trace converge at at least one third node; Alternatively, the middle sections of the first metal trace and the second metal trace do not merge.

12. The power amplifier as claimed in claim 1, characterized in that, At least one of the matching inductors is configured as a third inductor structure, the inductance of which is greater than or equal to 0.8nH.

13. The power amplifier as claimed in claim 12, characterized in that, The third inductor structure is constructed as a spiral coil structure, and at least one end of the third inductor structure is connected to the connection path.

14. The power amplifier as claimed in claim 12, characterized in that, Two of the plurality of matching inductors include a first matching inductor and a second matching inductor, wherein the inductance value of the first matching inductor is greater than the inductance value of the second matching inductor; The first matching inductor is connected in series between the first power amplifier circuit and the second power amplifier circuit, and the second matching inductor is connected in parallel between the first matching inductor and the second power amplifier circuit.

15. The power amplifier as claimed in claim 14, characterized in that, The first matching inductor is configured as the third inductor structure, and the second matching inductor is configured as either the first inductor structure or the second inductor structure.

16. The power amplifier as claimed in claim 14, characterized in that, The first matching inductor is configured as the second inductor structure, and the second matching inductor is configured as either the first inductor structure or the second inductor structure.

17. The power amplifier according to any one of claims 14 to 16, characterized in that, The interstage matching circuit further includes a first matching capacitor and a second matching capacitor. The first matching capacitor is connected in parallel between the first power amplifier circuit and the first matching inductor, and the second matching capacitor is connected in series between the second matching inductor and the second power amplifier circuit.

18. The power amplifier as claimed in claim 12, characterized in that, Two of the plurality of matching inductors include a third matching inductor and a fourth matching inductor, wherein the inductance value of the third matching inductor is greater than the inductance value of the fourth matching inductor; The third matching inductor is connected in parallel between the first power amplifier circuit and the second power amplifier circuit, and the fourth matching inductor is connected in parallel between the third matching inductor and the second power amplifier circuit.

19. The power amplifier as claimed in claim 18, characterized in that, The third matching inductor is configured as the third inductor structure, and the fourth matching inductor is configured as the first inductor structure or the second inductor structure.

20. The power amplifier as claimed in claim 18, characterized in that, The third matching inductor is configured as the second inductor structure, and the fourth matching inductor is configured as either the first inductor structure or the second inductor structure.

21. The power amplifier as claimed in claim 18, characterized in that, Both the first power amplifier circuit and the second power amplifier circuit are configured as single-ended amplifier circuits, and the interstage matching circuit further includes a first matching capacitor and a second matching capacitor. Wherein, the first end of the third matching inductor is connected to the output end of the first power amplifier circuit, and the second end of the third matching inductor is grounded; The first end of the fourth matching inductor is connected to the first end of the third matching inductor through the first matching capacitor and to the first input terminal of the second power amplifier circuit through the second matching capacitor. The second end of the fourth matching inductor is grounded.

22. The power amplifier as claimed in claim 18, characterized in that, Both the first power amplifier circuit and the second power amplifier circuit are configured as differential amplifier circuits, and the interstage matching circuit further includes a first matching capacitor, a second matching capacitor, a third matching capacitor and a fourth matching capacitor; Wherein, the first end of the third matching inductor is connected to the first output terminal of the first power amplifier circuit, and the second end of the third matching inductor is connected to the second output terminal of the first power amplifier circuit; The first end of the fourth matching inductor is connected to the first end of the third matching inductor through the first matching capacitor and to the first input terminal of the second power amplifier circuit through the second matching capacitor. The second end of the fourth matching inductor is connected to the second end of the third matching inductor through the third matching capacitor and to the second input terminal of the second power amplifier circuit through the fourth matching capacitor.

23. The power amplifier as claimed in claim 22, characterized in that, The first matching capacitor and the third matching capacitor are arranged symmetrically about a third straight line, and the second matching capacitor and the fourth matching capacitor are arranged symmetrically about a third straight line. Wherein, the second matching capacitor and the fourth matching capacitor are located on opposite sides of the first matching capacitor and the third matching capacitor; or, the second matching capacitor is located between the first matching capacitor and the second power amplifier circuit, and the fourth matching capacitor is located between the third matching capacitor and the second power amplifier circuit.

24. The power amplifier as claimed in claim 22, characterized in that, The power amplifier is integrated within a chip, wherein the second power amplifier circuit is disposed near a first edge of the chip. The first power amplifier circuit includes a first transistor and a second transistor, and the second power amplifier circuit includes a third transistor and a fourth transistor. The first transistor and the second transistor are symmetrically disposed about a third line perpendicular to the first edge. The third transistor and the fourth transistor are symmetrically disposed about the third line. The first matching capacitor and the third matching capacitor are symmetrically disposed about the third line. The second matching capacitor and the fourth matching capacitor are symmetrically disposed about the third line.

25. A power amplifier, characterized in that, include: At least two stages of power amplifier circuitry, wherein the two stages of power amplifier circuitry include a first power amplifier circuit and a second power amplifier circuit; and An interstage matching circuit is connected between the first power amplifier circuit and the second power amplifier circuit, and the interstage matching circuit includes at least two matching inductors with different structures.

26. The power amplifier as claimed in claim 25, characterized in that, The two matching inductors in the interstage matching circuit are configured as two of a first inductor structure, a second inductor structure, and a third inductor structure. The first inductor structure includes at least one bonding wire, the first end of which is disposed on a first pad, and the second end of which is disposed on a second pad. At least one of the first pad and the second pad is connected to the connection path between the first power amplifier circuit and the second power amplifier circuit. The second inductor structure includes multiple metal traces, at least two of the multiple metal traces have their first ends connected to a first node, and at least two of the multiple metal traces have their second ends connected to a second node, with both the first node and the second node disposed on the connection path; The third inductor structure is constructed as a spiral coil structure, and at least one end of the third inductor structure is connected to the connection path.

27. A radio frequency front-end module, characterized in that, This includes the power amplifier as described in any one of claims 1 to 24 or the power amplifier as described in any one of claims 25 to 26.

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