Ultrahigh-speed sampling frequency measurement processing board for single-bit receiver

Abstract

The utility model relates to the technical field of signal receiving and processing of electronic warfare detection equipment, in particular to an ultra-high-speed sampling frequency measurement processing board for a single-bit receiver, which comprises a frequency measurement processing board body, and a high-speed ADC (analog-to-digital converter) module, an FPGA (field programmable gate array) module, a low-speed ADC module, a power module and an interface module are integrated on the frequency measurement processing board body. The high-speed ADC module is directly connected with the FPGA module, the FPGA module receives digital signals output by the high-speed ADC module, the low-speed ADC module is used for converting linear video amplitude output by the SDLVA into digital signals and outputting the digital signals to the FPGA module, and the processing board integrates the high-speed ADC module, the FPGA module, the low-speed ADC module, a power supply module and an interface module. The processing board can directly sample and quantify 2-18GHz radio frequency signals, realizes pipelined instantaneous frequency measurement through the FPGA, and accurately outputs frequency and amplitude information of the signals.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic warfare reconnaissance equipment's signal receiving processing technical field, especially a kind of super high-speed sampling frequency measurement processing board. BACKGROUND

[0002] Frequency board is mainly used for the single-bit receiver of electronic reconnaissance equipment, and its main function is to directly sample quantization to 2-18GHz radio frequency signal, and to complete the flow instantaneous frequency measurement by the FPGA on the board, to give the frequency and amplitude information of signal, and to complete the function of single-bit receiver fast frequency measurement output together with single-bit front end. The real-time requirement of modern application scene to fast frequency measurement is higher and higher, and the requirement of equipment component localization rate is also higher and higher. Traditional single-bit receiving frequency measurement board needs constant updating and upgrading. UTILITY MODEL CONTENT

[0003] To solve the problems existing in the prior art, the utility model provides a super high-speed sampling frequency measurement processing board for single-bit receiver to solve the deficiencies in the prior art.

[0004] To achieve the above purpose, the utility model provides a super high-speed sampling frequency measurement processing board for single-bit receiver, including frequency measurement processing board body, high-speed ADC module, FPGA module, low-speed ADC module, power module and interface module are integrally arranged on the frequency measurement processing board body, the high-speed ADC module is directly connected with FPGA module, the FPGA module receives digital signal output by high-speed ADC module, the low-speed ADC module is used for converting linear video amplitude output by SDLVA into digital signal, and outputting to the FPGA module.

[0005] As a further improvement of the utility model, in order to improve the real-time performance and accuracy of signal processing, improve the efficiency and reliability of data transmission, the high-speed ADC module can convert wideband input analog signal into digital signal and output through high-speed serial interface;Wherein the input signal of the high-speed ADC module adopts single-ended input form to increase the integration, and the output of the high-speed ADC module adopts serial interface, and supports multiple serial data outputs at full rate.

[0006] As a further improvement of the utility model, in order to improve the flexibility and scalability of equipment, provide rich special clock and wiring resources, suitable for realizing complex high-speed digital logic circuit, the FPGA module integrates several groups of programmable resources, for realizing input and output interface, general digital logic, memory, digital signal processing and clock management function;Meanwhile, the FPGA module provides rich special clock and wiring resources, suitable for realizing complex high-speed digital logic circuit, and the FPGA module is connected with high-speed ADC module.

[0007] As a further improvement of this utility model, in order to improve the efficiency and real-time performance of data processing and accurately output the frequency and amplitude information of the signal to meet the frequency measurement accuracy requirements of electronic warfare reconnaissance equipment, the FPGA module works in conjunction with the high-speed ADC module and transmits data through a high-speed interface. The FPGA module receives the digital signal output by the high-speed ADC module, performs further processing and analysis on the received digital signal, and outputs the frequency and amplitude information of the signal.

[0008] As a further improvement of this utility model, in order to accurately convert the large dynamic range linear video amplitude output by SDLVA into a digital signal, realize the accurate extraction of signal amplitude information, and improve the measurement accuracy of signal amplitude by the device, the low-speed ADC module is a high-resolution, single-channel analog-to-digital converter circuit. This low-speed ADC module has high input bandwidth, fast sampling rate and good signal linearity. It is used to accurately convert the large dynamic range linear video amplitude output by SDLVA into a digital signal and output it to the FPGA module for subsequent processing to realize the extraction of signal amplitude information.

[0009] As a further improvement of this utility model, in order to support the simultaneous output of multiple pairs of differential signals and meet the requirements of high-speed, parallel transmission of frequency codes and amplitude codes, the interface module is equipped with a differential LVDS level interface for transmitting frequency codes and amplitude codes; the interface module is also designed with differential signal pairs, and the interface module supports the simultaneous output of multiple pairs of differential signals.

[0010] As a further improvement of this utility model, in order to ensure the normal operation of the equipment, prevent system shutdown due to power supply thermal failure, and improve the reliability and stability of the equipment, the power module adopts a power chip design, and the power module provides a stable power supply signal to each functional module; at the same time, the power module is designed with reserved margin.

[0011] In operation, the wideband input analog signal is first fed into the high-speed ADC module. The high-speed ADC module is a high-speed chip manufactured using CMOS technology, responsible for converting the received wideband input analog signal into a digital signal. This module uses a single-ended input to increase integration and outputs the converted digital signal through a high-speed serial interface.

[0012] Next, the FPGA module receives the digital signal output from the high-speed ADC module. The FPGA module integrates several sets of programmable resources, which can be used to implement input / output interfaces, general-purpose digital logic, memory, digital signal processing, and clock management functions. Simultaneously, the FPGA module provides abundant dedicated clock and routing resources, suitable for implementing complex, high-speed digital logic circuits. After receiving the digital signal from the high-speed ADC module, the FPGA module further processes and analyzes the signal, including pipelined instantaneous frequency measurement, to provide the signal's frequency information.

[0013] Meanwhile, the low-speed ADC module is also operating. It is responsible for converting the large dynamic range linear video amplitude output from the SDLVA into a digital signal. The low-speed ADC module is a high-resolution, single-channel analog-to-digital converter circuit with high input bandwidth, fast sampling rate, and good signal linearity. The converted digital signal is output to the FPGA module, where it undergoes further processing to extract the signal's amplitude information.

[0014] After processing the frequency and amplitude information, the FPGA module outputs this information through the interface module. The interface module is equipped with a differential LVDS level interface for transmitting frequency and amplitude codes. Simultaneously, the interface module also supports the simultaneous output of multiple pairs of differential signals to meet different application requirements.

[0015] Throughout the entire operation, the power module provides a stable power supply signal to all functional modules. This power module employs a power chip design and incorporates safety margins to prevent system shutdown due to power supply thermal failure.

[0016] The beneficial effects of this utility model are as follows:

[0017] Ultra-high-speed sampling and precise frequency measurement:

[0018] This processing board integrates a high-speed ADC module, capable of achieving an ultra-high-speed sampling rate of 40 Gsps, directly sampling and quantizing radio frequency signals in the 2–18 GHz range. This high sampling rate ensures signal integrity and accuracy, providing a solid foundation for subsequent instantaneous frequency measurement.

[0019] The FPGA module receives the digital signal output from the high-speed ADC module and performs pipelined instantaneous frequency measurement, which can quickly provide the frequency information of the signal. The frequency measurement time is less than or equal to 500ns, which meets the high real-time requirements of modern electronic warfare reconnaissance equipment for rapid frequency measurement.

[0020] High-resolution amplitude measurement:

[0021] The low-speed ADC module features high resolution, high input bandwidth, and a fast sampling rate, enabling it to accurately convert the large dynamic range linear video amplitude output from the SDLVA into a digital signal, which is then output to the FPGA module for further processing. This ensures accurate extraction of amplitude information and improves measurement precision.

[0022] High performance and stability:

[0023] The FPGA module integrates abundant programmable resources and dedicated clock and routing resources, making it suitable for implementing complex, high-speed digital logic circuits. This ensures the stable operation of the processing board under high-performance requirements, while providing flexible configuration and expansion capabilities.

[0024] The power module employs a high-efficiency power chip design, providing stable power signals to each functional module, while also incorporating margins to prevent power supply thermal failure. This further enhances the reliability and stability of the processing board.

[0025] Flexible interface design:

[0026] The interface module features a differential LVDS level interface for transmitting frequency and amplitude codes, and supports simultaneous output of multiple pairs of differential signals. This meets the data transmission requirements of different application scenarios and improves the flexibility and applicability of the processing board. Attached Figure Description

[0027] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings:

[0028] Figure 1 This is a structural diagram of the present invention.

[0029] Figure 2 This is a pin definition diagram of the interface module in this utility model.

[0030] The module consists of 1 high-speed ADC module, 2 FPGA module, 3 low-speed ADC module, 4 power supply module, and 5 interface module. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions in this application, the following description is provided in conjunction with the appendix. Figures 1-2 The present invention will be further described below. The following embodiments are only used to illustrate the technical solution of the present invention more clearly, and should not be used to limit the protection scope of the present invention.

[0032] like Figures 1-2The diagram shows an ultra-high-speed sampling and frequency measurement processing board for a single-bit receiver, comprising a frequency measurement processing board body. The frequency measurement processing board body integrates a high-speed ADC module 1, an FPGA module 2, a low-speed ADC module 3, a power supply module 4, and an interface module 5. The high-speed ADC module 1 is directly connected to the FPGA module 2. The FPGA module 2 receives the digital signal output by the high-speed ADC module 1. The low-speed ADC module 3 is used to convert the linear video amplitude output by the SDLVA into a digital signal and output it to the FPGA module 2.

[0033] The high-speed ADC module 1 can convert wideband input analog signals into digital signals and output them through a high-speed serial interface; wherein the input signal of the high-speed ADC module 1 adopts a single-ended input form to increase the integration, and the output of the high-speed ADC module 1 adopts a serial interface, supporting multiple serial data outputs at full rate.

[0034] The FPGA module 2 integrates several sets of programmable resources to implement input / output interfaces, general digital logic, memory, digital signal processing, and clock management functions. At the same time, the FPGA module 2 provides abundant dedicated clock and wiring resources, which are suitable for implementing complex high-speed digital logic circuits. The FPGA module 2 is connected to the high-speed ADC module 1.

[0035] The FPGA module 2 works in conjunction with the high-speed ADC module 1 and transmits data through a high-speed interface. The FPGA module 2 receives the digital signal output by the high-speed ADC module 1, performs further processing and analysis on the received digital signal, and outputs the frequency and amplitude information of the signal.

[0036] The low-speed ADC module 3 is a high-resolution, single-channel analog-to-digital converter circuit. It features high input bandwidth, fast sampling rate, and good signal linearity. It is used to accurately convert the large dynamic range linear video amplitude output by SDLVA into a digital signal and output it to the FPGA module 2 for further processing to extract the amplitude information of the signal.

[0037] The interface module 5 is equipped with a differential LVDS level interface for transmitting frequency code and amplitude code; the interface module 5 is also designed with differential signal pairs, and the interface module 5 supports the simultaneous output of multiple pairs of differential signals.

[0038] The power module 4 adopts a power chip design and provides a stable power supply signal to each functional module; at the same time, the power module 4 is designed with a reserved margin.

[0039] In operation, the broadband input analog signal is first fed into the high-speed ADC module 1. The high-speed ADC module 1 is a high-speed chip manufactured using CMOS technology, responsible for converting the received broadband input analog signal into a digital signal. This module uses a single-ended input to increase integration and outputs the converted digital signal through a high-speed serial interface.

[0040] Next, FPGA module 2 receives the digital signal output from high-speed ADC module 1. FPGA module 2 integrates several sets of programmable resources, which can be used to implement input / output interfaces, general-purpose digital logic, memory, digital signal processing, and clock management functions. Simultaneously, FPGA module 2 provides abundant dedicated clock and routing resources, suitable for implementing complex high-speed digital logic circuits. After receiving the digital signal from high-speed ADC module 1, FPGA module 2 further processes and analyzes the signal, including pipelined instantaneous frequency measurement, to provide the signal's frequency information.

[0041] Meanwhile, the low-speed ADC module 3 is also operating. It is responsible for converting the large dynamic range linear video amplitude output from the SDLVA into a digital signal. The low-speed ADC module 3 is a high-resolution, single-channel analog-to-digital converter circuit with high input bandwidth, fast sampling rate, and good signal linearity. The converted digital signal is output to the FPGA module 2, where it undergoes further processing to extract the signal's amplitude information.

[0042] After processing the frequency and amplitude information, FPGA module 2 outputs this information through interface module 5. Interface module 5 is equipped with a differential LVDS level interface for transmitting frequency and amplitude codes. Furthermore, interface module 5 supports the simultaneous output of multiple pairs of differential signals to meet different application requirements.

[0043] Throughout the entire operation, power module 4 provides a stable power supply signal to all functional modules. Power module 4 employs a power chip design and includes a safety margin to prevent system shutdown due to power supply thermal failure.

[0044] The following detailed description is provided with reference to the embodiments: Example

[0045] This embodiment provides an ultra-high-speed sampling and frequency measurement processing board for a single-bit receiver, the structure of which is as follows: Figure 1 As shown. The frequency measurement and processing board includes a high-speed ADC module 1, an FPGA module 2, a low-speed ADC module 3, a power supply module 4, and an interface module 5.

[0046] High-speed ADC module 1 uses the AAD01S040G chip, which converts wideband input analog signals into digital signals and outputs them through a high-speed serial interface. FPGA module 2 uses the JFM7VX690T20 chip, which integrates abundant programmable resources for implementing various digital signal processing functions. Low-speed ADC module 3 uses the CS9230-250N chip to convert the linear video amplitude output from the SDLVA into a digital signal.

[0047] Interface module 5 is equipped with a differential LVDS level interface for transmitting frequency and amplitude codes. It also features multiple differential signal pairs to support simultaneous output of multiple differential signals. Power module 4 employs a high-efficiency DC / DC chip design to provide stable power signals to all functional modules and reserves sufficient margin to prevent system crashes.

[0048] In practical applications, the radio frequency signal is sampled and quantized by the high-speed ADC module 1, and then the sampled digital signal is transmitted to the FPGA module 2 for further processing and analysis. The FPGA module 2 performs instantaneous frequency and amplitude measurement on the received digital signal according to a preset algorithm, and then outputs the signal's frequency and amplitude information. Simultaneously, the low-speed ADC module 3 converts the linear video amplitude output from the SDLVA into a digital signal and outputs it to the FPGA module 2 for subsequent processing. Finally, the processed frequency and amplitude information is output to external devices or systems through the interface module 5.

[0049] This utility model is not limited to the above embodiments. Based on the technical solutions disclosed in this utility model, those skilled in the art can make some substitutions and modifications to some of the technical features without creative labor, and these substitutions and modifications are all within the protection scope of this utility model.

Claims

1. A high-speed sampling frequency measurement processing board for a single-bit receiver, comprising a frequency measurement processing board body, characterized in that, The frequency measurement processing board is equipped with a high-speed ADC module (1), an FPGA module (2), a low-speed ADC module (3), a power supply module (4), and an interface module (5). The high-speed ADC module (1) is directly connected to the FPGA module (2). The FPGA module (2) receives the digital signal output by the high-speed ADC module (1). The low-speed ADC module (3) is used to convert the linear video amplitude output by the SDLVA into a digital signal and output it to the FPGA module (2).

2. The ultra-high-speed sampling and frequency measurement processing board for a single-bit receiver according to claim 1, characterized in that, The high-speed ADC module (1) can convert wideband input analog signals into digital signals and output them through a high-speed serial interface; wherein the input signal of the high-speed ADC module (1) adopts a single-ended input form to increase the integration, and the output of the high-speed ADC module (1) adopts a serial interface, supporting multiple serial data outputs at full rate.

3. The ultra-high-speed sampling and frequency measurement processing board for a single-bit receiver according to claim 1, characterized in that, The FPGA module (2) integrates several sets of programmable resources to implement multiple functions such as input / output interface, general digital logic, memory, digital signal processing and clock management; at the same time, the FPGA module (2) provides rich dedicated clock and wiring resources, which are suitable for implementing complex high-speed digital logic circuits. The FPGA module (2) is connected to the high-speed ADC module (1).

4. The ultra-high-speed sampling and frequency measurement processing board for a single-bit receiver according to claim 3, characterized in that, The FPGA module (2) works in conjunction with the high-speed ADC module (1) and transmits data through a high-speed interface. The FPGA module (2) receives the digital signal output by the high-speed ADC module (1), performs further processing and analysis on the received digital signal, and outputs the frequency and amplitude information of the signal.

5. The ultra-high-speed sampling and frequency measurement processing board for a single-bit receiver according to claim 1, characterized in that, The low-speed ADC module (3) is a high-resolution, single-channel analog-to-digital converter circuit. The low-speed ADC module (3) has high input bandwidth, fast sampling rate and good signal linearity. It is used to accurately convert the large dynamic linear video amplitude output by SDLVA into a digital signal and output it to the FPGA module (2) for subsequent processing to realize the extraction of signal amplitude information.

6. The ultra-high-speed sampling and frequency measurement processing board for a single-bit receiver according to claim 1, characterized in that, The interface module (5) is equipped with a differential LVDS level interface for transmitting frequency code and amplitude code; the interface module (5) is also designed with differential signal pairs, and the interface module (5) supports the simultaneous output of multiple pairs of differential signals.

7. The ultra-high-speed sampling and frequency measurement processing board for a single-bit receiver according to claim 1, characterized in that, The power module (4) adopts a power chip design and provides a stable power supply signal for each functional module; at the same time, the power module (4) is designed with a reserved margin.

Images