Wafer superposition chip packaging structure

Abstract

The utility model relates to the technical field of chip packaging, and discloses a wafer superposition chip packaging structure, which comprises a circuit board, and a conducting layer is arranged at the top of the circuit board. According to the wafer superposed chip packaging structure, the silicon intermediate plate is arranged, so that the main control wafer is arranged in the middle of the silicon intermediate plate, the four storage wafers surround the periphery of the main control wafer to form superposed packaging, and meanwhile, the distance between each storage wafer and the main control wafer is guaranteed when the storage wafers conduct data through the silicon intermediate plate; the four stacked storage wafers are all close to the main control wafer, so that the data communication speed among the four storage wafers during operation of the main control wafer is increased, the signal distance during information transmission between the main control wafer and the storage wafers is reduced, the energy consumption caused by overlong link in the transmission process is reduced, and the transmission efficiency is improved. Therefore, the storage capacity of the chip is increased by a plurality of stacked storage wafers, the operation efficiency of the chip is improved, the connection distance between parts is reduced, and the power consumption of operation is reduced.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging technology, and in particular to a wafer-stacked chip packaging structure. Background Technology

[0002] Chip packaging is a technology that isolates the internal circuitry of a chip from the external environment, protecting the chip from physical, chemical, and other external factors. It not only improves the stability and reliability of the chip, but also enhances its performance by optimizing the packaging design. With the rapid development of integrated circuit technology, chip packaging technology is also constantly improving to meet the demands for smaller size, higher integration, and better heat dissipation.

[0003] In practical applications, the traditional chip architecture suffers from inconsistent data transmission efficiency between the main control chip and the circuit board due to the difference in connection distance between different functional chips on the circuit board. The longer connection path increases the loss in the electronic signal transmission process, thereby reducing the efficiency of information transmission between chips. This not only increases energy consumption during operation, but also has a negative impact on the overall operating efficiency of the chip. Utility Model Content

[0004] The technical problem to be solved by this invention is that the existing technology has the disadvantage of unstable data transmission loss, which reduces the chip's operating performance. To address this, we propose a wafer-stacked chip packaging structure.

[0005] To achieve the above objectives, this application adopts the following technical solution: a wafer-stacked chip packaging structure, including a circuit board, a conductive layer disposed on the top of the circuit board, a plurality of solder joints fixedly connected to the top of the conductive layer, a wire carrier board electrically connected to the top of the solder joints, a silicon interposer disposed on the top of the wire carrier board, five micro-bumps bonded to the top of the silicon interposer board, a master control wafer fixedly connected to the top of the micro-bumps, a memory chip fixedly connected to the top of the micro-bumps, and a package shell fixedly connected to the top of the conductive layer.

[0006] Preferably, a barrier shell is fixedly connected to all four sides of the top of the silicon interposer, the main control wafer is placed inside the barrier shell, and the barrier shell is made of ceramic material.

[0007] Preferably, the area of ​​the micro-bump plate is larger than the size of the main control wafer and the memory chip.

[0008] Preferably, the interior of the connection between the barrier shell and the silicon intermediate plate is a vacuum.

[0009] Preferably, the space between the encapsulation shell and the conductor carrier is filled with epoxy resin.

[0010] Preferably, the micro-bump plate is made of gallium arsenide.

[0011] The technical effects and advantages of this utility model are as follows:

[0012] In this invention, a silicon interposer is used to position the main control wafer in the center of the interposer, and four memory chips surround the main control wafer to form a stacked package. This design ensures that each memory chip maintains a close distance to the main control wafer when transmitting data through the interposer, thereby improving the data communication speed between the main control wafer and the four memory chips during operation. It also reduces the signal distance between the main control wafer and the memory chips during information transmission, minimizing energy consumption caused by excessively long links. This allows the stacked memory chips to increase the chip's storage capacity and improve its operational efficiency, while simultaneously reducing the connection distance between components and lowering power consumption. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the main structure of this utility model;

[0014] Figure 2 This is a schematic diagram of the top structure of the silicon intermediate plate of this utility model;

[0015] Figure 3 This is a sectional view of the vertical cross-section of the present invention;

[0016] Figure 4 This is a schematic diagram showing the positional structure of the memory chip and the main control chip of this utility model;

[0017] Figure 5 This is a cross-sectional view of the internal structure of the barrier shell of this utility model.

[0018] Legend: 1. Circuit board; 2. Conductive layer; 3. Solder joint; 4. Conductor carrier board; 5. Silicon interposer; 6. Micro-bump plate; 7. Main control wafer; 8. Memory chip; 9. Package shell; 10. Barrier shell. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and preferred embodiments. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0020] Reference Figure 1 - Figure 5As shown, this utility model provides a technical solution: a wafer-stacked chip packaging structure, including a circuit board 1. A conductive layer 2 is disposed on the top of the circuit board 1. Several solder joints 3 are fixedly connected to the top of the conductive layer 2. A conductor carrier 4 is electrically connected to the top of the solder joints 3. A silicon interposer 5 is disposed on the top of the conductor carrier 4. Five micro-bumps 6 are attached to the top of the silicon interposer 5. A main control wafer 7 is fixedly connected to the top of the micro-bumps 6. A memory chip 8 is fixedly connected to the top of the micro-bumps 6. A packaging shell 9 is fixedly connected to the top of the conductive layer 2. Through the silicon interposer 5, the main control wafer 7 is positioned in the center of the silicon interposer 5. Four... The memory chips 8 are stacked around the main control wafer 7 to form a package. At the same time, the distance between each memory chip 8 and the main control wafer 7 is ensured when data is transmitted through the silicon interposer 5. This ensures that the four stacked memory chips 8 are close to the main control wafer 7, which improves the data communication speed between the four memory chips 8 when the main control wafer 7 is running. It also reduces the signal distance when the main control wafer 7 and the memory chips 8 transmit information, reduces the energy consumption caused by excessively long links during transmission, and increases the storage capacity of the chip by multiple stacked memory chips 8. This improves the chip's computing efficiency and reduces the power consumption during operation by reducing the connection distance between components.

[0021] Reference Figure 5 As shown in this embodiment: Barrier shells 10 are fixedly connected to all four sides of the top of the silicon interposer 5. The main control wafer 7 is placed inside the barrier shells 10. The barrier shells 10 are made of ceramic material. The barrier shells 10 surround and protect the outside of the main control wafer 7. Utilizing the high-temperature resistance and non-deformation properties of ceramic, and its ability to isolate external electromagnetic waves, the barrier shells 10 can isolate the influence of external electromagnetic waves on the operation of the main control wafer 7. During high-temperature operation of the chip, it is less prone to overheating and deformation damage, effectively ensuring the service life of the barrier shells 10 and improving the protective effect of the barrier shells 10 on the main control wafer 7.

[0022] Reference Figure 4 As shown in this embodiment: the area of ​​the micro-bump plate 6 is larger than the size of the main control wafer 7 and the memory chip 8. Because the area of ​​the micro-bump plate 6 that is bonded to the main control wafer 7 and the memory chip 8 is larger than the bottom area of ​​the main control wafer 7 and the memory chip 8, when the main control wafer 7 and the memory chip 8 deform and expand during high-temperature operation, the area of ​​the micro-bump plate 6 extending beyond the bottom of the main control wafer 7 and the memory chip 8 can still be placed at the bottom of the main control wafer 7 and the memory chip 8, achieving the effect of supporting the main control wafer 7 and the memory chip 8. This ensures the stability of the connection between the micro-bump plate 6 and the main control wafer 7 and the memory chip 8, and ensures the signal transmission efficiency between the main control wafer 7 and the memory chip 8 and the micro-bump plate 6, allowing them to remain stably bonded at high temperatures and ensuring signal transmission efficiency.

[0023] Reference Figure 5As shown in this embodiment: the interior of the connection between the barrier shell 10 and the silicon interposer 5 is a vacuum. By evacuating the air inside the connection between the barrier shell 10 and the silicon interposer 5 during the production process, the memory chip 8 operates in a vacuum environment. The vacuum environment ensures the sealing between the barrier shell 10 and the silicon interposer 5, reducing electromagnetic interference from the outside of the memory chip 8 and damage to the memory chip 8 caused by current conduction.

[0024] Reference Figure 3 As shown in this embodiment, the space between the encapsulation shell 9 and the conductor carrier 4 is filled with epoxy resin. By filling the encapsulation shell 9 with epoxy resin, the thermal conductivity between the barrier shell 10, the silicon interposer 5 micro-bump plate 6 of the main control wafer 7 and the encapsulation shell 9 is improved. This allows heat to be conducted to the encapsulation shell 9 through the filled epoxy resin, which is more conducive to the outward conduction of heat and improves the heat dissipation effect of the internal components of the encapsulation shell 9.

[0025] Reference Figure 3 and Figure 4 As shown in this embodiment, the micro-bump plate 6 is made of gallium arsenide. By using gallium arsenide material to make the micro-bump plate 6, and by taking advantage of the characteristics of gallium arsenide material, the micro-bump plate 6 has high heat resistance and stability, and its conductivity is more stable during long-term high-temperature operation. At the same time, it has a faster and more stable electron mobility, which improves the electron transmission speed in the micro-bump plate 6 and improves the operating performance of electronic devices.

[0026] Working Principle: The main control wafer 7 is positioned in the center of the silicon interposer 5. Four memory chips 8 surround the main control wafer 7, forming a stacked package. This design ensures that each memory chip 8 maintains a close proximity to the main control wafer 7 when transmitting data through the silicon interposer 5. This close proximity improves the data communication speed between the main control wafer 7 and the four memory chips 8, reduces the signal distance during information transmission between the main control wafer 7 and the memory chips 8, and minimizes energy consumption caused by excessively long links. Ultimately, the stacked memory chips 8 increase the chip's storage capacity and improve its operational efficiency. Simultaneously, reducing the connection distance between components lowers operating power consumption. The barrier shell 10 surrounds and protects the main control wafer 7. Utilizing the high-temperature resistance and non-deformation properties of ceramic, along with its ability to isolate external electromagnetic waves, the barrier shell 10 effectively shields the main control wafer 7 from external electromagnetic interference. This prevents overheating and deformation damage during high-temperature chip operation, effectively ensuring the lifespan of the barrier shell 10 and enhancing its protective effect on the main control wafer 7. Furthermore, the area where the micro-bump plate 6 adheres to the main control wafer 7 and the memory chip 8 is larger than the bottom area of ​​the main control wafer 7 and the memory chip 8, preventing deformation and expansion of the main control wafer 7 and the memory chip 8 during high-temperature operation. At the same time, the area at the bottom of the micro-bump plate 6, where it extends beyond the control wafer 7 and the memory chip 8, can still be placed on the bottom of the control wafer 7 and the memory chip 8, achieving the effect of supporting the control wafer 7 and the memory chip 8. This ensures the stability of the connection between the micro-bump plate 6 and the control wafer 7 and the memory chip 8, and ensures the signal transmission efficiency between the control wafer 7 and the memory chip 8 to the micro-bump plate 6, allowing them to remain stably bonded at high temperatures and ensuring signal transmission efficiency. By evacuating the internal air at the connection between the barrier shell 10 and the silicon interposer 5 during the production process, the memory chip 8 operates in a vacuum environment. This vacuum environment ensures the sealing between the barrier shell 10 and the silicon interposer 5, reducing the risk of damage to the memory chip. Damage to the memory chip 8 caused by electromagnetic interference and current conduction from the outside is mitigated by filling the inside of the package shell 9 with epoxy resin to improve the thermal conductivity between the barrier shell 10, the silicon interposer 5 of the main control wafer 7, the micro-bump plate 6, and the package shell 9. This allows heat to be conducted to the package shell 9 through the filled epoxy resin, which facilitates heat conduction outward and improves the heat dissipation of the components inside the package shell 9. The micro-bump plate 6 is made of gallium arsenide, and by utilizing the characteristics of gallium arsenide, the micro-bump plate 6 has high heat resistance and stability, and its conductivity is more stable during long-term high-temperature operation. At the same time, it has a faster and more stable electron mobility, which improves the electron transfer speed in the micro-bump plate 6 and improves the operating performance of electronic devices.

[0027] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A wafer-on-chip packaging structure, comprising a circuit board (1), characterized in that: The circuit board (1) has a conductive layer (2) on top, and a number of solder joints (3) are fixedly connected to the top of the conductive layer (2). A wire carrier board (4) is electrically connected to the top of the solder joints (3). A silicon interposer board (5) is provided on the top of the wire carrier board (4). Five micro-bumps (6) are attached to the top of the silicon interposer board (5). A master control wafer (7) is fixedly connected to the top of the micro-bumps (6). A memory chip (8) is fixedly connected to the top of the micro-bumps (6). A package shell (9) is fixedly connected to the top of the conductive layer (2).

2. The wafer-mounted chip packaging structure according to claim 1, characterized in that: The silicon interposer (5) is fixedly connected to a barrier shell (10) around its top. The main control wafer (7) is placed inside the barrier shell (10), which is made of ceramic material.

3. The wafer-mounted chip packaging structure according to claim 1, characterized in that: The area of ​​the micro-bump plate (6) is larger than the size of the main control wafer (7) and the memory chip (8).

4. The wafer-mounted chip packaging structure according to claim 2, characterized in that: The interior of the connection between the barrier shell (10) and the silicon intermediate plate (5) is a vacuum.

5. The wafer-mounted chip packaging structure according to claim 1, characterized in that: The space between the encapsulation shell (9) and the wire carrier plate (4) is filled with epoxy resin.

6. The wafer-mounted chip packaging structure according to claim 1, characterized in that: The micro-convex plate (6) is made of gallium arsenide.

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