N-type TOPCON battery with edge passivation structure
By setting an edge passivation structure at the edge of the N-type TOPCon cell, and utilizing the boron-doped emitter on the front side and the tunneling SiOx layer on the back side to form an insulating passivation region on the side of the silicon wafer, the problems of decreased edge passivation performance and insufficient light utilization of the cell are solved, thereby improving the cell's conversion efficiency and market competitiveness.
Patent Information
- Application Number
- CN202520471683.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2026-02-03
- Estimated Expiration
- 2035-03-18
AI Technical Summary
The N-type TOPCon cells suffer from reduced passivation performance at the cell edges and insufficient light utilization, which affects conversion efficiency.
An edge passivation structure is set at the edge of the battery, extending to the side of the silicon wafer through the boron-doped emitter on the front and the tunneling SiOx layer on the back, and forming an insulating passivation region between the two, which is covered by a composite insulating passivation layer.
This improved the battery's short-circuit current and open-circuit voltage, enhanced its photoelectric conversion efficiency, and strengthened its market competitiveness.
Smart Images
Figure CN223872683U_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of solar cell technology, specifically relating to an N-type TOPCON cell with an edge passivation structure. Background Technology
[0002] N-type TOPCon cells, also known as N-type tunneling oxide passivated contact cells, use N-type silicon wafers as substrates. The front structure of the cell consists of a boron-doped emitter, an AlOx layer, and a SiNx layer. The back structure consists of a back tunneling SiOx layer, a doped polycrystalline silicon layer, and a back SiNx layer (see [link to relevant documentation]). Figure 2 The front side of the battery is the light-absorbing surface, requiring the fabrication of a PN junction to form the emitter; the SiOx+ doped polycrystalline silicon layer serves as a tunneling passivation layer. The edge of the silicon wafer is a bare silicon insulating region.
[0003] Currently, N-type TOPCon cells feature a bare silicon design at the cell edges, with the silicon wafer thickness typically between 120 and 200 micrometers. This bare silicon design ensures complete insulation between the front and back sides of the wafer, preventing cell defects and efficiency losses due to leakage. However, bare silicon at the wafer edges also presents the following problems:
[0004] The battery has four sides, and the suspension keys on the sides are all composite centers, which will cause a decrease in the passivation performance of the battery, thus affecting the battery conversion efficiency. The battery edge can receive light, but cannot effectively utilize the light, resulting in waste and also affecting further improvement of battery conversion efficiency. Utility Model Content
[0005] This utility model provides an N-type TOPCON battery with an edge passivation structure, which aims to effectively utilize the battery edge to increase the short-circuit current and open-circuit voltage of the battery, thereby effectively improving the photoelectric conversion efficiency of the battery.
[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows: providing an N-type TOPCON cell with an edge passivation structure, comprising: an N-type silicon wafer as a substrate, wherein a front boron-doped emitter, a front AlOx layer and a front SiNx layer are sequentially disposed on the front side of the N-type silicon wafer, the front boron-doped emitter extends to the four sides of the N-type silicon wafer, and the portion of the front boron-doped emitter extending to the sides of the N-type silicon wafer is defined as an edge emitter;
[0007] The back side of the N-type silicon wafer is sequentially provided with a back tunneling SiOx layer, a doped polycrystalline silicon layer, and a back SiNx layer; the back tunneling SiOx layer extends to the four sides of the N-type silicon wafer, and the portion of the back tunneling SiOx layer extending to the four sides of the N-type silicon wafer is defined as an edge tunneling SiOx layer; an insulating passivation region is provided between the edge tunneling SiOx layer and the edge emitter; the doped polycrystalline silicon layer extends to the four sides of the N-type silicon wafer and covers the edge tunneling SiOx layer;
[0008] The front AlOx layer and the front SiNx layer extend to the four sides of the N-type silicon wafer, completely covering the edge tunneling SiOx layer, and forming a composite insulating passivation layer in the insulating passivation region.
[0009] In one possible implementation, the width W1 of the edge emitter covering the side of the N-type silicon wafer is 0-50 micrometers, wherein the thickness of the N-type silicon wafer is used as the width direction.
[0010] In one feasible embodiment, the width W1 of the edge emitter covering the side surface of the N-type silicon wafer is 20 micrometers to 50 micrometers.
[0011] In one feasible approach, the width W2 of the edge-tunneling SiOx layer covering the side surface of the N-type silicon wafer is 0-50 micrometers, wherein the thickness of the N-type silicon wafer is used as the width direction.
[0012] In one feasible approach, the width W2 of the edge-tunneling SiOx layer covering the side surface of the N-type silicon wafer is 20 micrometers to 50 micrometers.
[0013] In one feasible approach, the thickness of the front AlOx layer is 2nm-10nm.
[0014] In one feasible approach, the thickness of the front-side SiNx layer is 70nm-100nm.
[0015] In one feasible approach, the thickness of the backside SiNx layer is 60 nm to 90 nm.
[0016] In one possible implementation, the width of the insulating passivation region is greater than or equal to one-third of the thickness of the N-type silicon wafer, which has a thickness of 120 micrometers to 200 micrometers.
[0017] The N-type TOPCON battery with edge passivation structure provided by this utility model has the following advantages compared with the prior art: In order to fully utilize the silicon wafer, the ultimate goal of this invention is to adopt a battery edge structure, with the front boron-doped emitter extending to the side of the silicon wafer and the back tunneling SiOx layer extending to the side of the silicon wafer. An insulating passivation region exists between the two sides, covered by a composite insulating passivation layer. The specific effects are as follows:
[0018] (1) The boron-doped emitter on the side of the silicon wafer and the tunneling SiOx layer on the back are separated by a composite passivation insulating layer composed of non-conductive aluminum oxide and silicon nitride layers, which can effectively ensure the insulation of the front and back of the battery, prevent leakage, and ensure the battery conversion efficiency.
[0019] (2) Between the boron-doped emitter on the side of the silicon wafer and the tunneling SiOx layer on the back is a composite passivation insulating layer composed of non-conductive aluminum oxide and silicon nitride layers, which can effectively passivate the edge area, improve the open circuit voltage of the battery, and thus improve the conversion efficiency of the battery.
[0020] (3) By extending the boron-doped emitter on the front side to the side of the silicon wafer, the emitter area is increased, thereby improving the short-circuit current of the battery;
[0021] (4) A composite film passivation layer was added in the area far from the boron-doped emitter on the front side of the silicon wafer and close to the back side, which effectively improved the passivation performance of the battery and thus further improved the open circuit voltage of the battery.
[0022] In summary, the N-type TOPCON battery with edge passivation structure provided by this utility model improves the short-circuit current and open-circuit voltage of the battery, thereby effectively improving the battery's conversion efficiency and ultimately enhancing the market competitiveness of N-type batteries. Attached Figure Description
[0023] Figure 1 A schematic diagram of the structure of an N-type TOPCON battery with an edge passivation structure provided in an embodiment of this utility model;
[0024] Figure 2 A schematic diagram of the structure of an N-type TOPCON battery provided for the prior art;
[0025] Explanation of reference numerals in the attached figures:
[0026] 1. N-type silicon wafer; 2. Front boron-doped emitter; 3. Front AlOx layer; 4. Front SiNx layer; 5. Back tunneling SiOx layer; 6. Doped polycrystalline silicon layer; 7. Back SiNx layer; 8. Composite insulating passivation layer. Detailed Implementation
[0027] To make the technical problems, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.
[0028] Current N-type solar cells primarily passivate the front and back sides, while the edges of the silicon wafer are insulated using methods such as wet etching, laser etching, and plasma etching to prevent leakage caused by conduction between the front and back sides. However, the sides of the silicon wafer are not effectively utilized. To fully utilize the silicon wafer, this invention aims to expand the emitter area at the edge of the cell. Specifically, this is achieved by extending a boron-doped emitter from the front side to the side of the silicon wafer, and by tunneling a SiOx layer from the back side to the side of the silicon wafer. An insulating passivation region exists between these two locations, covered by a composite insulating passivation layer.
[0029] Please see Figure 1 The present invention will now describe the N-type TOPCON cell with an edge passivation structure. The N-type TOPCON cell with an edge passivation structure includes: an N-type silicon wafer 1 serving as a substrate; a front boron-doped emitter 2, a front AlOx layer 3, and a front SiNx layer 4 are sequentially disposed on the front side of the N-type silicon wafer 1; the front boron-doped emitter 2 extends to the four sides of the N-type silicon wafer 1; and the portion of the front boron-doped emitter 2 extending to the sides of the N-type silicon wafer 1 is defined as the edge emitter.
[0030] The back side of the N-type silicon wafer 1 is sequentially provided with a back tunneling SiOx layer 5, a doped polycrystalline silicon layer 6, and a back SiNx layer 7; the back tunneling SiOx layer 5 extends to the four sides of the N-type silicon wafer 1, and the portion of the back tunneling SiOx layer 5 extending to the four sides of the N-type silicon wafer 1 is defined as the edge tunneling SiOx layer; there is an insulating passivation region between the edge tunneling SiOx layer and the edge emitter; the doped polycrystalline silicon layer 6 extends to the four sides of the N-type silicon wafer 1 and covers the edge tunneling SiOx layer;
[0031] The front AlOx layer 3 and the front SiNx layer 4 extend to the four sides of the N-type silicon wafer 1, completely covering the edge tunneling SiOx layer, and forming a composite insulating passivation layer in the insulating passivation region.
[0032] The N-type TOPCON battery with edge passivation structure provided by this utility model has the following advantages compared with the prior art:
[0033] (1) The boron-doped emitter on the side of the silicon wafer and the tunneling SiOx layer 5 on the back are a composite passivation insulating layer composed of non-conductive aluminum oxide and silicon nitride layers, which can effectively ensure the insulation of the front and back of the battery, prevent leakage, and ensure the battery conversion efficiency.
[0034] (2) Between the boron-doped emitter on the side of the silicon wafer and the tunneling SiOx layer 5 on the back is a composite passivation insulating layer composed of non-conductive aluminum oxide and silicon nitride layers, which can effectively passivate the edge area, improve the open circuit voltage of the battery, and thus improve the conversion efficiency of the battery.
[0035] (3) By extending the boron-doped emitter 2 on the front side to the side of the silicon wafer, the emitter area is increased, thereby improving the short-circuit current of the battery;
[0036] (4) A composite film passivation layer was added in the area far from the boron-doped emitter 2 on the front side of the silicon wafer and close to the back side, which effectively improved the passivation performance of the battery and thus further improved the open circuit voltage of the battery.
[0037] In summary, the N-type TOPCON battery with edge passivation structure provided by this utility model improves the short-circuit current and open-circuit voltage of the battery, thereby effectively improving the battery's conversion efficiency and ultimately enhancing the market competitiveness of N-type batteries.
[0038] In some embodiments, see Figure 1 As shown, the width W1 of the edge emitter covering the side of the N-type silicon wafer 1 is 0-50 micrometers, where the thickness of the N-type silicon wafer 1 is used as the width direction. This ensures that the front boron-doped emitter 2 covers a certain area on the side of the silicon wafer, thereby improving the conversion efficiency of the cell.
[0039] In some embodiments, see Figure 1 As shown, the width W1 of the edge emitter covering the side of the N-type silicon wafer 1 is 20 micrometers to 50 micrometers. For example, this width is not limited to 10 micrometers, 15 micrometers, 22 micrometers, 25 micrometers, 30 micrometers, 36 micrometers, 43 micrometers, 48 micrometers, etc.
[0040] In some embodiments, see Figure 1 As shown, the width W2 of the edge-tunneling SiOx layer covering the side of the N-type silicon wafer 1 is 0-50 micrometers, where the thickness of the N-type silicon wafer 1 is used as the width direction. Specifically, the width of the front boron-doped emitter 2 extending to the side of the silicon wafer is 0-50 nm; the width of the back-side tunneling SiOx layer 5 extending to the side of the silicon wafer is 0-50 nm; the entire side of the silicon wafer is further covered with a composite insulating passivation layer of aluminum oxide and silicon nitride.
[0041] For example, the width of the edge emitter on the side of the silicon wafer is 5 micrometers, and the width of the edge tunneling SiOx layer is 5 micrometers; the width of the edge emitter is 10 micrometers, and the width of the edge tunneling SiOx layer is 5 micrometers; the width of the edge emitter is 20 micrometers, and the width of the edge tunneling SiOx layer is 25 micrometers; the width of the edge emitter is 35 micrometers, and the width of the edge tunneling SiOx layer is 15 micrometers. In general, the width of the edge emitter and the width of the edge tunneling SiOx layer can be the same or different, mainly to ensure that there is an insulating passivation region between them.
[0042] In some embodiments, see Figure 1 As shown, the width W2 of the edge-tunneled SiOx layer covering the side of the N-type silicon wafer 1 is 20 micrometers to 50 micrometers. For example, this width is unlimited, such as 5 micrometers, 12 micrometers, 15 micrometers, 22 micrometers, 25 micrometers, 30 micrometers, 33 micrometers, 36 micrometers, 43 micrometers, 48 micrometers, etc.
[0043] In some embodiments, the thickness of the front AlOx layer 3 is 2nm-10nm. For example, the thickness of the front AlOx layer 3 is 2nm, 3nm, 4nm, 5.5nm, 6.2nm, 7nm, 8.5nm, 9nm, 10nm, etc.
[0044] In some embodiments, see Figure 1 As shown, the thickness of the front-side SiNx layer 4 is 70 nm-100 nm. For example, the thickness of the front-side SiNx layer 4 is 70 nm, 75 nm, 78.5 nm, 81 nm, 84 nm, 86 nm, 87 nm, 90 nm, 94 nm, 97 nm, 99 nm, 100 nm, etc.
[0045] In some embodiments, see Figure 1 As shown, the thickness of the backside SiNx layer 7 is 60 nm-90 nm. For example, the thickness of the backside SiNx layer 7 is 60 nm, 61 nm, 63.5 nm, 65 nm, 68 nm, 70 nm, 71 nm, 73 nm, 74.5 nm, 76 nm, 80 nm, 82 nm, 85 nm, 88 nm, 88.5 nm, 90 nm, etc.
[0046] In some embodiments, see Figure 1As shown, the width of the insulating passivation region is greater than or equal to one-third of the thickness of the N-type silicon wafer 1, which has a thickness of 120 micrometers to 200 micrometers. For example, if the thickness of the N-type silicon wafer 1 is 120 micrometers, the width of the insulating passivation region is 45 micrometers, 50 micrometers, 80 micrometers, 100 micrometers, etc.; if the thickness of the N-type silicon wafer 1 is 180 micrometers, the width of the insulating passivation region is 60 micrometers, 65 micrometers, 80 micrometers, 90 micrometers, 120 micrometers, 130 micrometers, 158 micrometers, 164 micrometers, 170 micrometers, 178 micrometers, etc.
[0047] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0048] Existing battery structures such as Figure 2 As shown, the process flow is as follows:
[0049] Texturing → High-temperature boron diffusion → Wet cleaning and edge insulation treatment → SiO2 + polysi preparation → High-temperature phosphorus diffusion → Wet cleaning and edge insulation treatment → Front alumina preparation → Front silicon nitride preparation → Back silicon nitride preparation → Metallization.
[0050] The method for fabricating an N-type TOPCON battery with an edge passivation structure provided in this application includes the following steps:
[0051] Step 1, Pile Making
[0052] Preparation before texturing: First, the silicon wafer needs to be cleaned and de-damaged. The purpose of cleaning is to remove the mechanical damage layer, oil, and metallic impurities from the surface of the silicon wafer. After cleaning, a pyramid-shaped textured surface will form on the silicon wafer to reduce light reflection and improve light absorption efficiency.
[0053] Down-making process:
[0054] Alkaline texturing: This process uses an alkaline solution (such as sodium hydroxide NaOH, potassium hydroxide KOH, or tetramethylammonium hydroxide TMAH) to etch the surface of a silicon wafer, forming a pyramid structure. During alkaline texturing, the etching rate needs to be controlled at a low level (such as 2 μm / min or lower) to ensure the integrity of the pyramid structure.
[0055] Mechanical friction grooving: V-shaped blades are added to the texturing solution to perform mechanical friction grooving, combining the effects of chemical texturing and mechanical texturing to improve the light trapping effect.
[0056] Post-texturing treatment: After texturing, the silicon wafers need to be cleaned with deionized water and then dried in a sealed drying box.
[0057] The purpose of texturing: The main purpose of texturing is to reduce light reflection on the silicon wafer surface and increase light absorption, thereby improving the photoelectric conversion efficiency of the battery. By forming a pyramid structure, incident light undergoes multiple reflections and refractions on the silicon wafer surface, extending the optical path and increasing the generation of photogenerated carriers.
[0058] Quality control of texturing process: Factors affecting the quality of texturing process include silicon surface quality, etching time, etching solution concentration and temperature. Ensuring the cleanliness of the silicon wafer surface and controlling the etching time and etching solution concentration can obtain the ideal pyramid structure.
[0059] Step 2, High-temperature boron expansion
[0060] The purpose of boron diffusion is to diffuse p-type elements (boron) onto an n-type silicon wafer to form a PN junction. This step is usually carried out in a diffusion furnace, where a boron source (such as BBr3 or BCl3) vaporizes at high temperature and is deposited on the silicon wafer surface through a series of chemical reactions to form a suitable doping concentration and junction depth.
[0061] Step 3, wet cleaning: Using wet equipment, remove the borosilicate glass and emitters that are coated around the back of the silicon wafer and the edges of the silicon wafer adjacent to the back of the silicon wafer. Retain some borosilicate glass and emitters on the front of the silicon wafer and the edges of the silicon wafer adjacent to the front of the silicon wafer. That is, retain the edge boron-doped emitters coated around the side of the silicon wafer with a certain width. The width is 0-50 micrometers, with the thickness of the silicon wafer as the width direction.
[0062] Step 4, SiO2+polysi preparation: preparation of tunneling SiOx layer and intrinsic polysi.
[0063] Step 5, High-temperature phosphorus diffusion: Intrinsic polysi doping to complete the preparation of the tunneling SiOx layer.
[0064] Step 6, wet cleaning: Remove the tunneling SiOx layer deposited around the front side of the silicon wafer and the edge of the silicon wafer adjacent to the front side of the silicon wafer, and retain part of the tunneling oxide passivation layer on the back side of the silicon wafer and the edge of the silicon wafer adjacent to the back side of the silicon wafer, that is, retain the edge tunneling SiOx layer adjacent to the back side of the silicon wafer, with the thickness of the silicon wafer as the width direction, and retain the width range of 0-50 micrometers.
[0065] Step 7, Preparation of the front AlOx layer: While depositing front alumina, alumina is deposited on the side of the silicon wafer with a thickness of 2nm-10nm.
[0066] Step 8, Front-side silicon nitride fabrication: Simultaneously with the deposition of front-side silicon nitride, silicon nitride with a thickness of 70nm-100nm is deposited on the sides of the silicon wafer. That is, the front-side AlOx layer and the front-side SiNx layer extend to the four sides of the N-type silicon wafer, completely covering the edge tunneling SiOx layer and forming a composite insulating passivation layer in the insulating passivation region. Alternatively, the back-side SiNx layer can extend onto the front-side AlOx layer on the side.
[0067] Step 9, Preparation of the back SiNx layer: While depositing silicon nitride on the back side, silicon nitride with a thickness of 60nm-90nm is deposited on the side of the silicon wafer.
[0068] Step 10: Metallization, completing the battery fabrication.
[0069] The battery produced is as follows Figure 1 As shown, the phosphorus-doped polycrystalline silicon layer in the structure can be a multilayer phosphorus-doped polycrystalline silicon thin film, and the silicon nitride thin film can be a multilayer film containing multiple layers of silicon nitride and silicon oxynitride.
[0070] The battery data parameters prepared using this application are compared with those of the prior art as shown in Table 1:
[0071] Table 1
[0072]
[0073] A comparison of technical parameters shows that the battery provided in this application improves the short-circuit current and open-circuit voltage, thereby effectively improving the battery's conversion efficiency and ultimately enhancing the market competitiveness of N-type batteries.
[0074] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.
Claims
1. An N-type TOPCON battery with an edge passivation structure, characterized in that, include: The N-type silicon wafer (1) serves as a substrate. The front side of the N-type silicon wafer (1) is sequentially provided with a front boron-doped emitter (2), a front AlOx layer (3), and a front SiNx layer (4). The front boron-doped emitter (2) extends to the four sides of the N-type silicon wafer (1). The portion of the front boron-doped emitter (2) extending to the sides of the N-type silicon wafer (1) is defined as an edge emitter. The back side of the N-type silicon wafer (1) is sequentially provided with a back tunneling SiOx layer (5), a doped polycrystalline silicon layer (6), and a back SiNx layer (7); the back tunneling SiOx layer (5) extends to the four sides of the N-type silicon wafer (1), and the portion of the back tunneling SiOx layer (5) extending to the four sides of the N-type silicon wafer (1) is defined as an edge tunneling SiOx layer; there is an insulating passivation region between the edge tunneling SiOx layer and the edge emitter; the doped polycrystalline silicon layer (6) extends to the four sides of the N-type silicon wafer (1) and covers the edge tunneling SiOx layer; The front AlOx layer (3) and the front SiNx layer (4) extend to the four sides of the N-type silicon wafer (1), completely covering the edge tunneling SiOx layer, and forming a composite insulating passivation layer in the insulating passivation region.
2. The N-type TOPCON battery with an edge passivation structure as described in claim 1, characterized in that, The width W1 of the edge emitter covering the side of the N-type silicon wafer (1) is 0-50 micrometers, wherein the thickness of the N-type silicon wafer (1) is used as the width direction.
3. The N-type TOPCON battery with an edge passivation structure as described in claim 2, characterized in that, The width W1 of the edge emitter covering the side of the N-type silicon wafer (1) is 20 micrometers to 50 micrometers.
4. The N-type TOPCON battery with an edge passivation structure as described in claim 1, characterized in that, The width W2 of the edge tunneling SiOx layer covering the side of the N-type silicon wafer (1) is 0-50 micrometers, wherein the thickness of the N-type silicon wafer (1) is used as the width direction.
5. The N-type TOPCON battery with an edge passivation structure as described in claim 4, characterized in that, The width W2 of the edge tunneling SiOx layer covering the side of the N-type silicon wafer (1) is 20 micrometers to 50 micrometers.
6. The N-type TOPCON battery with an edge passivation structure as described in claim 1, characterized in that, The thickness of the front AlOx layer (3) is 2nm-10nm.
7. The N-type TOPCON battery with an edge passivation structure as described in claim 1, characterized in that, The thickness of the front SiNx layer (4) is 70nm-100nm.
8. The N-type TOPCON battery with an edge passivation structure as described in claim 1, characterized in that, The thickness of the back SiNx layer (7) is 60nm-90nm.
9. The N-type TOPCON battery with an edge passivation structure as described in claim 1, characterized in that, The width of the insulating passivation region is greater than or equal to 1 / 3 of the thickness of the N-type silicon wafer (1), and the thickness of the N-type silicon wafer (1) is 120 micrometers to 200 micrometers.