Battery wiring structure, perovskite and crystalline silicon laminated battery assembly and photovoltaic system

Abstract

The utility model discloses a cell wiring structure, a perovskite and crystalline silicon laminated cell assembly and a photovoltaic system, comprising a crystalline silicon cell layer, a perovskite cell layer and a packaging material layer, the perovskite cell layer and the crystalline silicon cell layer are distributed in a laminated manner, and the perovskite cell layer and the crystalline silicon cell layer have rated output voltage matched with each other. The perovskite cell layer and the crystalline silicon cell layer are both provided with bus bars with positive polarity and bus bars with negative polarity, and the bus bars with the same polarity have safety gaps on projection surfaces in the lamination direction. And the packaging material layer is arranged between the crystalline silicon cell layer and the perovskite cell layer in a laminated manner. Through voltage matching and safety gaps of the bus bars with the same polarity, mutual interference between output of the crystalline silicon cell layer and output of the perovskite cell layer can be reduced, the stability and safety requirements of output voltage are met, and therefore the wiring requirement of energy parallel output of the crystalline silicon cell layer and the perovskite cell layer is met; the number of junction boxes is reduced through a parallel output mode, the cable cost is reduced, and the compatibility of downstream products is improved.

Description

Technical Field

[0001] This utility model relates to the field of new energy technology, and in particular to a battery wiring structure, a perovskite and crystalline silicon tandem battery module and a photovoltaic system. Background Technology

[0002] In photovoltaic cells, four-terminal perovskite-crystalline silicon tandem cell modules have been mass-produced and applied due to their simple process (perovskite modules and crystalline silicon modules only need to be mechanically stacked). However, since both perovskite modules and crystalline silicon modules in the four-terminal tandem structure need to be connected to junction boxes independently, the cable cost is high and the compatibility with downstream products is low. Utility Model Content

[0003] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a battery wiring structure, a perovskite and crystalline silicon tandem battery module, and a photovoltaic system, which can meet the wiring requirements for parallel energy output, thereby reducing the number of junction boxes, lowering cable costs, and improving the compatibility of downstream products.

[0004] On one hand, this utility model embodiment provides a battery wiring structure, including:

[0005] Crystalline silicon solar cell layer;

[0006] The perovskite solar cell layer is stacked with the crystalline silicon solar cell layer and has a rated output voltage that matches the crystalline silicon solar cell layer. Both the perovskite solar cell layer and the crystalline silicon solar cell layer are provided with positive and negative current bars, and the current bars of the same polarity have a safety gap on the projection surface in the stacking direction.

[0007] An encapsulation material layer is stacked between the crystalline silicon cell layer and the perovskite cell layer.

[0008] According to some embodiments of the present invention, the perovskite solar cell layer is divided into multiple solar cell units based on a scribing method, and the multiple solar cell units are connected in series to obtain a rated output voltage that matches the crystalline silicon solar cell layer.

[0009] According to some embodiments of the present invention, the surface of the crystalline silicon battery layer is covered with a first light-transmitting protective layer.

[0010] According to some embodiments of the present invention, the busbars of the crystalline silicon cell layer and the perovskite cell layer both extend to the first light-transmitting protective layer.

[0011] According to some embodiments of the present invention, the first light-transmitting protective layer is provided with a first vent hole and a second vent hole arranged adjacent to each other. The first vent hole extends to the crystalline silicon cell layer, and the second vent hole penetrates the encapsulation material layer and extends to the perovskite cell layer. The busbar of the crystalline silicon cell layer passes through the first vent hole, and the busbar of the perovskite cell layer passes through the second vent hole.

[0012] According to some embodiments of the present invention, the busbar of the perovskite solar cell layer has a first segment, a second segment and a third segment. The first segment is located in the perovskite solar cell layer, the second segment is located in the second vent hole, and the third segment extends to the first light-transmitting protective layer. The first segment and the third segment are both located on the same side of the second segment and are both connected to the second segment at an angle.

[0013] According to some embodiments of the present invention, the surface of the perovskite solar cell layer is covered with a second light-transmitting protective layer.

[0014] According to some embodiments of the present invention, the crystalline silicon cell layer, the perovskite cell layer, and the encapsulation material layer are mechanically stacked.

[0015] On the other hand, this utility model embodiment provides a perovskite and crystalline silicon tandem solar cell module, including the above-mentioned cell wiring structure.

[0016] In another aspect, this utility model provides a photovoltaic system including the above-mentioned perovskite and crystalline silicon tandem cell module.

[0017] The embodiments of this utility model have at least the following beneficial effects:

[0018] By using voltage matching and safety gaps between busbars of the same polarity, mutual interference between the outputs of crystalline silicon and perovskite solar cells can be reduced, meeting the requirements for output voltage stability and safety. This satisfies the wiring requirements for parallel energy output of crystalline silicon and perovskite solar cells, thereby reducing the number of junction boxes, lowering cable costs, and improving the compatibility of downstream products through parallel output.

[0019] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0021] Figure 1This is a schematic diagram of the stacked structure of a perovskite and crystalline silicon tandem solar cell module according to an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the structure of a perovskite and crystalline silicon tandem solar cell module according to an embodiment of the present invention;

[0023] Figure 3 for Figure 2 A perspective view of the perovskite and crystalline silicon tandem solar cell assembly is shown (one of the junction boxes is hidden).

[0024] Figure 4 for Figure 2 Cross-sectional schematic diagrams of two examples of parallel wires in a perovskite and crystalline silicon tandem solar cell assembly are shown.

[0025] Figure 5 for Figure 2 The center circle shows a magnified view of a portion at position A;

[0026] Figure 6 for Figure 2 The center circle shows a magnified view of position B.

[0027] Figure 7 This is a schematic diagram of the structure of the wiring terminals in some embodiments of this utility model;

[0028] Figure 8 for Figure 3 A schematic diagram of the cross-sectional structure marked CC;

[0029] Figure 9 for Figure 8 The center circle shows a magnified view of position D.

[0030] Figure label:

[0031] Crystalline silicon cell layer 100, first positive electrode busbar 110, first negative electrode busbar 120, perovskite cell layer 200, second positive electrode busbar 210, second negative electrode busbar 220, first segment 211, second segment 212, third segment 213, encapsulation material layer 300, first light-transmitting protective layer 400, first vent hole 401, second vent hole 402, second light-transmitting protective layer 500, junction box 600, parallel wire 610, first path 611, second path 612, insulating layer 613, first electrode 614, second electrode 615, first terminal 616, second terminal 617. Detailed Implementation

[0032] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0033] In the description of this utility model, it should be understood that the directional descriptions, such as up, down, front, back, left, right, etc., indicate the directional or positional relationship based on the directional or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0034] In the description of this utility model, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If "first," "second," etc., are used in the description, they are only for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the sequential relationship of the indicated technical features.

[0035] In the description of this utility model, unless otherwise explicitly defined, the terms "setting", "installation", "connection", etc. should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this utility model in combination with the specific content of the technical solution.

[0036] Solar energy, as a clean and renewable energy source, has received widespread attention. Solar cells, as key devices for converting solar energy into electrical energy, have always been a research hotspot due to their conversion efficiency and stability. Perovskite cells and crystalline silicon cells are currently two important technologies in the field of solar cells. Perovskite cells have advantages such as low cost, high conversion efficiency, and flexible fabrication, while crystalline silicon cells have mature technology and high stability. Stacking perovskite and crystalline silicon cells can fully utilize the advantages of both, improving the overall performance of solar cells. However, traditional stacked cells face technical bottlenecks in current matching and process compatibility, limiting their development.

[0037] The wiring structure design of perovskite and crystalline silicon tandem solar cells directly affects the efficiency, cost, and compatibility with downstream industries. Currently, the mainstream technologies are two-terminal and four-terminal tandem solar cells, with significant differences in wiring methods, busbar leads, and the number of junction boxes between the two.

[0038] The core design of the two-terminal stacked battery structure is to connect the perovskite battery and the crystalline silicon battery in series through a tunneling connection layer (composite junction) to form a single circuit output (i.e., one positive and one negative electrode). Its wiring characteristics include:

[0039] 1) Internal series connection: The perovskite cell layer and the crystalline silicon cell layer are directly connected through a tunnel junction, without the need for external wiring, and the current is transmitted within the stacked layers.

[0040] 2) Simplified electrode: Only one layer of transparent conductive electrode (such as TCO, Transparent Conductive Oxide) is needed, avoiding the metal grid line design of traditional crystalline silicon cells and reducing light absorption loss;

[0041] 3) No laser scribing required: The electrodes adopt a conductive film + grid line process and are directly integrated with the crystalline silicon substrate, eliminating the need for the P1~P3 laser scribing steps of perovskite single junction cells.

[0042] Regarding busbars and junction boxes, since the output of the stacked cells at both ends is a single positive and negative terminal, the busbar is usually led out from the edge of the module, requiring only one junction box.

[0043] The core structural design of the four-terminal tandem solar cell consists of independent perovskite and crystalline silicon solar cell layers mechanically stacked together. The circuits are independent of each other, and its wiring characteristics include:

[0044] 1) Parallel optical coupling: The perovskite cell layer and the crystalline silicon module cell layer are only optically coupled (i.e., share incident light), and there is no direct circuit connection. External circuitry is required to achieve energy output.

[0045] 2) Dual-circuit output: The perovskite cell layer and the crystalline silicon cell layer each have a pair of positive and negative electrodes, that is, a total of four electrodes are required (two positive and two negative).

[0046] Regarding busbars and junction boxes, due to the mechanical stacking process, the perovskite and crystalline silicon solar cell layers do not need to consider voltage and current matching issues. They only need to have independent busbars led out, arranged vertically along the stacking direction and isolated by encapsulation materials. Because independent wiring is required, the amount of cables and junction boxes used is significantly higher than that of the two stacked ends, leading to increased material costs. Moreover, the wiring is complex and difficult for downstream products to be compatible.

[0047] In terms of applications, two-terminal stacked batteries are compatible with the existing industry chain and have lower costs, making them suitable for large-scale promotion, but the current matching problem needs to be solved; while four-terminal stacked batteries are easier to mass-produce in the short term due to their simple process (only mechanical stacking), but they face the challenge of industry chain adaptation due to the separate wiring and the design of four junction boxes.

[0048] Please refer to Figure 2 and Figure 3This embodiment discloses a battery wiring structure, which is a semi-finished product in the processing of a perovskite and crystalline silicon tandem battery module. The battery wiring structure includes a crystalline silicon battery layer 100, a perovskite battery layer 200, and an encapsulation material layer 300. The perovskite battery layer 200 and the crystalline silicon battery layer 100 are stacked and distributed, and have a rated output voltage that matches the crystalline silicon battery layer 100. Both the perovskite battery layer 200 and the crystalline silicon battery layer 100 are provided with positive and negative busbars, and the busbars of the same polarity have a safety gap (e.g., ...) on the projection plane in the stacking direction. Figure 3 As indicated by the mark L in the middle, the encapsulation material layer 300 is stacked between the crystalline silicon cell layer 100 and the perovskite cell layer 200. Through voltage matching and the safety gap of the same polarity busbars, mutual interference between the outputs of the crystalline silicon cell layer 100 and the perovskite cell layer 200 can be reduced, meeting the stability and safety requirements of the output voltage. This satisfies the wiring requirements for parallel energy output of the crystalline silicon cell layer 100 and the perovskite cell layer 200, thereby reducing the number of junction boxes, lowering cable costs, and improving the compatibility of downstream products through parallel output.

[0049] To facilitate understanding of the technical concept of the battery wiring structure in this embodiment, the following description is from the perspective of a photovoltaic system. This embodiment discloses a photovoltaic system including a perovskite and crystalline silicon tandem cell module, which can reduce the number of junction boxes, thereby reducing cable costs and improving the compatibility of downstream products.

[0050] Please refer to Figure 1 , Figure 2 and Figure 3 The perovskite and crystalline silicon tandem solar cell module includes a crystalline silicon cell layer 100, a perovskite cell layer 200, an encapsulation material layer 300 (such as EVA, ethylene-vinyl acetate copolymer), and a first light-transmitting protective layer 400. The perovskite cell layer 200 and the crystalline silicon cell layer 100 are stacked and distributed, and the perovskite cell layer 200 has a rated output voltage that matches the crystalline silicon cell layer 100. Both the perovskite cell layer 200 and the crystalline silicon cell layer 100 are provided with positive and negative busbars, and the busbars of the same polarity have a safety gap (e.g., ...) on their projection plane in the stacking direction. Figure 3 (as indicated by L in the middle); the encapsulation material layer 300 is stacked between the crystalline silicon cell layer 100 and the perovskite cell layer 200; the first light-transmitting protective layer 400 covers the crystalline silicon cell layer 100, and a junction box 600 with positive and negative polarities is provided on the first light-transmitting protective layer 400. The junction box 600 is provided with parallel wires 610, and the parallel wires 610 have two conductive paths. The two conductive paths are respectively electrically connected to the busbars of the same polarity of the crystalline silicon cell layer 100 and the perovskite cell layer 200.

[0051] For example, the crystalline silicon solar cell layer 100 is located below the perovskite solar cell layer 200 in a stack. The surface of the perovskite solar cell layer 200 is covered with a second light-transmitting protective layer 500. The crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200 adopt the design concept of four-terminal stacking. The crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200 are processed by mechanical stacking, which is simple and allows the crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200 to have independent positive and negative electrodes, respectively. That is, the crystalline silicon solar cell layer 100 is provided with a first positive electrode bus bar 110 and a first negative electrode bus bar 120, and the perovskite solar cell layer 200 is provided with a second positive electrode bus bar 210 and a second negative electrode bus bar 220. This can ensure the independent operation of the crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200 without considering the current matching problem. Unlike conventional four-terminal stacked cells, this embodiment performs voltage matching on the crystalline silicon cell layer 100 and the perovskite cell layer 200, meaning that the crystalline silicon cell layer 100 and the perovskite cell layer 200 have mutually matched rated output voltages. Furthermore, the spatial arrangement of the busbars of the same polarity in the crystalline silicon cell layer 100 and the perovskite cell layer 200 is adjusted, meaning that the busbars of the same polarity have a safety gap on the projection plane in the stacking direction. For example, the first positive busbar 110 and the second positive busbar 210 have a first safety gap on the projection plane in the stacking direction, and the first negative busbar 120 and the second negative busbar 220 have a second safety gap on the projection plane in the stacking direction. Busbars of the same polarity are connected for output via parallel conductors 610 in the same junction box 600. These parallel conductors 610 have two parallel conductive paths, ensuring the independence of the output from the crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200. The voltage matching design reduces the voltage difference between the two conductive paths, thereby reducing the potential difference during parallel transmission and preventing circulating current or power loss due to voltage imbalance, thus improving the stability of energy transmission. Furthermore, the same polarity busbars have safety gaps on their projection surfaces in the stacking direction, which physically isolate and weaken electric field coupling and leakage current interference between conductors, reducing the risk of short circuits and meeting the insulation redundancy requirements under complex conditions such as high humidity and mechanical deformation. By using parallel conductors 610 with dual conductive paths to connect the same polarity busbars of the crystalline silicon cell layer 100 and the perovskite cell layer 200 in parallel, the number of junction boxes 600 can be reduced, simplifying the manufacturing process and reducing cable material costs. By integrating the same polarity output of the two cell layers in a single junction box 600, the number of connection nodes is reduced, avoiding impedance mismatch and thermal failure risks caused by multi-point contact, while improving the compatibility of downstream products (such as inverters or energy storage devices).

[0052] To ensure the stability of the parallel output of the dual-cell layer, voltage matching design is required. In this embodiment, the perovskite cell layer 200 is divided into multiple cell units based on a scribe line method, and the multiple cell units are connected in series to obtain a rated output voltage that matches the crystalline silicon cell layer 100. It is worth mentioning that the open-circuit voltage (Voc) of the perovskite cell layer 200 can be estimated using formula (1) based on parameters such as the band gap (Eg), temperature (T), and Boltzmann constant (k) of the perovskite material, where ni is the intrinsic carrier concentration, NA and ND are the acceptor and donor impurity concentrations, respectively, and q is the elementary charge.

[0053] Formula (1):

[0054] Related technologies optimize the open-circuit voltage of the perovskite cell layer 200 by adjusting the band gap and impurity concentration of the material, thereby improving the rated output voltage. However, achieving voltage matching between the two cell layers by adjusting the band gap and impurity concentration of the material places high demands on the process. According to formula (1), under constant temperature conditions, the open-circuit voltage of the solar cell module is determined by the material, that is, the open-circuit voltage remains basically unchanged when the material is determined. For perovskite materials, given a fixed product area, different rated output voltages can be obtained by dividing the material into multiple battery cells and connecting these cells in series. For example, assuming that the rated output voltage of the crystalline silicon battery layer 100 is determined during the design phase, such as 240V, for a product with an area of ​​1600*1200mm, the perovskite battery layer 200 uses perovskite methylammonium lead iodide (MAPbI3) as the material, with an open-circuit voltage of approximately 1.2V. The perovskite methylammonium lead iodide battery panel can be laser-scribed to divide it into 200 battery cells, and these 200 cells can be connected in series to form the perovskite battery layer 200, resulting in a rated output voltage of approximately 240V. It should be noted that in this embodiment, the perovskite solar cell layer 200 and the crystalline silicon solar cell layer 100 are independently connected in parallel, and a safety gap is provided between the busbars of the same polarity. Therefore, the voltage matching of the perovskite solar cell layer 200 and the crystalline silicon solar cell layer 100 allows for a certain range of voltage difference between them, which is beneficial to increase the redundancy of voltage matching and reduce the design and processing difficulty of voltage matching. In this way, by scribing and connecting multiple cell units in series, different rated output voltages can be formed, reducing the voltage matching difficulty of the voltage dual-cell layer. In actual processing, scribing the crystalline silicon solar cell layer 100 significantly damages the photoelectric conversion efficiency of the cell layer, while scribing the perovskite solar cell layer 200 is less difficult and has less impact on the photoelectric conversion efficiency. Therefore, in the design stage, the rated output voltage of the crystalline silicon solar cell layer 100 is set first, and then the perovskite solar cell layer 200 is scribed for voltage matching. The open-circuit voltage reflects the battery's theoretical voltage output capability, while the output voltage reflects the battery's voltage output under actual operating conditions. The output voltage is always less than or equal to the open-circuit voltage.

[0055] Please refer to Figure 4 The two conductive paths of the parallel conductor 610 are coaxially arranged, and the two conductive paths are as follows: Figure 4(a) shows a first path 611 and a second path 612. The first path 611 is located radially inside the second path 612, which can effectively reduce the self-inductance and mutual inductance of the parallel conductor 610, reduce battery interference, and solve battery compatibility issues. The coaxial arrangement can also ensure that the current is evenly distributed in the two conductive paths, avoiding local overheating and current congestion, which is beneficial to improving the service life and safety of the conductor. An insulating layer 613 is provided between the two conductive paths, which can control the capacitive effect between the conductors, improve the stability and reliability of transmission, and has good mechanical strength and bending resistance, which is beneficial to improving the durability of the parallel conductor 610. In some other application examples, the two conductive paths of the parallel conductor 610 can be arranged side by side, such as Figure 4 (b) shows a first passage 611 and a second passage 612, with an insulating layer 613 disposed between the first passage 611 and the second passage 612.

[0056] In some application examples, the two conductive paths of the parallel wire 610 are respectively connected to the first electrode 614 and the second electrode 615, and the first electrode 614 and the second electrode 615 are coaxially arranged. Please refer to... Figure 5 , Figure 5 In the terminal block shown, the first electrode 614 is disposed on the inner wall of the terminal block, and the second electrode 615 is located radially inside the first electrode 614, and protrudes from the terminal block relative to the first electrode 614 in the axial direction. Please refer to... Figure 6 , Figure 6 The first electrode 614 in the terminal block shown is disposed on the outer wall of the terminal block, and the second electrode 615 ( Figure 6 Not shown in the image, please refer to the image below. Figure 5 The first electrode 614 is recessed into the terminal block relative to the first electrode 614 in the axial direction. The coaxial arrangement of the first electrode 614 and the second electrode 615 enables parallel output of the dual battery layers, reduces the number of terminals, and improves the compatibility of downstream products.

[0057] In other application examples, please refer to Figure 7 The parallel conductor 610 has two conductive paths connected to adjacent first terminals 616 and 617, respectively. A first electrode 614 is disposed within the first terminal 616, and a second electrode 615 is disposed within the second terminal 617. The first electrode 614 and the second electrode 615 are respectively disposed within the adjacent first terminal 616 and second terminal 617, which increases the safety gap between the first electrode 614 and the second electrode 615 and reduces the risk of short circuits. The two conductive paths within the parallel conductor 610 can be arranged coaxially or side-by-side.

[0058] Please refer to Figure 2 , Figure 5 and Figure 6 The positive polarity junction box 600 is connected to a male connector (such as...) via a corresponding parallel wire 610. Figure 2 (As shown in position A in the middle circle), the negative polarity junction box 600 is connected to a female terminal (such as...) via a corresponding parallel wire 610. Figure 2 As shown in position B (circled in the middle), the male and female connectors are mutually compatible. For example, Figure 5 The terminals shown are male connectors. Figure 6 The terminals shown are female connectors. The first positive busbar 110 and the second positive busbar 210 are both connected to the male connector via parallel wires 610 corresponding to the positive terminal box 600. Similarly, the first negative busbar 120 and the second negative busbar 220 are both connected to the female connector via parallel wires 610 corresponding to the negative terminal box 600. It should be noted that the terminal box 600 does not distinguish between positive and negative polarities before assembly. When the terminal box 600 is connected to a positive busbar, its polarity becomes positive; similarly, when the terminal box 600 is connected to a negative busbar, its polarity becomes negative. In applications, multiple perovskite and crystalline silicon tandem solar cell modules are used to form a photovoltaic array. Adjacent perovskite and crystalline silicon tandem solar cell modules can be connected in series using male and female connectors.

[0059] The integration of the two conductive paths of the parallel conductor 610 into one unit improves its mechanical strength, reduces the number of conductors, lowers wiring complexity during application, and maintains neat and concise wiring, thereby reducing error rates and costs during the wiring process. Simultaneously, simplifying the wiring structure also improves reliability and maintainability, reducing potential failure points caused by wiring complexity.

[0060] Please refer to Figure 3 , Figure 8 and Figure 9The first light-transmitting protective layer 400 is provided with a first vent hole 401 and a second vent hole 402 arranged adjacent to each other. The first vent hole 401 extends to the crystalline silicon cell layer 100, and the second vent hole 402 penetrates the encapsulation material layer 300 and extends to the perovskite cell layer 200. The busbar of the crystalline silicon cell layer 100 passes through the first vent hole 401, and the busbar of the perovskite cell layer 200 passes through the second vent hole 402. The busbars of the crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200 extend to the surface of the first light-transmitting protective layer 400 through the first vent hole 401 and the second vent hole 402, respectively, to enter the junction box 600. The busbars can be protected by the first light-transmitting protective layer 400 and the encapsulation material layer 300. The positions of the first vent hole 401 and the second vent hole 402 both avoid the crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200, which can prevent damage or obstruction to the crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200, and help ensure the photoelectric conversion efficiency of the crystalline silicon solar cell layer 100 and the perovskite solar cell layer 200.

[0061] Please refer to Figure 9 The busbar of the perovskite solar cell layer 200 has a first segment 211, a second segment 212, and a third segment 213. The first segment 211 is located in the perovskite solar cell layer 200, the second segment 212 is located in the second vent hole 402, and the third segment 213 is located in the junction box 600. The first segment 211 and the third segment 213 are both located on the same side of the second segment 212 and are both connected to the second segment 212 at an angle. In this way, the first segment 211, the second segment 212, and the third segment 213 can form a 180° bending structure, increasing the spatial distance between the busbar of the perovskite solar cell layer 200 and the busbar of the crystalline silicon solar cell layer 100 in the stacking direction (e.g., ...). Figure 9 As shown by the mark H in the middle, it achieves safe isolation between busbars of the same polarity, which helps to reduce mutual interference between busbars of the same polarity and reduce the risk of short circuit.

[0062] The embodiments of the present utility model have been described in detail above with reference to the accompanying drawings. However, the present utility model is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present utility model.

Claims

1. A battery wiring structure, characterized in that, include: Crystalline silicon cell layer (100); The perovskite solar cell layer (200) is stacked with the crystalline silicon solar cell layer (100) and has a rated output voltage that matches the crystalline silicon solar cell layer (100). Both the perovskite solar cell layer (200) and the crystalline silicon solar cell layer (100) are provided with positive and negative busbars, and the busbars of the same polarity have a safety gap on the projection surface in the stacking direction. An encapsulation material layer (300) is stacked between the crystalline silicon cell layer (100) and the perovskite cell layer (200).

2. The battery wiring structure according to claim 1, characterized in that, The perovskite solar cell layer (200) is divided into multiple solar cells by a scribing method, and the multiple solar cells are connected in series to obtain a rated output voltage that matches the crystalline silicon solar cell layer (100).

3. The battery wiring structure according to claim 1, characterized in that, The surface of the crystalline silicon cell layer (100) is covered with a first light-transmitting protective layer (400).

4. The battery wiring structure according to claim 3, characterized in that, The busbars of the crystalline silicon cell layer (100) and the perovskite cell layer (200) both extend to the first light-transmitting protective layer (400).

5. The battery wiring structure according to claim 4, characterized in that, The first light-transmitting protective layer (400) is provided with a first vent hole (401) and a second vent hole (402) arranged adjacent to each other. The first vent hole (401) extends to the crystalline silicon cell layer (100), and the second vent hole (402) penetrates the encapsulation material layer (300) and extends to the perovskite cell layer (200). The busbar of the crystalline silicon cell layer (100) passes through the first vent hole (401), and the busbar of the perovskite cell layer (200) passes through the second vent hole (402).

6. The battery wiring structure according to claim 5, characterized in that, The busbar of the perovskite solar cell layer (200) has a first segment (211), a second segment (212) and a third segment (213). The first segment (211) is located in the perovskite solar cell layer (200), the second segment (212) is located in the second vent hole (402), and the third segment (213) extends to the first light-transmitting protective layer (400). The first segment (211) and the third segment (213) are both located on the same side of the second segment (212) and are both connected to the second segment (212) at an angle.

7. The battery wiring structure according to any one of claims 1 to 6, characterized in that, The surface of the perovskite solar cell layer (200) is covered with a second light-transmitting protective layer (500).

8. The battery wiring structure according to claim 1, characterized in that, The crystalline silicon cell layer (100), the perovskite cell layer (200), and the encapsulation material layer (300) are mechanically stacked.

9. A perovskite and crystalline silicon tandem solar cell module, characterized in that, Includes the battery wiring structure as described in any one of claims 1 to 8.

10. A photovoltaic system, characterized in that, Includes the perovskite and crystalline silicon tandem solar cell module as described in claim 9.

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