Power semiconductor device

Abstract

The utility model discloses a power semiconductor device, a first conductive layer and a second conductive layer of the power semiconductor device are respectively connected to a copper-clad ceramic substrate, and the copper-clad ceramic substrate is used for being connected with an external circuit by taking the first conductive layer as a positive electrode and the second conductive layer as a negative electrode; the insulating layer is located between the first conductive layer and the second conductive layer, and the insulating layer is used for insulating the first conductive layer and the second conductive layer; the shell is arranged on the copper-clad ceramic substrate, the shell is used for protecting the copper-clad ceramic substrate, and one ends, far away from the copper-clad ceramic substrate, of the first conductive layer and the second conductive layer extend to the outside of the shell. According to the invention, the insulating layer is arranged between the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer are insulated through the insulating layer, so that the overlapping area and the distance between the first conductive layer and the second conductive layer can be further adjusted without worrying about the problem that the pouring sealant is not in place; and the production yield of the power semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Technology

[0002] Existing power semiconductor devices typically connect to a copper-clad ceramic substrate via a conductive mechanism to enable connection to external circuits. This conductive mechanism can include positive and negative copper busbars. When insulating the positive and negative copper busbars, current methods usually involve directly injecting potting compound into the module after the functional components on the copper-clad ceramic substrate have been soldered. The potting compound's self-flowing properties fill the areas requiring insulation. Then, air is extracted from the power semiconductor device, creating a negative pressure environment to release the air trapped in the potting compound. Finally, the potting compound is cured by heating.

[0003] However, the magnitude of stray inductance within a power semiconductor device is a crucial parameter for evaluating its design quality. Therefore, it's essential to minimize this stray inductance during the design process. Common methods for reducing stray inductance include shortening the length of the positive and negative circuits and stacking the positive and negative copper busbars. Circuit length typically depends on the chip and terminal layout, offering limited flexibility for adjustment; while stacking the positive and negative copper busbars results in a smaller distance between them, leading to lower stray inductance within the module.

[0004] In existing solutions using potting compound for insulation, the insulation performance of power semiconductor devices largely depends on the properties of the potting compound and the design spacing between devices. Due to the high viscosity of the potting compound, when the positive and negative copper busbars of the conductive mechanism are stacked on a large, closely spaced plane, the potting compound may struggle to flow to the areas requiring insulation. This can lead to gaps between the positive and negative copper busbars during curing, resulting in low yield rates for power semiconductor devices. Furthermore, commonly used potting compounds are flexible, making power semiconductor devices susceptible to deformation under impact, while rigid compounds are prone to cracking, further increasing the product failure rate. Therefore, there is an urgent need to improve the insulation performance of the positive and negative copper busbars while simultaneously reducing internal stray inductance and increasing production yield. Utility Model Content

[0005] To address the low yield problem associated with using potting compound for insulation in existing technologies, this application provides a power semiconductor device.

[0006] To address the technical problems existing in the prior art, this application provides a power semiconductor device, including a copper-clad ceramic substrate, a conductive mechanism, an insulating layer, and a housing. The conductive mechanism includes a first conductive layer and a second conductive layer, which are respectively connected to the copper-clad ceramic substrate. The copper-clad ceramic substrate is used to connect to an external circuit through the first conductive layer as a positive electrode and the second conductive layer as a negative electrode. The insulating layer is located between the first conductive layer and the second conductive layer and is used to insulate the first conductive layer and the second conductive layer. The housing is disposed on the copper-clad ceramic substrate and is used to protect the copper-clad ceramic substrate. The ends of the first and second conductive layers away from the copper-clad ceramic substrate extend to the outside of the housing.

[0007] Optionally, the projections of the first conductive layer and the second conductive layer on the copper-clad ceramic substrate overlap, and the insulating layer is located between the overlapping first conductive layer and the second conductive layer.

[0008] Optionally, the first conductive layer, the second conductive layer, the insulating layer, and the outer shell are integrally formed.

[0009] Optionally, the aforementioned housing is an injection-molded housing.

[0010] Optionally, the distance between the opposing surfaces of the first conductive layer and the second conductive layer is a first value, and the thickness of the insulating layer is a second value, wherein the first value is greater than or equal to the second value.

[0011] Optionally, the thickness of the above-mentioned insulating layer is less than or equal to 1 mm.

[0012] Optionally, the distance between the opposing surfaces of the first conductive layer and the second conductive layer is greater than 1 mm.

[0013] Optionally, the insulating layer is attached to the surface of the second conductive layer, and there is a gap between the first conductive layer and the insulating layer; or, the insulating layer is attached to the surface of the first conductive layer, and there is a gap between the second conductive layer and the insulating layer; or, the first conductive layer and the insulating layer are tightly attached, and the second conductive layer and the insulating layer are also tightly attached.

[0014] Optionally, the second conductive layer is fixed on the copper-clad ceramic substrate, the insulating layer is located on the side of the second conductive layer away from the copper-clad ceramic substrate, the first conductive layer is located on the side of the insulating layer away from the second conductive layer, and the first conductive layer, the insulating layer and the second conductive layer are stacked.

[0015] Optionally, the power semiconductor device includes two sets of conductive mechanisms and an output copper busbar. The output copper busbar is connected to the copper-clad ceramic substrate. The two sets of conductive mechanisms are respectively connected to both sides of the copper-clad ceramic substrate, and the output copper busbar is located between the two sets of conductive mechanisms.

[0016] Compared with the prior art, the power semiconductor device of this application includes a copper-clad ceramic substrate, a conductive mechanism, an insulating layer, and a housing. The conductive mechanism includes a first conductive layer and a second conductive layer, which are respectively connected to the copper-clad ceramic substrate. The copper-clad ceramic substrate is used to connect to an external circuit through the first conductive layer as a positive electrode and the second conductive layer as a negative electrode. The insulating layer is located between the first and second conductive layers and is used to insulate the first and second conductive layers. The housing is disposed on the copper-clad ceramic substrate and is used to protect the copper-clad ceramic substrate. The ends of the first and second conductive layers away from the copper-clad ceramic substrate extend to the outside of the housing. By setting an insulating layer between the first and second conductive layers, the power semiconductor device of this application can further adjust the overlap area and spacing of the first and second conductive layers without worrying about insufficient potting compound, thereby reducing the low yield caused by potting and curing and improving the production yield of the power semiconductor device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of the first embodiment of the power semiconductor device provided in this application;

[0019] Figure 2 for Figure 1 A schematic cross-sectional view of the power semiconductor device in the diagram, taken along line A-A'.

[0020] Figure 3 This is a schematic diagram of the structure of a second embodiment of the power semiconductor device provided in this application;

[0021] Figure 4 yes Figure 3 A schematic diagram of the middle conductive mechanism and the output copper busbar.

[0022] In the figure, 10 is a copper-clad ceramic substrate; 110 is a power device; 20 is a conductive mechanism; 21 is a first conductive layer; 211 is a first fixed side; 212 is a first conductive side; 22 is a second conductive layer; 221 is a second fixed side; 222 is a second conductive side; 30 is an insulating layer; 40 is a housing; and 50 is an output copper busbar. Detailed Implementation

[0023] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0024] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or connections separated by an intermediate medium. For those skilled in the art, if directional indicators (such as up, down, left, right, front, back, etc.) are involved in the embodiments of this application, these directional indicators are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indicators will also change accordingly.

[0026] This application first provides a power semiconductor device; please refer to [link to relevant documentation]. Figure 1-4 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the power semiconductor device provided in this application. Figure 2 for Figure 1 A schematic cross-sectional view of the power semiconductor device in the diagram, taken along line A-A'. Figure 3 This is a schematic diagram of the structure of the second embodiment of the power semiconductor device provided in this application. Figure 4 yes Figure 3 A schematic diagram of the intermediate conduction mechanism and the output copper busbar. (See diagram below.) Figure 1-4As shown, the power semiconductor device of this embodiment includes a copper-clad ceramic substrate 10, a conductive mechanism 20, an insulating layer 30, and a housing 40.

[0027] The conductive mechanism 20 includes a first conductive layer 21 and a second conductive layer 22, which are respectively connected to the copper-clad ceramic substrate 10. The copper-clad ceramic substrate 10 is used to connect to an external circuit through the first conductive layer 21 as the positive electrode and the second conductive layer 22 as the negative electrode. An insulating layer 30 is located between the first conductive layer 21 and the second conductive layer 22 and is used to insulate the first conductive layer 21 and the second conductive layer 22. A housing 40 is disposed on the copper-clad ceramic substrate 10 and is used to protect the copper-clad ceramic substrate 10. One end of the first conductive layer 21 and the second conductive layer 22 away from the copper-clad ceramic substrate 10 extends to the outside of the housing 40.

[0028] Specifically, the copper-clad ceramic substrate 10 is a substrate formed by bonding a copper metal layer to a ceramic substrate using direct bonding technology. The copper-clad ceramic substrate 10 is also soldered with several power devices 110, such as semiconductor chips and control circuits. The first conductive layer 21 may include a first fixed side 211 and a first conductive side 212, and the second conductive layer 22 may include a second fixed side 221 and a second conductive side 222. The first fixed side 211 and the second fixed side 221 are fixed to the copper-clad ceramic substrate 10, and the first conductive side 212 and the second conductive side 222 extend beyond the copper-clad ceramic substrate 10 and are exposed outside the outer casing 40, allowing the copper-clad ceramic substrate 10 to be connected to an external circuit via the first conductive layer 21 as the positive electrode and the second conductive layer 22 as the negative electrode. That is, in this embodiment, the first conductive layer 21 can serve as the positive copper busbar of the copper-clad ceramic substrate 10, and the second conductive layer 22 can serve as the negative copper busbar of the copper-clad ceramic substrate 10.

[0029] The housing 40 is used to provide mechanical protection for the power device 110 on the copper-clad ceramic substrate 10 and to provide electrical insulation for the power device 110 on the copper-clad ceramic substrate 10. The conductive sides of the first conductive layer 21 and the second conductive layer 22 extend beyond the coverage area of ​​the housing 40 so that external circuits can be stably connected to the conductive sides of the first conductive layer 21 and the second conductive layer 22.

[0030] In this embodiment, the power semiconductor device uses an insulating layer 30 between the first conductive layer 21 and the second conductive layer 22 to insulate them. The overlapping area and spacing of the first and second conductive layers 21 and 22 can be further adjusted without worrying about insufficient potting compound. Even if potting compound does not flow into the space between the first and second conductive layers 21 and 22 during subsequent potting, the insulation performance between them will not be affected. This further reduces the low yield caused by potting curing and improves the production yield of the power semiconductor device. Furthermore, using the insulating layer 30 to insulate the first and second conductive layers 21 and 22, compared to potting compound insulation which requires consideration of the potting compound's influence, reduces the limitations of terminal layout on the copper-clad ceramic substrate 10, making the terminal layout on the copper-clad ceramic substrate 10 more flexible and reducing the design difficulty of the power semiconductor device.

[0031] In one embodiment, the projections of the first conductive layer 21 and the second conductive layer 22 on the copper-clad ceramic substrate 10 overlap, and the insulating layer 30 is located between the overlapping first conductive layer 21 and the second conductive layer 22.

[0032] Specifically, the projection surface of the first conductive layer 21 on the copper-clad ceramic substrate 10 is the first projection surface, and the projection surface of the second conductive layer 22 on the copper-clad ceramic substrate 10 is the second projection surface. The first projection surface and the second projection surface at least partially overlap. It can be understood that since the conductive sides of the first conductive layer 21 and the second conductive layer 22 extend beyond the copper-clad ceramic substrate 10, i.e., the conductive sides of the first conductive layer 21 and the second conductive layer 22 are not projected onto the copper-clad ceramic substrate 10, the aforementioned projection surface can be understood as including the projection surfaces of the first fixed side 211 and the second fixed side 221 on the copper-clad ceramic substrate 10. The insulating layer 30 is located between the overlapping projection surfaces of the first conductive layer 21 and the second conductive layer 22, i.e., the insulating layer 30 is located between the first fixed side 211 and the second fixed side 221, so that the first conductive layer 21, the insulating layer 30, and the second conductive layer 22 form a stacked structure. The insulating layer 30 can insulate the overlapping portion of the first conductive layer 21 and the second conductive layer 22.

[0033] The power semiconductor device of this embodiment can adjust the spacing between the first conductive layer 21 and the second conductive layer 22 by adjusting the thickness of the insulating layer 30. Furthermore, compared to using potting compound for insulation, even if the overlap area of ​​the first conductive layer 21 and the second conductive layer 22 in this embodiment is large, there is no need to worry about insufficient potting compound coverage. This allows the power semiconductor device of this embodiment to reduce stray inductance and improve performance by adjusting the overlap area and spacing between the first conductive layer 21 and the second conductive layer 22.

[0034] Optionally, the first conductive layer 21, the second conductive layer 22, the insulating layer 30, and the outer shell 40 are integrally formed.

[0035] Specifically, in this embodiment, the first conductive layer 21, the second conductive layer 22, and the insulating layer 30 of the power semiconductor device can be pre-placed on the copper-clad ceramic substrate 10. The first conductive layer 21, the second conductive layer 22, and the insulating layer 30 are integrally formed with the outer casing 40 as inserts, so that the first conductive layer 21, the second conductive layer 22, the insulating layer 30, and the outer casing 40 are connected as a whole. The outer casing 40 can be formed by, but is not limited to, injection molding, metal injection molding, plastic forming, casting, etc.

[0036] In this embodiment, the power semiconductor device uses the first conductive layer 21, the second conductive layer 22, and the insulating layer 30 as inserts, integrally formed with the outer casing 40. This allows the first conductive layer 21, the second conductive layer 22, and the insulating layer 30 to be formed and cured together with the outer casing 40, improving the stability of the first conductive layer 21, the second conductive layer 22, and the insulating layer 30, enhancing the impact resistance of the power semiconductor device, further reducing the problem of low yield caused by potting and curing, and improving the production yield of the power semiconductor device.

[0037] Furthermore, the outer shell 40 is an injection-molded shell.

[0038] Specifically, the first conductive layer 21, the second conductive layer 22, and the insulating layer 30 are injection molded together with the outer shell 40 as injection molding inserts, so that the first conductive layer 21, the second conductive layer 22, the insulating layer 30 and the outer shell 40 are connected as one unit, thereby improving the stability of the first conductive layer 21, the second conductive layer 22, and the insulating layer 30.

[0039] In one embodiment, the distance between the opposing surfaces of the first conductive layer 21 and the second conductive layer 22 is a first value, and the thickness of the insulating layer 30 is a second value, wherein the first value is greater than the second value.

[0040] Specifically, since the first conductive layer 21, the insulating layer 30, and the second conductive layer 22 form a stacked structure, the first conductive layer 21 has a first surface opposite to the insulating layer 30, and the second conductive layer 22 has a second surface opposite to the insulating layer 30. The distance between the first surface and the second surface can be defined as a first value, and the thickness of the insulating layer 30 is a second value. The first value is greater than or equal to the second value. When the first value is greater than the second value, the insulating layer 30 is in contact with one of the first and second surfaces, and there is a gap between the insulating layer 30 and the other of the first and second surfaces, facilitating the placement of the insulating layer 30. When the first value is equal to the second value, the insulating layer 30 is in contact with both the first and second surfaces, reducing the distance between the first and second surfaces and further reducing the stray inductance of the power semiconductor device.

[0041] In one embodiment, the thickness of the insulating layer 30 is less than or equal to 1 mm.

[0042] Specifically, the thickness of the insulating layer 30 can be 0.05mm, 0.1mm, 0.15mm, 0.2mm, 0.25mm, 0.3mm, 0.35mm, 0.4mm, 0.45mm, 0.5mm, 0.55mm, 0.6mm, 0.65mm, 0.7mm, 0.75mm, 0.8mm, 0.85mm, 0.9mm, 0.95mm, or 1mm. The thickness of the insulating layer 30 can be selected based on the material, withstand voltage performance, stray inductance requirements, etc., and is not specifically limited here.

[0043] Understandably, the distance between the copper busbars in the stacked design of the first conductive layer 21 and the second conductive layer 22 is a key factor in evaluating the performance of a power semiconductor device. With other parts having the same structure and under the same testing environment, when the distance between the first and second surfaces is 2mm, the stray inductance inside the power semiconductor device is 7nH; when the distance between the first and second surfaces is adjusted to 0.25mm, the stray inductance drops from 7nH to 3nH, a significant reduction. However, when using potting compound for insulation, due to the adhesiveness of the potting compound, when the stacked area of ​​the first conductive layer 21 and the second conductive layer 22 is large and the distance is close, for example, when the distance between the first and second surfaces is between 1mm and 2mm or less, the potting compound may not be fully in place. In this embodiment, the thickness of the insulating layer 30 is less than or equal to 1mm, allowing the distance between the first and second surfaces to be set at 1mm or less, which can significantly reduce the stray inductance of the power semiconductor device.

[0044] Optionally, the distance between the opposing surfaces of the first conductive layer 21 and the second conductive layer 22 is greater than 1 mm.

[0045] Specifically, the distance between the opposing surfaces of the first conductive layer 21 and the second conductive layer 22 is greater than 1 mm, and the thickness of the insulating layer 30 is less than or equal to 1 mm, facilitating the placement of the insulating layer 30 between the first and second surfaces. In this embodiment, by setting the distance between the opposing surfaces of the first conductive layer 21 and the second conductive layer 22 to be greater than 1 mm, the height of the power semiconductor device can be effectively reduced, and the power density of the power semiconductor device can be increased.

[0046] In one embodiment, the insulating layer 30 is attached to the surface of the second conductive layer 22, and there is a gap between the first conductive layer 21 and the insulating layer 30; or, the insulating layer 30 is attached to the surface of the first conductive layer 21, and there is a gap between the second conductive layer 22 and the insulating layer 30; or, the first conductive layer 21 and the insulating layer 30 are tightly attached, and the second conductive layer 22 and the insulating layer 30 are also tightly attached.

[0047] Specifically, the way the insulating layer 30 is disposed between the first conductive layer 21 and the second conductive layer 22 may include: the insulating layer 30 is attached to the surface of the second conductive layer 22, and there is a gap between the first conductive layer 21 and the insulating layer 30; or, the insulating layer 30 is attached to the surface of the first conductive layer 21, and there is a gap between the second conductive layer 22 and the insulating layer 30; or, the first conductive layer 21 and the insulating layer 30 are tightly attached, and the second conductive layer 22 and the insulating layer 30 are tightly attached.

[0048] In this way, when the first conductive layer 21, the second conductive layer 22, and the insulating component are used as inserts during the molding of the outer casing 40, the positions of the first conductive layer 21, the second conductive layer 22, and the insulating component can be fixed, ensuring the stability of the first conductive layer 21, the insulating layer 30, and the second conductive layer 22, and enhancing the impact resistance of the power semiconductor device.

[0049] In one embodiment, the second conductive layer 22 is fixed on the copper-clad ceramic substrate 10, the insulating layer 30 is located on the side of the second conductive layer 22 away from the copper-clad ceramic substrate 10, the first conductive layer 21 is located on the side of the insulating layer 30 away from the second conductive layer 22, and the first conductive layer 21, the insulating layer 30 and the second conductive layer 22 are stacked.

[0050] Specifically, the second conductive layer 22 is fixed to the copper-clad ceramic substrate 10 as a negative electrode copper busbar. The second conductive layer 22 can be fixed by screws, bolts, or welding. The insulating layer 30 is disposed on the side of the second conductive layer 22 away from the copper-clad ceramic substrate 10, and the first conductive layer 21 is located on the side of the insulating layer 30 away from the second conductive layer 22. The copper-clad ceramic substrate 10, the second conductive layer 22, the insulating layer 30, and the first conductive layer 21 are stacked sequentially to form a stacked structure of the first conductive layer 21 and the second conductive layer 22. Unlike potting compound insulation, which requires consideration of the potting compound's influence, the power semiconductor device in this embodiment uses an insulating layer 30 between the second conductive layer 22 and the first conductive layer 21 for insulation treatment. This reduces the limitations of the terminal layout on the copper-clad ceramic substrate 10, making the terminal layout on the copper-clad ceramic substrate 10 more flexible and reducing the design difficulty of the power semiconductor device.

[0051] In one embodiment, the power semiconductor device includes two sets of conductive mechanisms 20 and an output copper busbar 50. The output copper busbar 50 is connected to a copper-clad ceramic substrate 10. The two sets of conductive mechanisms 20 are respectively connected to both sides of the copper-clad ceramic substrate 10, and the output copper busbar 50 is located between the two sets of conductive mechanisms 20.

[0052] Specifically, the power semiconductor device may include two sets of conductive mechanisms 20 connected to the copper-clad ceramic substrate 10. The first set of conductive mechanisms 20 is disposed on one side of the copper-clad ceramic substrate 10, and the second set of conductive mechanisms 20 is disposed on the side of the copper-clad ceramic substrate 10 away from the first set of conductive mechanisms 20. The power semiconductor device may also include an output copper busbar 50, which is connected to the copper-clad ceramic substrate 10 and is located between the first set of conductive mechanisms 20 and the second set of conductive mechanisms 20, so that the power device 110 on the copper-clad ceramic substrate can be connected to an external control device through the output copper busbar 50.

[0053] In one embodiment, the heat distortion temperature of the insulating layer 30 can be greater than the injection molding temperature of the housing 40, so that the insulating layer 30 is not affected during the molding process of the housing 40, thereby improving the stability of the insulating layer 30 and thus improving the reliability of the semiconductor device.

[0054] In one embodiment, the insulation layer 30 is able to perform normally at a temperature greater than 200°C to ensure the insulation performance of the insulation layer 30.

[0055] In one embodiment, the insulation class of the insulation layer 30 can be between F-class insulation and H-class insulation, that is, the insulation layer 30 can maintain its insulation performance between 155°C and 180°C, thereby improving the stability of the insulation layer 30.

[0056] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A power semiconductor device, characterized in that, include: Copper-clad ceramic substrate; A conductive mechanism includes a first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer being respectively connected to the copper-clad ceramic substrate, the copper-clad ceramic substrate being used to connect to an external circuit through the first conductive layer as a positive electrode and the second conductive layer as a negative electrode. An insulating layer is located between the first conductive layer and the second conductive layer, and the insulating layer is used to insulate the first conductive layer and the second conductive layer. A housing is disposed on the copper-clad ceramic substrate, the housing being used to protect the copper-clad ceramic substrate, and the ends of the first conductive layer and the second conductive layer away from the copper-clad ceramic substrate extending to the outside of the housing.

2. The power semiconductor device according to claim 1, characterized in that, The projections of the first conductive layer and the second conductive layer on the copper-clad ceramic substrate overlap, and the insulating layer is located between the overlapping first conductive layer and the second conductive layer.

3. The power semiconductor device according to claim 1, characterized in that, The first conductive layer, the second conductive layer, the insulating layer, and the outer shell are integrally formed.

4. The power semiconductor device according to claim 2, characterized in that, The outer shell is an injection-molded shell.

5. The power semiconductor device according to claim 1, characterized in that, The distance between the opposing surfaces of the first conductive layer and the second conductive layer is a first value, and the thickness of the insulating layer is a second value, wherein the first value is greater than or equal to the second value.

6. The power semiconductor device according to claim 1, characterized in that, The thickness of the insulating layer is less than or equal to 1 mm.

7. The power semiconductor device according to claim 6, characterized in that, The distance between the opposing surfaces of the first conductive layer and the second conductive layer is greater than 1 mm.

8. The power semiconductor device according to claim 1, characterized in that, The insulating layer is attached to the surface of the second conductive layer, and there is a gap between the first conductive layer and the insulating layer; or, the insulating layer is attached to the surface of the first conductive layer, and there is a gap between the second conductive layer and the insulating layer; or, the first conductive layer and the insulating layer are tightly attached, and the second conductive layer and the insulating layer are tightly attached.

9. The power semiconductor device according to claim 1, characterized in that, The second conductive layer is fixed on the copper-clad ceramic substrate, the insulating layer is located on the side of the second conductive layer away from the copper-clad ceramic substrate, the first conductive layer is located on the side of the insulating layer away from the second conductive layer, and the first conductive layer, the insulating layer and the second conductive layer are stacked.

10. The power semiconductor device according to claim 1, characterized in that, The power semiconductor device includes two sets of conductive mechanisms and an output copper busbar. The output copper busbar is connected to the copper-clad ceramic substrate. The two sets of conductive mechanisms are respectively connected to both sides of the copper-clad ceramic substrate, and the output copper busbar is located between the two sets of conductive mechanisms.

Images