Power semiconductor device and method

Abstract

Power semiconductor device and method. A power semiconductor device includes an active region having at least one power cell, wherein the active region has a total volume, the total volume has a central volume forming at least 20% of the total volume; a peripheral volume forming at least 20% of the total volume and surrounding the central volume; and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The power semiconductor device further includes an edge termination region surrounding the outermost peripheral volume of the active region; a semiconductor body having a front side and a back side; a first load terminal at the front side of the semiconductor body and a second load terminal at the back side of the semiconductor body; a first doped semiconductor region formed in the semiconductor body and electrically connected to the first load terminal; a second doped semiconductor region formed in the semiconductor body and electrically connected to the second load terminal.

Description

TECHNICAL FIELD

[0001] The present specification relates to embodiments of power semiconductor devices and to embodiments of methods of processing power semiconductor devices. In particular, the present specification relates to aspects of front-side and / or back-side emitters configured in a peripheral volume adjacent to an edge termination region of a power semiconductor device. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving electric motors or machines, rely on power semiconductor switches. For example, just to name a few, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes have been used in a variety of applications, including but not limited to switching in power supplies and power converters.

[0003] A power semiconductor device typically comprises a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device.

[0004] Further, in case of controllable power semiconductor devices, such as transistors, the load current path can be controlled by means of an insulating electrode, often referred to as gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to be in one of a conducting state and a blocking state. In some cases, the gate electrode can be comprised within a trench of the power semiconductor switch, wherein the trench can exhibit, for example, a stripe configuration or a needle configuration.

[0005] Irrespective of whether a power semiconductor device is implemented as an uncontrollable device, such as an uncontrollable diode, or as a controllable device, such as a transistor, thyristor, or the like, it is generally desirable to provide a reliable device exhibiting a low risk of failure, for example, due to overheating and / or so-called dynamic avalanche.

[0006] To this end, it can be desirable to adjust a spatial distribution of a load current density in the semiconductor body. SUMMARY

[0007] Aspects described herein relate to front-side and / or back-side emitters in a peripheral volume adjacent to an edge termination region of a power semiconductor device. Implementing the emitter(s) can involve configuring the emitter(s) with respect to their lateral and / or longitudinal average dopant dose profiles, wherein such profile(s) can be designed so as to achieve a specified load current density distribution in the power semiconductor body.

[0008] According to an embodiment, a power semiconductor device comprises: an active region having at least one power cell, wherein the active region has a total volume, the total volume having: a central volume forming at least 20% of the total volume; a peripheral volume forming at least 20% of the total volume and surrounding the central volume; and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The power semiconductor device further comprises: an edge termination region surrounding an outermost peripheral volume of the active region, wherein the peripheral volume has a constant lateral distance from the edge termination region; a semiconductor body having a front side and a back side, wherein the semiconductor body forms both a part of the active region and a part of the edge termination region; a first load terminal at the semiconductor body front side and a second load terminal at the semiconductor body back side; a first doped semiconductor region formed in the semiconductor body and electrically connected with the first load terminal; a second doped semiconductor region formed in the semiconductor body and electrically connected with the second load terminal. At least one of the first doped semiconductor region and the second doped semiconductor region has: a central portion extending into the central volume of the active region and having a central average dopant dose; a peripheral portion extending into the peripheral volume of the active region and having a peripheral average dopant dose, wherein the central average dopant dose is at least 5% lower or at least 10% lower than the peripheral average dopant dose.

[0009] According to an embodiment, a power semiconductor device comprises: an active region having at least one power cell, wherein the active region has a total volume, the total volume having: a central volume forming at least 80% of the total volume; a peripheral volume surrounding the central volume; and an edge termination region arranged outside the active region and surrounding the peripheral volume; a semiconductor body having a front side and a back side, wherein the semiconductor body forms a part of each of the active region, the peripheral volume, and the edge termination region. The semiconductor body has a total thickness along a vertical direction between the front side and the back side. The peripheral volume has a lateral extension amounting to at least half of the total semiconductor body thickness. The power semiconductor device further comprises: a first load terminal at the semiconductor body front side and a second load terminal at the semiconductor body back side; a first doped semiconductor region formed in the semiconductor body and electrically connected with the first load terminal; a second doped semiconductor region formed in the semiconductor body and electrically connected with the second load terminal. The second doped semiconductor region has: a central portion extending into the central volume of the active region and having a central average dopant dose; a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose, the peripheral average dopant dose having a negative gradient in a lateral direction towards the edge termination region along the lateral extension of the peripheral volume; and an edge portion extending into the edge termination region and having an edge average dopant dose, wherein the edge average dopant dose is at least 5% lower than the central average dopant dose.

[0010] According to an embodiment, a power semiconductor device comprises an active region having at least one power cell, wherein the active region has a total volume, the total volume having: a central volume forming at least 20% of the total volume; a peripheral volume forming at least 20% of the total volume and surrounding the central volume; and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The power semiconductor device further comprises an edge termination region surrounding an edge of the outermost peripheral volume of the active region, wherein the peripheral volume has a constant lateral distance from the edge termination region; a semiconductor body having a front side and a back side, wherein the semiconductor body forms both a portion of the active region and a portion of the edge termination region; a first load terminal at the semiconductor body front side and a second load terminal at the semiconductor body back side. The active region is configured to conduct a load current between the first load terminal and the second load terminal, wherein a load current density in the central volume is at least 5% lower than a load current density in the peripheral volume.

[0011] According to an embodiment, a method of processing a power semiconductor device comprises providing a power semiconductor device having an active region with at least one power cell, wherein the active region has a total volume, the total volume having: a central volume forming at least 20% of the total volume; a peripheral volume forming at least 20% of the total volume and surrounding the central volume; and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The power semiconductor device further comprises an edge termination region surrounding an edge of the outermost peripheral volume of the active region, wherein the peripheral volume has a constant lateral distance from the edge termination region; a semiconductor body having a front side and a back side, wherein the semiconductor body forms both a portion of the active region and a portion of the edge termination region; a first load terminal at the semiconductor body front side and a second load terminal at the semiconductor body back side. The method further comprises forming a first doped semiconductor region in the semiconductor body such that it is electrically connected with the first load terminal; forming a second doped semiconductor region in the semiconductor body such that it is electrically connected with the second load terminal. At least one of the first doped semiconductor region and the second doped semiconductor region has: a central portion extending into the central volume of the active region and having a central average dopant dose; a peripheral portion extending into the peripheral volume of the active region and having a peripheral average dopant dose, wherein the central average dopant dose is at least 5% lower or at least 10% lower than the peripheral average dopant dose.

[0012] According to an embodiment, a method of processing a power semiconductor device comprises: providing a power semiconductor device having: an active region having at least one power cell, wherein the active region has a total volume, the total volume having a central volume forming at least 80% of the total volume; a peripheral volume surrounding the central volume; and an edge termination region arranged outside the active region and surrounding the peripheral volume; a semiconductor body having a front side and a back side, wherein the semiconductor body forms part of each of the active region, the peripheral volume, and the edge termination region. The semiconductor body has a total thickness along a vertical direction between the front side and the back side. The peripheral volume has a lateral extension amounting to at least half of the total semiconductor body thickness. The power semiconductor device further comprises a first load terminal at the semiconductor body front side and a second load terminal at the semiconductor body back side. The method further comprises: forming a first doped semiconductor region in the semiconductor body such that it is electrically connected with the first load terminal; and forming a second doped semiconductor region in the semiconductor body such that it is electrically connected with the second load terminal. The second doped semiconductor region has: a central portion extending into the central volume of the active region and having a central average dopant dose; a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose, the peripheral average dopant dose having a negative gradient in a lateral direction towards the edge termination region along the lateral extension of the peripheral volume; and an edge portion extending into the edge termination region and having an edge average dopant dose, wherein the edge average dopant dose is lower than the central average dopant dose, e.g. by at least 5%.

[0013] Those skilled in the art will realize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0014] Portions of the figures herein can not be to scale, emphasis instead being placed on illustrating the principles of the application. In addition, in the figures, like reference numerals designate corresponding parts throughout the different views. In the drawings:

[0015] Figure 1 schematically and exemplarily illustrates a cross-section of a horizontal projection of a power semiconductor device according to one or more embodiments;

[0016] Figs. 2A-C each schematically and exemplarily illustrate a cross-section of a horizontal projection of a power semiconductor device according to one or more embodiments;

[0017] Figure 3 schematically and exemplarily illustrates a cross-section of a vertical cross-section of an active region of a power semiconductor device according to one or more embodiments;

[0018] Figs. 4A-B schematically and exemplarily illustrate the profile of the load current density and temperature along the lateral direction in a power semiconductor device according to one or more embodiments, as compared to a reference diode;

[0019] Figure 5A Fig. 4B schematically and exemplarily illustrates a cross-section of a vertical cross-section of a reference diode;

[0020] Figure 6A Fig. 5 schematically and exemplarily illustrates various vertical cross-sections of a power semiconductor device according to some embodiments, having a first doped semiconductor region with an increasing average dopant dose in a peripheral volume;

[0021] Fig. 7 schematically and exemplarily illustrates a cross-section of a vertical cross-section of a reference diode;

[0022] Fig. 8A-B schematically and exemplarily illustrate various vertical cross-sections of a power semiconductor device according to some embodiments, having a second doped semiconductor region with a decreasing average dopant dose in a peripheral volume;

[0023] Figure 9 Fig. 8B schematically and exemplarily illustrates a cross-section of a vertical cross-section of a reference diode;

[0024] Figures 10A-13 Fig. 9 schematically and exemplarily illustrates various vertical cross-sections of a power semiconductor device according to some embodiments, having a second doped semiconductor region with a decreasing average dopant dose in a peripheral volume;

[0025] Figure 14 Fig. 10 schematically and exemplarily illustrates a profile of a lateral dopant dose according to some embodiments; and

[0026] Figure 15 Fig. 11 schematically and exemplarily illustrates an implantation pattern according to some embodiments. DETAILED DESCRIPTION

[0027] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the application can be practiced. These

[0028] In this regard, directional terms such as "top," "bottom," "upper," "lower," "under," "over," "front," "back," "leading," "trailing," "above," and the like can be used with reference to the orientation of the illustrated figures. Because portions of the embodiments can be positioned in a number of different orientations, the directional terms are used for purposes of illustration and are in no way limiting. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. The following detailed description, therefore, is not to be taken in a limiting sense, as the scope of the present application is defined by the appended claims.

[0029] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation of the application and is not meant as a limitation of the application. For example, features illustrated or described as part of one embodiment, can be used with another embodiment to yield yet a further embodiment. It is intended that the present application include such modifications and variations. The particular language used herein is not intended to limit the scope of the claims. The figures are not drawn to scale and are used solely for purposes of illustration. For the purposes of clarity, not every component is called out in every drawing where it can be present. For the purposes of clarity, identical reference numerals can be used in the different drawings to denote identical, similar, or corresponding parts in different embodiments.

[0030] The term "horizontal" as used in this description is intended to describe an orientation that is substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This can be, for example, a surface of a semiconductor wafer or die or chip. For example, both a first lateral direction X and a second lateral direction Y mentioned below can be horizontal directions, where the first lateral direction X and the second lateral direction Y can be perpendicular to each other. A radial direction R mentioned below can also be lateral (i.e., horizontal), formed, for example, by an arbitrary combination (e.g., linear combination) of the first lateral direction X and the second lateral direction Y.

[0031] The term "vertical" as used in this description is intended to describe an orientation that is substantially arranged perpendicular to a horizontal surface, i.e., parallel to a normal direction of a semiconductor wafer / chip / die surface. For example, an extension direction Z mentioned below can be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as "vertical direction Z".

[0032] In this description, n-doping is referred to as "first conductivity type" and p-doping is referred to as "second conductivity type". Alternatively, an opposite doping relationship can be employed, such that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0033] In the context of the present specification, the terms "making ohmic contact", "making electrical contact", "making ohmic connection" and "being electrically connected" are intended to describe the presence of a low-ohmic electrical connection or low-ohmic current path between two regions, segments, strips, parts or portions of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a part or portion of a semiconductor device. Furthermore, in the context of the present specification, the term "making contact" is intended to describe the presence of a direct physical connection between two elements of a respective semiconductor device; for example, the transition between two elements making contact with each other can not include further intermediate elements or the like.

[0034] Furthermore, in the context of the present specification, the term "electrically insulated" is used in the context of its general effective understanding and thus is intended to describe that two or more components are positioned separately from each other and that no ohmic connection connecting those components is present. However, components being electrically insulated from each other can still be coupled to each other, for example, mechanically and / or capacitively and / or inductively. By way of example, two electrodes of a capacitor can be electrically insulated from each other and at the same time be mechanically and capacitively coupled to each other, for example, by means of an insulation such as a dielectric.

[0035] The specific embodiments described in the present specification relate to, but are not limited to, power semiconductor devices exhibiting a single cell, a bar-shaped cell, a honeycomb (which is also referred to as "needle-shaped" or "column-shaped") cell or another cell configuration, for example, a power semiconductor device that can be used within a power converter or power supply. Thus, in embodiments, the power semiconductor devices described herein can be configured to carry a load current to be fed to a load and / or to provide the load current by a power supply accordingly.

[0036] For example, the power semiconductor device can comprise one or more active power semiconductor cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell (for example, a monolithically integrated cell of two anti-serially connected diodes), a monolithically integrated transistor cell, for example, a monolithically integrated IGBT cell, a monolithically integrated RC IGBT cell, a monolithically integrated MOSFET cell, a monolithically integrated thyristor cell, a monolithically integrated gate turn-off thyristor (GTO) cell and / or a derivative thereof. Such diode / transistor cells can be integrated in a power semiconductor module. A plurality of such equally configured cells can constitute a cell field for the active region arrangement of the power semiconductor device.

[0037] The term "power semiconductor device" as used in the present specification is intended to describe a semiconductor device on a single chip with high voltage blocking and / or high current carrying capability. In other words, the power semiconductor devices described herein can be single-chip power semiconductor devices and can be intended for high currents, typically in the range of amperes of up to several tens or hundreds of amperes, and / or intended for high voltages, typically above 15 V, more typically at 100 V and above, e.g. up to at least 400 V or even higher, e.g. up to at least 3 kV, or even up to 10 kV or higher.

[0038] For example, the power semiconductor devices described herein can be single semiconductor chips exhibiting a single cell configuration, a bar cell configuration or a honeycomb cell configuration and can be configured to be employed as power components in low voltage, medium voltage and / or high voltage applications.

[0039] For example, the term "power semiconductor device" as used in the present specification is not directed to logic semiconductor devices used for storing data, computing data and / or other types of semiconductor-based data processing.

[0040] Figure 1 A cross-section of a horizontal projection of a power semiconductor device 1 according to one or more embodiments is schematically and exemplarily illustrated. The power semiconductor device 1 can be implemented based on / in a single chip. The power semiconductor device 1 can be one of a diode, an IGBT or a MOSFET, or a derivative of a diode, an IGBT or a MOSFET, for example.

[0041] The power semiconductor device 1 has an active area 1-2 with at least one power cell 1-1 (see Figs. 2A-C). The active area 1-2 has a total volume, wherein the total volume has a central volume 1-21 forming at least 20% of the total volume.

[0042] The central volume 1-21 can form up to 75% of the volume, for example. For example, the central volume 1-21 can form between 20% and 75% (but for example not more than 75%) of the total volume.

[0043] The power semiconductor device 1 has a peripheral volume 1-22 surrounding the central volume 1-21.

[0044] In some embodiments, the peripheral volume 1-22 can be entirely comprised in the active area 1-2 and form at least 20% of the total volume of the active area 1-2, for example, if the power semiconductor device 1 is a diode. For example, the peripheral volume 1-22 can form up to 50% of the total volume of the active area 1-2.

[0045] In another embodiment, the peripheral volume 1-22 can extend into both the edge termination region 1-3 and the active region 1-2, or only into the active region 1-2, or only into the edge termination region 1-3, for example, if the power semiconductor device 1 is an IGBT.

[0046] In some embodiments, for example, if the power semiconductor device 1 is a diode, the active region 1-2 can further comprise an optional outermost peripheral volume 1-23, which forms at least 5% of the total volume and surrounds the peripheral volume 1-22. For example, in these embodiments, the active region 1-2 consists of three volumes: the central volume 1-21 (e.g., forming 50% of the total volume), the peripheral volume 1-22 (e.g., forming 45% of the total volume), and the outermost peripheral volume 1-23 (e.g., forming 5% of the total volume).

[0047] The edge termination region 1-3 of the power semiconductor device 1 surrounds the peripheral volume 1-22, or respectively the outermost peripheral volume 1-23 if it is present. Thus, the edge termination region 1-3 is arranged outside of the active region 1-2. The edge termination region 1-3 is laterally terminated by an edge 1-4. The edge 1-4 can form a chip edge of the power semiconductor device 1.

[0048] The central volume 1-21 can directly adjoin the peripheral volume 1-22, and the peripheral volume 1-22 can directly adjoin the outermost peripheral volume 123 if present or respectively the edge termination region 1-3.

[0049] As used herein, the terms “edge termination region” and “active region” are both associated with the technical meaning that a skilled person typically associates with them in the context of power semiconductor devices. That is, the active region 1-2 is primarily configured for load current conduction and switching purposes, while the edge termination region 1-3 primarily implements functions with respect to reliable blocking capability, proper guidance of electric fields, sometimes also charge carrier extraction functionality, and / or further functions with respect to protection and proper termination of the active region 1-2.

[0050] For example, the boundary of the active area 1-2 is defined by the lateral boundary of the outermost power cell(s) 1-1. For example, in case of a diode, this lateral boundary can be identical to the lateral boundary of the first load terminal 11 (see below for a more detailed explanation). In case of a multi-cell IGBT, this lateral boundary can be defined by the outermost source region(s) 109 (see below for a more detailed explanation). For example, all functional elements enabling the conduction of a load current are present in the vertical projection of the active area 1-2 of the power semiconductor device 1, which functional elements for example comprise at least the first load terminal (e.g. its front side metal contact), the anode / body region, the drift region, the backside emitter and the second load terminal 12 (e.g. its backside metal).

[0051] As will be explained in more detail below, the structure of the central volume 1-21 of the active area 1-2 can be different from the structure of the peripheral volume 1-22 and from the structure of the outermost peripheral volume 1-23 (if it exists).

[0052] In embodiments, the central volume 1-21 and the peripheral volume 1-22 (and, if it exists, the outermost peripheral volume 1-23) are for example symmetrically arranged with respect to a central vertical axis 1-0 of the power semiconductor device 1 to each other. Further, the edge termination area 1-3 and the active area 1-2 can for example be symmetrically arranged with respect to the central vertical axis 1-0 of the power semiconductor device 1 to each other, as it is exemplarily illustrated in Figure 1 .

[0053] Further, according to embodiments, the lateral transition between the central volume 1-21 and the peripheral volume 1-22 can exclusively extend along the vertical direction Z. Also, the lateral transition between the active area 1-2 and the edge termination area 1-3 can exclusively extend along the vertical direction Z. Further, the lateral transition between the peripheral volume 1-22 and the outermost peripheral volume 1-23 (if it exists) can exclusively extend along the vertical direction Z.

[0054] For example, the peripheral volume 1-22 (when it exclusively forms a part of the active area 1-2) can have a constant lateral distance to the edge termination area 1-3. In embodiments, as illustrated in Figure 1 , said constant lateral distance to the edge termination area 1-3 is filled with or respectively formed by the outermost peripheral volume 1-23.

[0055] With reference to Figs. 2A-C, it is to be understood that the cell configuration of the active region 1-2 can be arbitrarily chosen. In one embodiment (Fig. 2A), the active region 1-2 has a plurality of power cells 1-1 configured as strip cells arranged next to each other, e.g., along a first lateral direction X. Such a configuration can for example be applied to form an IGBT, e.g., an IGBT with a micro-pattern trench (MPT) configuration. In another embodiment (Fig. 2B), the active region 1-2 has a plurality of power cells 1-1 configured as pillar / needle cells arranged next to each other, e.g., according to a grid pattern. Such a configuration can for example be applied to form a MOSFET. In yet another embodiment (Fig. 2C), the active region 1-2 has only one power cell 1-1. Such a configuration can for example be applied to form a diode. Figure 2C

[0056] Figure 3 Fig. 2A schematically and exemplarily illustrates a cross-section of a vertical cross-section of the active region 1-2 of the power semiconductor device 1 according to one or more embodiments. With reference to the foregoing description of one of Figs. 2A-C, the same can equally apply to the embodiment illustrated in Figure 1 Fig. 2D. Figure 3

[0057] The power semiconductor device 1 has a semiconductor body 10 with a front side 110 and a back side 120. The front side 110 and the back side 120 can vertically terminate the semiconductor body 10. That is, the semiconductor body 10 has a total thickness along the vertical direction Z between the front side 110 and the back side 120. In lateral directions, the semiconductor body 10 can be terminated by edges 1-4 (not illustrated in Figure 3 Fig. 2D).

[0058] Here, it is to be noted that the peripheral volume 1-22 can have a lateral extension that amounts to at least half of the total semiconductor body thickness, or even more than the total semiconductor body thickness. Moreover, in contrast to the schematic illustration in Figure 3 , it is to be emphasized again that in some embodiments, the peripheral volume 1-22 is not entirely comprised in the active region 1-2, but can also or exclusively extend into the edge termination region 1-3. In other embodiments, the peripheral volume 1-22 is entirely comprised in the active region 1-2 (as illustrated in Figure 3 Fig. 2A), and the active region 1-2 can in addition comprise an outermost peripheral region 1-23 (as not illustrated in Figure 3 Fig. 2B).

[0059] ​​The semiconductor body 10 forms a part of each of the active region 1-2, the peripheral volume 1-22, and the edge termination region 1-3. The semiconductor body 10 is configured to conduct a load current between the first load terminal 11 and the second load terminal 12 in the active region 1-2. For example, the above-mentioned cell configuration of the power cell(s) is mainly implemented in the semiconductor body 10. The first load terminal 11 is arranged at the semiconductor body front side 110, and the second load terminal 12 is arranged at the semiconductor body back side 120. For example, the first load terminal 11 comprises a front side metallization, and / or the second load terminal 12 comprises a back side metallization.

[0060] For example, the power semiconductor device 1 can have an IGBT configuration. Then, the first load terminal 11 can be an emitter terminal, and the second load terminal 12 can be a collector terminal. In another embodiment, the power semiconductor device 1 has a MOSFET configuration. Then, the first load terminal 11 can be a source terminal, and the second load terminal 12 can be a drain terminal. In yet another embodiment, the power semiconductor device 1 has a diode configuration. Then, the first load terminal 11 can be an anode terminal, and the second load terminal 12 can be a cathode terminal.

[0061] In an embodiment, the first load terminal 11 (e.g., the front side metallization) laterally overlaps the active region 1-2, i.e., along the first lateral direction X and / or the second lateral direction Y and / or a combination thereof (see radial directions R in Figure 1 In an embodiment, the first load terminal 11 can form both a part of the central volume 1-21 and a part of the peripheral volume 1-22 of the active region 1-2, e.g., if the peripheral volume 1-22 is at least partially comprised in the active region 1-2. For example, the first load terminal 11 (e.g., the front side metallization) laterally overlaps at least 80%, or even 100% of the total lateral extension of the peripheral volume 1-22. For example, as illustrated in Figure 3 In an embodiment, the first load terminal 11 (e.g., the front side metallization) laterally overlaps the active region 1-2, i.e., along the first lateral direction X and / or the second lateral direction Y and / or a combination thereof (see radial directions R in

[0062] At this point, it should be made clear again that in other embodiments, the peripheral volume 1-22 can not be included in or only partially included in the active area 1-2. For example, if the peripheral volume 1-22 does not extend into the active area 1-2, but only in the edge termination area 1-3, there can also be no overlap between the first load terminal 11 and the peripheral volume 1-22.

[0063] Similarly, in embodiments, the second load terminal 12 (e.g. the backside metallization) laterally overlaps the active area 1-2, i.e. along the first lateral direction X and / or the second lateral direction Y and / or a combination thereof (see Figure 1 the radial direction R in ). In embodiments, the second load terminal 12 can form both a portion of the central volume 1-21 and a portion of the peripheral volume 1-22 of the active area 1-2. For example, the second load terminal 12 (e.g. the backside metallization) laterally overlaps at least 80% of the peripheral volume 1-22, or even 100% of the total lateral extension of the peripheral volume 1-22. For example, as illustrated in Figure 3 , the second load terminal 12 (e.g. the backside metallization) completely laterally overlaps the peripheral volume 1-22. It should be noted that the second load terminal 12 is typically not structured, but formed homogenously and monolithically at the semiconductor backside 120, e.g. in order to establish a laterally homogenous contact with the semiconductor body 10. Such a homogenous structure can also be implemented in the area where the second load terminal 12 laterally overlaps the peripheral volume 1-22.

[0064] Still referring to Figure 3 , it should be understood that in some embodiments, as explained above, the total volume of the active area 1-2 can be terminated by an outermost peripheral volume 1-23, which is not illustrated in Figure 3 .

[0065] The power semiconductor device 1 further comprises a first doped semiconductor region 101 formed in the semiconductor body 10 and electrically connected with the first load terminal 11, and a second doped semiconductor region 102 formed in the semiconductor body 10 and electrically connected with the second load terminal 12. For example, the first doped semiconductor region 101 is separated from the second doped semiconductor region 102 along the vertical direction Z at least by means of the semiconductor drift region 100.

[0066] The total extension of the drift region 100 in the vertical direction Z can be at least four times (or even at least ten times) larger than the maximum extension of the first doped semiconductor region 101 in the vertical direction Z, and / or at least four times (or even at least ten times) larger than the maximum extension of the second doped semiconductor region 102 in the vertical direction Z.

[0067] For example, the first doped semiconductor region 101 forms a front-side emitter region of the power semiconductor device 1.

[0068] Further, the second doped semiconductor region 102 can form a back-side emitter region of the power semiconductor device 1.

[0069] In an embodiment, the first doped semiconductor region 101 continuously extends into both the peripheral volume 1-22 and the central volume 1-21. Additionally or alternatively, the second doped semiconductor region 102 can continuously extend into both the peripheral volume 1-22 and the central volume 1-21.

[0070] According to one or more embodiments, in a vertical cross-section, the first load terminal 11 and the first doped semiconductor region 101 can laterally overlap each other, and / or a transition along the vertical direction Z between the first load terminal 11 and the first doped semiconductor region 101 is electrically conductive along at least 75% of a total lateral extension of the peripheral volume 1-22. Additionally or alternatively, in said vertical cross-section, the second load terminal 12 and the second doped semiconductor region 102 can laterally overlap each other, and / or a transition along the vertical direction Z between the second load terminal 12 and the second doped semiconductor region 102 is electrically conductive along at least 75% of a total lateral extension of the peripheral volume 1-22.

[0071] Both the first doped semiconductor region 101 and the second doped semiconductor region 102 can be configured to contribute to a path of a load current of the power semiconductor device. For example, during a conducting state of the power semiconductor device 1, in which a load current is conducted between the first load terminal 11 and the second load terminal 12, both the first doped semiconductor region 101 and the second doped semiconductor region 102 contribute to maintaining a high charge carrier concentration in the semiconductor body 10, which results in low conduction losses.

[0072] For example, the power semiconductor device 1 can have an IGBT configuration. Then, the first doped semiconductor region 101 can be a body region of, for example, a second conductivity type, e.g., a “p-emitter”, (or a source region of, for example, a first conductivity type, e.g., an “n-emitter”), and the second doped semiconductor region 102 can be a collector region of, for example, the second conductivity type, e.g., a “p-emitter”.

[0073] In another embodiment, the power semiconductor device 1 has a MOSFET configuration. Then, the first doped semiconductor region 101 can be a body region of, for example, a second conductivity type, e.g., a “p-emitter”, (or a source region of, for example, a first conductivity type, e.g., an “n-emitter”), and the second doped semiconductor region 102 can be a drain region of, for example, the first conductivity type, e.g., a further “n-emitter”.

[0074] In yet another embodiment, the power semiconductor device 1 has a diode configuration. Thus, the first doped semiconductor region 101 can be, for example, an anode region of the second conductivity type, e.g., a "p-emitter", and the second doped semiconductor region 102 can be, for example, a cathode region of the first conductivity type, e.g., an "n-emitter". Combinations thereof are also possible, e.g., in order to design a semiconductor device having an RC-IGBT configuration.

[0075] Still referring to Figure 8B According to embodiments, at least one of the first doped semiconductor region 101 and the second doped semiconductor region 102 has (i.e., either the first or the second doped semiconductor region, or both the first and the second doped semiconductor region):

[0076] - a central portion 101-21; 102-21, which extends into a central volume 1-21 of the active region 1-2, and has a central average dopant, and a peripheral portion 101-22; and

[0077] - a peripheral portion 101-22; 102-22, which extends into a peripheral volume 1-22, and has a peripheral average dopant dose.

[0078] For example, the central portion 101-21 of the first doped semiconductor region 101 has the same total lateral extension as the central volume 1-21 of the active region 1-2. Further, the central portion 102-21 of the second doped semiconductor region 102 can also have the same total lateral extension as the central volume 1-21 of the active region 1-2. It is thus to be understood that, according to the embodiments described herein, the central portion 101-21 / 102-21 (of the first doped semiconductor region 101 and / or of the second doped semiconductor region 102) extends along the vertical direction Z into the central volume 1-21 of the active region 1-2. For example, the central portion 101-21 / 102-21 does not laterally extend beyond the boundaries of the central volume 1-21.

[0079] Correspondingly, the peripheral portion 101-22 of the first doped semiconductor region 101 can have the same total lateral extension as the peripheral volume 1-22. The peripheral portion 102-22 of the second doped semiconductor region 102 can also have the same total lateral extension as the peripheral volume 1-22.

[0080] It should be clear from the previous paragraph that, according to some or all of the embodiments described herein, the first doped semiconductor region 101 can extend continuously into the entire active region 1-2, e.g. can extend continuously along the entire lateral extension of both the central volume 1-21 (where its central portion 101-21 is formed) and the peripheral volume 1-22 (where its peripheral portion 101-22 is formed). The same applies to the second doped semiconductor region 102, which according to some or all of the embodiments described herein can extend continuously into the entire active region 1-2, e.g. can extend continuously along the entire lateral extension of both the central volume 1-21 (where its central portion 102-21 is formed) and the peripheral volume 1-22 (where its peripheral portion 102-22 is formed).

[0081] In embodiments described herein, the central average dopant dose can differ from the peripheral average dopant dose by at least 5%, at least 10%, at least 20% or even more than 50%.

[0082] In particular, in embodiments in which the active region 1-2 comprises the entire peripheral volume 1-22 and the outermost peripheral volume 1-23 (e.g. when the power semiconductor device 1 is a diode), and in which the peripheral volume 1-22 forms at least 20% of the total volume of the active region 1-2, and in which the outermost peripheral volume 1-23 forms at least 5% of the total volume of the active region 1-2, the central average dopant dose can be at least 5%, at least 10%, at least 30% or even at least 50% lower than the peripheral average dopant dose.

[0083] As explained above, in embodiments, the central portion 101-21 of the first doped semiconductor region 101 is not separated (not spaced apart) from its peripheral portion 101-22. Also, in embodiments, the central portion 102-21 of the second doped semiconductor region 102 is not separated (not spaced apart) from its peripheral portion 102-22. Rather, both portions can form the respective continuous semiconductor region 101; 102. This can similarly apply if, for example, the second semiconductor region 102 is laterally structured, e.g. formed by means of a plurality of local emitters (as Figure 4B It should be understood, however, that according to embodiments, both the central portion 101-21 and the peripheral portion 101-22 of the first doped semiconductor region 101 are electrically connected to the first load terminal 11, and according to embodiments, both the central portion 102-21 and the peripheral portion 102-22 of the second doped semiconductor region 102 are electrically connected to the second load terminal 12.

[0084] According to one or more embodiments, an appropriate selection of differences in the average dopant dosage allows to design the power semiconductor device 1 with a defined distribution of the spatial load current density, and thus also with a corresponding defined spatial temperature distribution. For example, by increasing the average dopant dosage in the peripheral volume(s) 101-22; 102-22, it is possible to direct a larger portion of the load current within the peripheral volume 1-22, thereby reducing the risk of generating a hot spot within the central volume 1-21.

[0085] For example, in embodiments (and independently of the final differences in the average dopant dosage), the active region 1-2 is configured to conduct a load current between the first load terminal 11 and the second load terminal 12, wherein the load current density in the central volume 1-21 is at least 5%, at least 10% or at least 15% lower than the load current density in the peripheral volume 1-22. In addition to or as an alternative to the above-mentioned differences in the average dopant dosage, this can be achieved by correspondingly configuring the first load terminal 11 and / or the second load terminal 12. For example, by means of the load terminal structure, it is possible to laterally structure the electrical resistance between the semiconductor body 10 and the load terminal(s). For example, in order to increase the load current density in the peripheral volume 1-22, the transition between the first load terminal 11 and the semiconductor body 10 in the peripheral volume 1-22 has a reduced electrical resistance, and / or the transition between the first load terminal 11 and the semiconductor body 10 in the central volume 1-21 has an increased electrical resistance.

[0086] Herein, the respective dopant dosage of the first and second doped semiconductor regions 101, 102 can be defined by the dopant concentration integrated along a vertical direction Z, for example pointing from the first load terminal 11 to the second load terminal 12. For example, the respective average dopant dosage is defined by the dopant dosage averaged over a distance of at least 10 pm in at least one of the lateral directions R; X; Y, which are perpendicular to the vertical direction Z and point from the central volume 1-21 to the edge termination region 1-3. It is even possible to define the respective average dopant dosage by the dopant dosage averaged over a volume along the total lateral extension of the respective region, or respectively the lateral directions R; X; Y. Of course, for comparison purposes, according to one or more embodiments, the average dopant dosage in the peripheral portion 101-22; 102-22 is determined at the same vertical level and along the same lateral directions as in the central portion 101-21; 102-21. Similar definitions can apply with respect to the edge portion 102-23 further mentioned below.

[0087] Furthermore, both the terms "central average dopant dose" and "peripheral average dopant dose" (as well as the "edge average dopant dose" mentioned below) refer to electrically active dopants of the same conductivity type. Thus, a change in the average dopant dose can also be achieved by keeping the dose of one dopant type constant in both portions and by applying counter-doping and / or damage doping. Also by this means, a difference between the (net) average dopant doses can be obtained.

[0088] Furthermore, it is to be understood that the integration path according to which the average dopant dose is determined does not extend beyond the border of the first doped semiconductor region 101 or, respectively, the second doped semiconductor region 102. For example, with respect to the first doped semiconductor region 101, the integration path terminates at the latest at the place where the first doped semiconductor region 101 (e.g. a p-type emitter) forms a pn-junction with the drift region 100 (e.g. an n- drift region). Also with respect to the second doped semiconductor region 102, the integration path terminates at the latest at the place where the second doped semiconductor region 102 (e.g. a p-type emitter in the case of an IGBT / RC-IGBT) forms a pn-junction with the drift region 100 (e.g. an n- drift region) or, respectively, with a field stop region (not shown) which can be arranged between the drift region 100 and the second doped semiconductor region 102. In case the second doped semiconductor region 102 has the same conductivity type as the drift region 100 (e.g. in case the power semiconductor device 1 is a diode or a MOSFET), the average dopant dose in the peripheral volume 1-22 does not differ from the average dopant dose in the central volume 1-21 at some point with respect to the vertical direction Z, since the drift region 100 extends into both volume portions 1-21, 1-22 without a change in the dopant dose.

[0089] Thus, according to some or all of the embodiments described herein, the respective dopant dose can be defined by the dopant concentration which is integrated along the vertical direction Z pointing from the first load terminal 11 to the second load terminal 12 and in a cross-section close to the respective load terminal 11; 12. For example, the average dopant dose of the second doped semiconductor region 102 is determined in a layer of the second doped semiconductor region 102 which is less than 5 pm thick along the vertical direction Z and which is spaced apart from the second load terminal 12 by not more than 2 pm along the vertical direction Z, and, for example, the average dopant dose of the first doped semiconductor region 101 is determined in a layer of the first doped semiconductor region 101 which is less than 30 pm thick along the vertical direction Z and which is spaced apart from the first load terminal 11 by not more than 2 pm along the vertical direction Z.

[0090] Various options for designing a power semiconductor device 1 having a specific spatial load current / temperature distribution will now be discussed with respect to the remaining figures.

[0091] For example, with reference to Figures 4A-B, both of which relate to embodiments in which the power semiconductor device 1 is implemented as a diode (and accordingly, the first doped semiconductor region 101 is an anode region, and the second doped semiconductor region 102 is a cathode region), the peripheral average dopant dosage of the second doped semiconductor region 102 is greater than the central average dopant dosage of the second doped semiconductor region 102, e.g., the central average dopant dosage is at least 5%, or at least 10%, or at least 50% lower than the peripheral average dopant dosage. That is, in embodiments, the peripheral average dopant dosage can be twice as large as the central average dopant dosage.

[0092] Figures 4A and Figure 4B illustrate the spatial load current density (Figure 4A) and the spatial temperature distribution (Figure 4B) along the first lateral direction X for a diode according to the embodiments explained in the preceding paragraphs. Figure 4B The dashed line refers to a reference diode, which does not exhibit the difference between the central average dopant dosage and the peripheral average dopant dosage described herein, but rather exhibits a cathode region that is homogenously doped with respect to both the active volume and the peripheral volume. Figures 4A and Figure 4B The solid line in both Figures refers to the embodiments explained in the preceding paragraphs. Thus, with reference to Figure 4A, the reference diode has a load current density that does not substantially change in dosage at the transition between the central volume 1-21 and the peripheral volume 1-22 (due to the homogenously doped cathode), but only changes in dosage in the vicinity of the transition between the active region 1-2 and the edge termination region 1-3. This quasi-homogenous load current density in the active region of the reference diode is correspondingly reflected by the temperature distribution (Figure 4B), which has a sharp peak in the central volume of the reference diode. Figure 1 In contrast, such a high peak in the central volume 1-21 of the active region 1-2 of the diode according to this embodiment is avoided by the increased average dopant dosage in the peripheral portion 102-22 of the second doped semiconductor region 102. This increased dopant dosage can even result in an increased load current density in the peripheral volume 1-22 as compared to the load current density in the central volume 1-21.

[0093] In the outermost peripheral volume 1-23, which can separate the peripheral volume from the edge termination region 1-3, the dopant dosage of the second doped semiconductor region 102 can again be decreased, which is reflected by a decrease in the load current density (Figure 4A). For example, various designs are possible for the dopant dosage of the second doped semiconductor region 102 in the outermost peripheral volume 1-23, e.g., to implement an HDR (high dynamic robustness) concept, etc. For example, some designs also provide for an increased (rather than decreased) dopant dosage of the second doped semiconductor region 102 in the outermost peripheral volume 1-23.

[0094] Fig. 4A-B further schematically illustrates both the central vertical axis 1-0 (see also Fig. 1A) of the active region 1-2 and the orientation of the cut line, wherein the edge 1-4 of the edge termination region 1-3 (i.e. the edge of the semiconductor body 10) can be covered by means of a protective material such as a module gel 1-5. Figure 5A

[0095] Figure 6A The cross-section schematically and exemplarily illustrates a vertical cross-section of a reference diode. Depending on the design of the reference diode, the first doped semiconductor region 101 (e.g. a p-doped anode region) is homogenously doped along the first lateral direction X within the active region 1-2, i.e. without any change between the central volume 1-21 and the peripheral volume 1-22. However, depending on the chosen design option, the dopant dose can (or can not) change in the outermost peripheral volume 1-23. The outermost peripheral volume 1-23 is currently of less interest.

[0096] Still referring to the design of the reference diode, with the beginning of the edge termination region 1-3, the first doped semiconductor region 101 can seamlessly join into a third doped semiconductor region 103, which can have the same conductivity type as the first doped semiconductor region 101 (in the illustrated example: also p-doped) and / or which can have a VLD (laterally doped variation) structure along the first lateral direction X (and of course also along the other lateral directions Y and R). The third doped semiconductor region 103 can also be electrically connected with the first load terminal 11, but as illustrated is mainly covered by means of the insulating structure 13. The third doped semiconductor region 103 can extend along the front side 110 within the edge termination region 1-3.

[0097] Figure 6A - D schematically and exemplarily illustrates various vertical cross-sections of a power semiconductor device 1 according to some embodiments, wherein the central average dopant dose of the first doped semiconductor region 101 differs from the average peripheral dopant dose by at least -5%, i.e. is an embodiment wherein the peripheral average dopant dose of the first doped semiconductor region 101 is significantly increased compared to its central average dopant dose.

[0098] In Figure 2C In the example illustrated in - D, the power semiconductor device 1 can be a diode, e.g. having a single power cell 1-1 (see Fig. 4A) in the active region 1-2. Figure 6A The first doped semiconductor region 101 can be a p-doped anode region. The second doped semiconductor region 102 (not illustrated) can be an n-doped cathode region, which as Figure 6A ​- the first doped semiconductor region 101 is homogenously doped along the lateral directions X, Y, R in the active region 1-2 as illustrated in -D, or as illustrated in Figs. 8A-B.

[0099] In embodiments, the first doped semiconductor region 101 comprises a central portion 101-21 which extends, for example, exclusively within a central volume 1-21, and which may, for example, be arranged there in contact with the first load terminal 11. The first doped semiconductor region 101 further comprises a peripheral portion 101-22 which extends, for example, exclusively within a peripheral volume 1-22, and which may, for example, be arranged there in contact with the first load terminal 11. The first doped semiconductor region 101 can further comprise a portion which extends within an outermost peripheral volume 1-23, and which may, for example, be at least partially arranged there in contact with the first load terminal 11.

[0100] According to Figure 6A - the embodiment illustrated in -D, the active region 1-2 comprises a peripheral volume 1-22 and an outermost peripheral volume 1-23. The outermost peripheral volume 1-23, which forms at least 5% of the total volume of the active region 1-2, is arranged between the peripheral volume 1-22 and the edge termination region 1-3. As illustrated, the transition between the active region 1-2 (i.e. its outermost peripheral volume 1-23) and the edge termination region 1-3 can be formed at the lateral border of the contact between the first load terminal 11 and the semiconductor body 10.

[0101] For example, according to Figure 6A the embodiment illustrated in -D, the increased average dopant dosage of the first doped semiconductor region 101 in the peripheral volume 1-22 is achieved by “conventionally” producing the first doped semiconductor region 101 (e.g. in the way as it is produced for the reference diode) and by means of an additional implantation process step and added photographic / lithographic techniques as illustrated for producing the complementary doped semiconductor portion 105 in the peripheral volume 1-22. For example, due to the complementary doped semiconductor portion 105, an increased emitter functionality is achieved for the peripheral portion 101-22 of the first doped semiconductor region 101 in the peripheral volume 1-22, thereby increasing the current density in the peripheral volume 1-22.

[0102] With regard to Figure 1 all embodiments of -D, it is to be understood that the illustrated dopant profile can equally exist throughout the entire peripheral volume 1-22 (cf. the embodiment illustrated in -D), for example, creating a ring-like structure in horizontal projection. Figure 6C

[0103] ​According to the embodiment illustrated in Fig. 6B, the increased average dopant dosage of the first doped semiconductor region 101 in the peripheral volume 1-22 is achieved by “unconventionally” creating the first doped semiconductor region 101, such that the first doped semiconductor region 101 has a VLD structure in the peripheral volume 1-22 of the active region 1-2, which is, for example, a VLD structure according to which the dopant dosage increases in direction towards the edge termination region 1-3. Such an increase in the average dopant dosage can be reflected by the peripheral portion 101-22 extending somewhat further along the vertical direction Z compared to the central portion 101-21.

[0104] According to the embodiment illustrated in Fig. 6B, the increased average dopant dosage of the first doped semiconductor region 101 in the peripheral volume 1-22 is achieved by “unconventionally” creating the first doped semiconductor region 101, such that the first doped semiconductor region 101 has a VLD structure in the peripheral volume 1-22 of the active region 1-2, which is, for example, a VLD structure according to which the dopant dosage increases in direction towards the edge termination region 1-3. Such an increase in the average dopant dosage can be reflected by the peripheral portion 101-22 extending somewhat further along the vertical direction Z compared to the central portion 101-21. Figure 5A According to the embodiment illustrated in Fig. 6B, the increased average dopant dosage of the first doped semiconductor region 101 in the peripheral volume 1-22 is achieved by “unconventionally” creating the first doped semiconductor region 101, such that the first doped semiconductor region 101 has a VLD structure in the peripheral volume 1-22 of the active region 1-2, which is, for example, a VLD structure according to which the dopant dosage increases in direction towards the edge termination region 1-3. Such an increase in the average dopant dosage can be reflected by the peripheral portion 101-22 extending somewhat further along the vertical direction Z compared to the central portion 101-21.

[0105] Fig. 5B schematically and exemplarily illustrates a further cross-section of a vertical cross-section of a reference diode, which mainly corresponds to the example shown in Fig. 5A, but in which an additional doped semiconductor region 107 is provided. This additional doped semiconductor region 107 can have the same conductivity type as the first doped semiconductor region 101 (e.g. p-doped) and is arranged at the transition between the active region 1-2 and the edge termination region 1-3, such that it extends at least into the outermost peripheral volume 1-23, e.g. into both the first and the third doped semiconductor region 101, 103. For example, within the outermost peripheral volume 1-23, the first doped semiconductor region 101 seamlessly joins into the additional doped semiconductor region 107 and then seamlessly joins into the third doped semiconductor region 103 within the edge termination region 1-3, which can have the same conductivity type as the first doped semiconductor region 101 (also p-doped in the illustrated example) and / or can have a VLD structure along the lateral directions as explained above. Figure 6D Fig. 5B schematically and exemplarily illustrates a further cross-section of a vertical cross-section of a reference diode, which mainly corresponds to the example shown in Fig. 5A, but in which an additional doped semiconductor region 107 is provided. This additional doped semiconductor region 107 can have the same conductivity type as the first doped semiconductor region 101 (e.g. p-doped) and is arranged at the transition between the active region 1-2 and the edge termination region 1-3, such that it extends at least into the outermost peripheral volume 1-23, e.g. into both the first and the third doped semiconductor region 101, 103. For example, within the outermost peripheral volume 1-23, the first doped semiconductor region 101 seamlessly joins into the additional doped semiconductor region 107 and then seamlessly joins into the third doped semiconductor region 103 within the edge termination region 1-3, which can have the same conductivity type as the first doped semiconductor region 101 (also p-doped in the illustrated example) and / or can have a VLD structure along the lateral directions as explained above.

[0106] Based on the reference design illustrated in Fig. 5B, for example, according to Figure 15 the embodiment illustrated in Fig. 5B, an increased dopant dosage of the first doped semiconductor region 101 in the peripheral volume 1-22 can be achieved by extending the mask used to form the additional doped semiconductor region 107 into the active region 1-2 and providing mask openings of varying size (e.g., with a larger size than Figure 6A the concept of providing a reduced dopant dosage in the peripheral volume 1-22) contrary to the embodiment illustrated in Fig. 5B.

[0107] With respect to Figs. 7 and 8A-B, further options for providing a central average dopant dosage that is at least 5% lower than the peripheral average dopant dosage will be explained, wherein these further options can be combined with the designs explained based on Figure 6A Figs. 5A-D. Thus, what has been stated with respect to Figure 2C Figs. 5A-D can equally apply to the embodiments illustrated in Figs. 8A-B.

[0108] Referring first to Fig. 7, which schematically and exemplarily illustrates a cross-section of a vertical cross-section of a reference diode, it can be seen that, generally within the active region 1-2, the structure of the first doped semiconductor region 101 and the second doped semiconductor region 102 in the central volume 1-21 is not different from the structure of the first doped semiconductor region 101 and the second doped semiconductor region 102 in the peripheral volume 1-22. Generally, a difference in structure is observed at the transition from the active region 1-2 to the edge termination region 1-3, e.g. sometimes already in the outermost peripheral volume 1-23. As explained above, the first doped semiconductor region 101 can there join into said third doped semiconductor region 103, which has a different average dopant dosage than the first doped semiconductor region 101. In a similar manner, the second doped semiconductor region 102 can join at said transition into a fourth doped semiconductor region 104, which can have the same conductivity type as the second doped semiconductor region and / or which can also be electrically connected to the second load terminal 12. However, in some known reference diode implementations based on a so-called high dynamic robustness (HDR) concept, the fourth doped semiconductor region 104 is not provided in the edge termination region 1-3, or respectively at least not electrically connected to the second load terminal 12, in order to avoid an extension of the cathode function from the active region 1-2 into the edge termination region 1-3. This concept can have been implemented at least partially within the outermost peripheral volume 1-23. To illustrate this option, the fourth doped semiconductor region 104 is illustrated by means of a dashed line. That is: Since the omission of the fourth doped semiconductor region 104 can have started already within the outermost peripheral volume 1-23 of the active region 1-2 near the edge termination region 1-3, the peripheral average dopant dosage in the outermost peripheral volume 1-23 can even be reduced compared to the central average dopant dosage in the central volume 1-21 of the active region 1-1, depending on the design of the reference diode.

[0109] Also according to the example illustrated in Figs. 8A-B, the power semiconductor device 1 can be a diode, e.g. having a single power cell 1-1 (cf. Fig. 8A) in the active region 1-2. The first doped semiconductor region 101 can be a p-doped anode region, which is either (as illustrated) homogenously doped along the lateral directions X, Y, R in the active region 1-2, or respectively inhomogeneously doped along the lateral directions X, Y, R in the active region 1-2, e.g. in one of the ways as described above with respect to Fig. 7-D. The second doped semiconductor region 102 can be an n-doped cathode region, which is inhomogeneously doped along the lateral directions X, Y, R in the active region 1-2, as will now be explained with respect to Figs. 8A-B. Figure 6A Figure 1

[0110] ​​In embodiments, the second doped semiconductor region 102 comprises a central portion 102-21 which, for example, extends exclusively within the central volume 1-22 and which, for example, can be arranged there in contact with the second load terminal 12. The second doped semiconductor region 102 further comprises a peripheral portion 102-22 which, for example, extends exclusively within the peripheral volume 1-22 and which, for example, can be arranged there in contact with the second load terminal 12. The second doped semiconductor region 102 can further comprise a portion which extends within the outermost peripheral volume 1-23 and which, for example, can be at least partially arranged there in contact with the second load terminal 12.

[0111] According to the embodiment illustrated in Figs. 8A-B, the active region 1-2 comprises a peripheral volume 1-22 and an outermost peripheral volume 1-23. The outermost peripheral volume 1-23 which forms at least 5% of the total volume of the active region 1-2 is arranged between the peripheral volume 1-22 and the edge termination region 1-3. As illustrated, the transition between the active region 1-2, i.e. its outermost peripheral volume 1-23, and the edge termination region 1-3 can be formed at the lateral border of the contact between the first load terminal 11 and the semiconductor body 10.

[0112] For example, according to the embodiment illustrated in Fig. 8A, the increased average dopant dose of the second doped semiconductor region 102 in the peripheral volume 1-22 is achieved by applying an implantation process step, for example, in a similar manner as compared to the implementation of the HDR concept, for example, using a backside photography technique. The peripheral portion 102-22 of the second doped semiconductor region 102 can exhibit a dopant profile along the first lateral direction X as a VLD.

[0113] With respect to the embodiments of Figs. 8A-B, it is to be understood that the illustrated and described dopant profiles can equally exist throughout the entire peripheral volume 1-22 (see Figure 8B ), for example, resulting in a ring-like structure in a horizontal projection.

[0114] Reference is now made to the embodiment illustrated in Figure 8B , the increased average dopant dose of the second doped semiconductor region 102 in the peripheral volume 1-22 can be achieved by modifying the mask layout for the peripheral volume 1-22, for example, due to an increased density of mask openings, thereby achieving a greater density of local emitters. Here, it is to be noted that the second doped semiconductor region 102 does not necessarily extend monolithically within the active volume 1-21 and / or within the peripheral volume 1-22. Rather, as Figure 4BAs illustrated in the center, the second doped semiconductor region 102 can also be laterally configured within the central volume 1-21 and / or within the peripheral volume 1-22, e.g. because the second doped semiconductor region 102 comprises a plurality of local emitters spaced apart from each other along one or more of the lateral directions X, Y and R. For example, at least one of a density and / or size of such local emitters can be increased in the peripheral volume 1-22 (as compared to the central volume 1-21) in order to achieve said negative difference of at least 5% between the central average dopant dose of the second doped semiconductor region 102 and the peripheral average dopant dose of the second doped semiconductor region 102. It is thus to be further understood that the second doped semiconductor region 102 does not necessarily seamlessly join into the fourth doped semiconductor region 104.

[0115] In the embodiments described above with respect to Figs. 4A-8B, the central average dopant dose of the first doped semiconductor region 101 and / or of the second doped semiconductor region 102 is lower as compared to the peripheral average dopant dose of the first doped semiconductor region 101 and / or of the respective second doped semiconductor region 102. As explained, such difference of the average dopant dose(s) can result in an increased load current density in the peripheral volume 1-22, which in turn can result in a more homogeneous temperature distribution within the overall volume of the active region 1-2, e.g. avoiding (significant) temperature spikes within the center of the active region 1-2 (see Figures 9 to 15 ).

[0116] Furthermore, the embodiments described above with respect to Figs. 4A-8B have been explained exemplarily with respect to diodes. However, it is to be understood that these embodiments can equally be implemented in case the power semiconductor device 1 is an IGBT or a MOSFET, e.g., in which case the first doped semiconductor region 101 would be a p-body region at the front side of the semiconductor body of the IGBT or of the respective MOSFET, and / or in which case the second doped semiconductor region 102 can be a p-emitter at the back side of the semiconductor body of the IGBT or a n-emitter at the back side of the semiconductor body of the respective MOSFET.

[0117] According to embodiments described in the following with respect to Figures 9 to 15 the central average dopant dose of the second doped semiconductor region 102 (which is electrically connected with the second load terminal 12 at the semiconductor body back side 120) can be greater as compared to the peripheral average dopant dose of the second doped semiconductor region 102. For example, such configuration can increase the reliability of the device if the remaining design of the device can tolerate eventual temperature spikes within the center of the active region 1-2 and / or if other means (e.g. dedicated cooling means) are provided to avoid such temperature spikes.

[0118] It should be made clear, however, that both design variants - namely those described above with respect to Figs. 4A-8B and those described below with respect to Figure 9 - can be combined with each other, i.e. be implemented simultaneously.

[0119] According to the following embodiments, the reduced average dopant dosage in the peripheral volume 1-22 will be exemplarily described with respect to the second doped semiconductor region 102.

[0120] Similar to Fig. 7, Figures 10A to 15 schematically and exemplarily illustrates a cross-section of a vertical cross-section of a reference diode or, respectively, of an IGBT. As illustrated, in the peripheral volume 1-22, the second doped semiconductor region 102 seamlessly joins into a fourth doped semiconductor region 104 near the transition between the active region 1-2 and the edge termination region 1-3, wherein the fourth doped semiconductor region 104 has the same conductivity type as the second doped semiconductor region 102 and extends along the backside 120 within the edge termination region 1-3. As already explained above, the fourth doped semiconductor region 104 can exhibit a significantly smaller average dopant dosage compared to the average dopant dosage of the second doped semiconductor region 102, e.g. if the HDR concept is implemented or, respectively, for other reasons. For example, the central average dopant dosage of the second doped semiconductor region 102 is at least four times, or even at least ten times, the average dopant dosage of the fourth doped semiconductor region 104 in the edge termination region 1-3. Thus, in the peripheral volume 1-22, near the transition between the active region 1-2 and the edge termination region 1-3, there can be a sudden change of the average dopant dosage along the lateral direction X at the transition 102-104 between the second doped semiconductor region 102 and the fourth doped semiconductor region 104 according to the design of the reference diode (which can be similarly implemented in other reference designs, e.g. in IGBT or MOSFET designs). The sudden change in the emitter efficiency caused by the transition 102-104 can lead to an increased current density on the high efficiency side of the transition 102-104.

[0121] Figures 10A to 15 The embodiments illustrated in each of Figs. 1-8B include the idea of replacing such a sudden transition 102-104 with a smooth transition by gradually reducing the average dopant dosage of the emitter towards the edge 1-4 (which does not necessarily imply that the average dopant dosage in the peripheral volume 1-22 is smaller than the average dopant dosage in the central volume 1-21).

[0122] According to the following embodiments, the reduced average dopant dosage in the peripheral volume 1-22 will be exemplarily described with respect to the second doped semiconductor region 102. Figures 10A to 15The power semiconductor device 1, e.g. an IGBT, as illustrated in each of the embodiments in Figs. 1-3, comprises an active region 1-2 having at least one (more typically several hundred) power cell 1-1, wherein the active region 1-2 has a total volume having a central volume 1-21 forming at least 80% of the total volume. A peripheral volume 1-22 surrounds the central volume 1-21. An edge termination region 1-3 is arranged outside the active region 1-2 and surrounds the peripheral volume 1-22. Here, it should be made clear that the peripheral volume 1-22 can be comprised by the active region 1-2 or the edge termination region 1-3 or can extend into both the active region 1-2 and the edge termination region 1-3. The semiconductor body 10 has a front side 110 and a back side 120, wherein the semiconductor body 10 forms part of each of the active region 1-2, the peripheral volume 1-22 and the edge termination region 1-3. The semiconductor body 10 has a total thickness along the vertical direction Z between the front side 110 and the back side 120. The peripheral volume 1-22 has a lateral extension amounting to at least half or at least 100% of the total semiconductor body thickness.

[0123] As clarified earlier, the device 1 can have a symmetrical design with respect to a central vertical axis 1-0, e.g. the following design: According to this design, the minimum lateral extension of the peripheral volume 1-22 exists in each of the lateral directions X, Y and R. The power semiconductor device 1 further comprises a first load terminal 11 (e.g. an emitter terminal) at the semiconductor body front side 110 and a second load terminal 12 at the semiconductor body back side 120; a first doped semiconductor region 101 formed in the semiconductor body 10 (e.g. a p-body region) and electrically connected with the first load terminal 11; a second doped semiconductor region 102 formed in the semiconductor body 10 (e.g. a p-emitter region) and electrically connected with the second load terminal 12. The second doped semiconductor region 102 has a central portion 102-21 extending into the central volume 1-21 of the active region 1-2 and having a central average dopant dose; a peripheral portion 102-22 extending into the peripheral volume 1-22 and having a peripheral average dopant dose having a negative gradient along the lateral extension of the peripheral volume in the lateral direction towards the edge termination region 1-3; and an edge portion 102-23 extending into the edge termination region 1-3 and having an edge average dopant dose, wherein the edge average dopant dose is lower than the central average dopant dose, e.g. by at least 5%.

[0124] According to Figure 1In each of the embodiments illustrated in the figures, the peripheral average dopant dose of the second doped semiconductor region 102 decreases along at least one of the lateral directions R, X, Y (pointing from the central volume 1-21 towards the edge termination region 1-3). With respect to all embodiments described in the following, it should again be understood that the illustrated profiles can equally exist throughout the entire peripheral volume 1-22 (see e.g. Fig. 1-1). In embodiments, the peripheral average dopant dose of the second doped semiconductor region 102 can be lower than the central average dopant dose of the central volume 1-21. In embodiments, the peripheral average dopant dose of the second doped semiconductor region 102 can be higher than the edge average dopant dose of the edge termination region 1-3. In embodiments, the peripheral average dopant dose of the second doped semiconductor region 102 can be lower than the central average dopant dose of the central volume 1-21 and higher than the edge average dopant dose of the edge termination region 1-3. Figures 10A-13 For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 20% and higher than the edge average dopant dose by at least 20%. For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 30% and higher than the edge average dopant dose by at least 30%. For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 40% and higher than the edge average dopant dose by at least 40%. For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 50% and higher than the edge average dopant dose by at least 50%. For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 60% and higher than the edge average dopant dose by at least 60%. For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 70% and higher than the edge average dopant dose by at least 70%. For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 80% and higher than the edge average dopant dose by at least 80%. For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 90% and higher than the edge average dopant dose by at least 90%. For example, the peripheral average dopant dose can be lower than the central average dopant dose by at least 95% and higher than the edge average dopant dose by at least 95%.

[0125] In embodiments, the edge portion 102-23 of the second doped semiconductor region 102 can correspond to the fourth doped semiconductor region 104 mentioned above. The power semiconductor device 1 can be an IGBT or MOSFET, and the semiconductor body 10 in the active region 1-2 can be configured to conduct an IGBT / MOSFET load current between the first load terminal 11 and the second load terminal 12.

[0126] In embodiments, the peripheral average dopant dose (e.g. integrated over the entire lateral extension of the peripheral volume 1-22) can be lower than the central average dopant dose (e.g. integrated over the entire lateral extension of the central volume 1-21), e.g. the peripheral average dopant dose amounts to not more than 80% of the central average dopant dose. Additionally or alternatively, the peripheral average dopant dose (e.g. integrated over the entire lateral extension of the peripheral volume 1-22) can be higher than the edge average dopant dose (e.g. integrated over the entire lateral extension of the edge termination region 1-3), e.g. the peripheral average dopant dose amounts to more than 120% of the edge average dopant dose.

[0127] Thus, according to embodiments described herein, the peripheral average dopant dose can be at least 20% lower than the central average dopant dose, and the peripheral average dopant dose can be at least 20% higher than the edge average dopant dose.

[0128] For example, with reference to Figure 10A which schematically and exemplarily illustrates various vertical cross sections of a power semiconductor device 1 having a second doped semiconductor region 102 with a decreasing average dopant dose in a peripheral volume 1-22, i.e. according to some embodiments, with a negative gradient in a lateral direction towards an edge termination region 1-3 along a lateral extension of the peripheral volume 1-22, the decrease of the peripheral average dopant dose of the peripheral portion 102-22 of the second doped semiconductor region 102 along the lateral direction can be lower than a maximum rate. Such gradual decrease of the average dose is schematically illustrated by the corresponding hatched area of the second doped semiconductor region 102.

[0129] For example, the peripheral average dopant dose of the second doped semiconductor region 102 (i.e. in the peripheral portion 102-22) has a negative gradient along the lateral direction towards the edge 1-4 of less than 5% per 1 pm, or even less than 1% per 1 pm, for example. For example, this means that the average dopant dose can amount to a first value averaged over a first distance of 1 pm, and a second value averaged over a second distance of 1 pm following the first distance, wherein the second value amounts to at least 95% of the first value (negative gradient of 5% per 1 pm, which means that the dopant dose decreases to 1 / e (~.37) over a distance of 20 pm, for example) or correspondingly at least 99% of the first value (negative gradient of 1% per 1 pm, which means that the dopant dose decreases to 1 / e over a distance of 100 pm, for example).

[0130] Further, in embodiments, the aforementioned maximum change rate (i.e. maximum gradient) can be present for at least 80% of the total lateral extension of the peripheral volume 1-22, which can amount to at least 50% or even at least 100% of the total semiconductor body thickness, as explained above. Thus, the peripheral average dopant dose of the peripheral portion 102-22 of the second doped semiconductor region 102 can moderately decrease along the lateral direction towards the edge termination region 1-3 (i.e. towards the edge 1-4).

[0131] For example, the peripheral average dopant dose of the second doped semiconductor region 102 in the peripheral volume 1-22 and along the lateral direction towards the edge 1-4 decreases from a value amounting to at least 80% of the central average dopant dose to a value amounting to at most 120% of the edge average dopant dose of the edge portion 102-23.

[0132] Further, the decrease of the peripheral average dopant dose of the second doped semiconductor region 102 can gradually occur along a distance of at least 30%, or at least 50%, or at least 80% of the total lateral extension of the peripheral volume 1-22.

[0133] It can be provided that the average dopant dose of the second doped semiconductor region 102 decreases along the lateral direction towards the edge 1-4 from a maximum value in the central volume 1-21 to a minimum value in the peripheral volume 1-22, wherein the decrease gradually occurs along a lateral distance in a range of 20% to 150% of the total semiconductor body thickness along the vertical direction Z, or in a range corresponding to 50% to 100% of the total semiconductor body thickness along the vertical direction Z.

[0134] For example, with reference to Figure 10B and Figure 10AThe foregoing exemplary variations of average dopant dose reduction can be implemented by implementing a VLD structure in the peripheral portion 102-22 that provides a gradual transition, e.g., between the highest average dopant dose of the second doped semiconductor region 102 at the transition between the central volume 1-21 and the peripheral volume 1-22 and the lowest average dopant dose of the second doped semiconductor region 102 at the transition between the peripheral volume 1-22 and the edge termination region 1-3. For example, the VLD structure has a total lateral extension that is at least 50% of the total lateral extension of the peripheral volume 1-22. For example, the reduction of the average dopant dose is less than, e.g., 5% per 1 pm, or even less than 1% per 1 pm, along the entire lateral extension of the VLD structure.

[0135] For example, the VLD structure in the peripheral portion 102-22 has a lateral extension that is defined by the distance between the portion of the second doped semiconductor region 102 that forms the homogenous high-efficiency emitter region in the active region 1-2 (e.g., the central portion 102-21) and the portion of the second doped semiconductor region 102 that forms the homogenous low-efficiency emitter region between the high-efficiency emitter region and the edge 1-4 (e.g., the edge portion 102-23). This lateral extension of the peripheral portion 102-22 can be large compared to the typical diffusion length of the doping, which is on the order of 0.1 to 5 pm, and can amount to at least 10%, at least 50%, or even at least 100% of the total thickness of the semiconductor body 10 (or the vertical extension of the space-charge region at the nominal blocking voltage). Exemplary values of the lateral extension of the VLD structure are in the range of 20% to 150% of the thickness of the semiconductor body 10. For example, according to one embodiment, there is then no point where a sudden change in emitter efficiency can pin a developing current filament, and the robustness of the power semiconductor device 1 is expected to be limited only by the robustness of the active region 1-2.

[0136] As explained above and as illustrated in Figure 10B The peripheral volume 1-22, and thus also the peripheral portion 102-22, can extend into both the edge termination region 1-3 and the active region 1-2. For example, a gradual reduction of the average peripheral dopant dose is then implemented across the boundary between the active region 1-2 and the edge termination region 1-3. Alternatively, as illustrated in Figure 11As illustrated in the middle, the peripheral volume 1-22 only comprises the active region 1-2, and in this case, the VLD structure can terminate within the peripheral volume 1-22 of the active region 1-2, and the average dopant dose of the second doped semiconductor region 102 can be substantially constant along the lateral direction towards the edge 1-4 from the termination of the VLD structure onwards, e.g. a total average edge dopant dose. For example, in the vicinity of the transition between the active region 1-2 and the edge termination region 1-3, the dopant dose of the second doped semiconductor region 102 can be substantially equal to the average edge dopant dose.

[0137] As Figure 11 As illustrated in the middle, the peripheral volume 1-22 only comprises the active region 1-2, and in this case, the VLD structure can terminate within the peripheral volume 1-22 of the active region 1-2, and the average dopant dose of the second doped semiconductor region 102 can be substantially constant along the lateral direction towards the edge 1-4 from the termination of the VLD structure onwards, e.g. a total average edge dopant dose. For example, in the vicinity of the transition between the active region 1-2 and the edge termination region 1-3, the dopant dose of the second doped semiconductor region 102 can be substantially equal to the average edge dopant dose.

[0138] As Figure 12 The embodiment illustrated in the middle, the transition between the active region 1-2 and the edge termination region 1-3, i.e. the border of the active region 1-2, is at the outermost power cell 1-1, e.g. at the outermost source region 109 which contributes to form the path of the device load current. Further, the peripheral volume 1-22 is fully comprised in the edge termination region 1-3.

[0139] For example, as illustrated, the power cells 1-1 can laterally overlap with a central portion 102-21 of the second doped semiconductor region 102 which, e.g. in the manner as explained above, differs in average dopant dose compared to the peripheral portion 102-22 as well as compared to an edge portion 102-23 of the second doped semiconductor region 102.

[0140] Figure 13 The embodiment illustrated in the middle corresponds to the embodiment illustrated in the middle of Figure 10A The embodiment illustrated in the middle corresponds to the embodiment illustrated in the middle of Figure 12 Therein, in particular what has been stated there with respect to the semiconductor regions / portions 101, 102 can equally apply to the embodiments of Figure 12 The embodiment illustrated in the middle corresponds to the embodiment illustrated in the middle of 13 The embodiment illustrated in the middle corresponds to the embodiment illustrated in the middle of The embodiment illustrated in the middle corresponds to the embodiment illustrated in the middle of

[0141] As Figure 13 and Figure 12 illustrated in

[0142] In Figure 13 , the conductive portion 113 exhibiting the potential of the second load terminal 12 can be arranged at the insulating structure 13 and can contact the semiconductor body 10 in the edge termination region 1-3, e.g. in the vicinity of the edge 1-4, e.g. in order to realize a channel stopper function.

[0143] In a variant according to Figure 13 , the conductive portion 113 exhibits the potential of a control (e.g. gate) terminal (e.g. when the power semiconductor device 1 is an IGBT) and is arranged at the insulating structure 13 and does not contact the semiconductor body 10. Further, in order to reduce the electric field strength in the edge termination region 1-3, a field plate 131 can be integrated within the insulating structure 13 and can be electrically contacted by the conductive portion 113. Figure 13 Reference sign 1-3 can also designate a gate terminal region or a gate finger region, too, which can also refer to a structure of a gate terminal or a gate finger which is not necessarily located in the vicinity of the chip edge. In this case, reference sign 1-3 can also designate a gate terminal region or a gate finger region.

[0144] The third doped semiconductor region 103 can have the same conductivity type as the first doped semiconductor region 101 (e.g. both are p-doped) and can extend along the front side 110 within the edge termination region 1-3 and can have substantially the same average dopant dose as the first doped semiconductor region 101 as illustrated in Figure 12 , or can differ in dose, e.g. by exhibiting a lower average dopant dose compared to the first doped semiconductor region 101 (see Figure 13 , indicated by a separation line segment between region 101 and region 103). Further, the third doped semiconductor region 103 can extend throughout the entire lateral extension of the edge termination region 1-3 (see Figure 12 ), or can accordingly terminate before the edge 1-4 as illustrated in Figure 6A , e.g. in order to avoid being contacted by the conductive portion 113.

[0145] For example, the conductive portion 113 can form a metal pad for a control terminal or a gate finger structure.

[0146] Embodiments of a method of processing a power semiconductor device are also presented herein.

[0147] For example, in an embodiment, a method of processing a power semiconductor device includes providing a power semiconductor device having an active region having at least one power cell, where the active region has a total volume having: a central volume forming at least 20% of the total volume; a peripheral volume forming at least 20% of the total volume and surrounding the central volume; and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The power semiconductor device further includes: an edge termination region surrounding an edge of the outermost peripheral volume of the active region, where the peripheral volume has a constant lateral distance from the edge termination region; a semiconductor body having a front side and a back side, where the semiconductor body forms both a portion of the active region and a portion of the edge termination region; a first load terminal at the semiconductor body front side and a second load terminal at the semiconductor body back side. The method further includes: forming a first doped semiconductor region in the semiconductor body such that it is electrically connected with the first load terminal; forming a second doped semiconductor region in the semiconductor body such that it is electrically connected with the second load terminal. At least one of the first doped semiconductor region and the second doped semiconductor region has: a central portion extending into the central volume of the active region and having a central average dopant dose; a peripheral portion extending into the peripheral volume of the active region and having a peripheral average dopant dose, where the central average dopant dose is at least 5% lower or at least 10% lower than the peripheral average dopant dose.

[0148] According to another embodiment, a method of processing a power semiconductor device comprises providing a power semiconductor device having an active region with at least one power cell, wherein the active region has a total volume, the total volume having a central volume forming at least 80% of the total volume, a peripheral volume surrounding the central volume, and a edge termination region arranged outside the active region and surrounding the peripheral volume, a semiconductor body having a front side and a back side, wherein the semiconductor body forms part of each of the active region, the peripheral volume, and the edge termination region. The semiconductor body has a total thickness along a vertical direction between the front side and the back side. The peripheral volume has a lateral extension amounting to at least half of the total semiconductor body thickness. The power semiconductor device further comprises a first load terminal at the semiconductor body front side and a second load terminal at the semiconductor body back side. The method further comprises forming a first doped semiconductor region in the semiconductor body such that it is electrically connected with the first load terminal, and forming a second doped semiconductor region in the semiconductor body such that it is electrically connected with the second load terminal. The second doped semiconductor region has a central portion extending into the central volume of the active region and having a central average dopant dose, a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose, the peripheral average dopant dose having a negative gradient along the lateral extension of the peripheral volume in a lateral direction towards the edge termination region, and an edge portion extending into the edge termination region and having an edge average dopant dose, wherein the edge average dopant dose is lower than the central average dopant dose.

[0149] Exemplary further embodiments of the two methods described in the two preceding paragraphs correspond to the embodiments of the power semiconductor device 1 described above. So far, it refers to the foregoing.

[0150] For example, with respect to Figure 10A - D, Figs. 8A-B, Figures 11-13 - B and Figure 6C Various possibilities have been described how the difference in average dopant dose and / or the peripheral average dopant dose can be configured to have a negative gradient along the lateral extension of the peripheral volume 1-22 in a lateral direction towards the edge termination region can be implemented. For example, to form the first doped semiconductor region 101 and / or the second doped semiconductor region 102 in the peripheral volume 1-22, one or more additional dopants of the provision step (e.g., the implantation step) can be carried out, and / or one or more modified masks can be used, for example without altering the process flow applied to the reference design.

[0151] For example, in the peripheral volume 1-22, the specified average dopant dose can be achieved by at least one of a variation of the injected dose, an injected duration and a variation of the average open area percentage along the lateral direction towards the edge 1-4 during the injection.

[0152] According to an embodiment of the method, it has been explained that such a modified mask can be used for forming the modified first doped semiconductor region 101; thus, the modified mask can be used to form both the central portion 101-21 and the peripheral portion 101-22, e.g. a mask exhibiting a plurality of openings which increase in at least one of number and size along the lateral directions X, Y and R, such that the difference in average dopant dose can be achieved. Figure 15 For example, for forming the second doped semiconductor region 102 such that it exhibits the above explained gradual decrease of the average dopant dose in the peripheral volume 1-22, i.e. according to an embodiment a negative gradient of the peripheral average dopant dose of the second doped semiconductor region 102, i.e. in the peripheral portion 102-22, along the lateral direction towards the edge 1-4 of e.g. less than 5% per 1 pm, or even less than 1% per 1 pm, an injection pattern 300 as illustrated in

[0153] Figure 14 therein can be employed. There, the unshaded (white areas) indicate high injection dose, while the hatched areas indicate low injection dose. Thus, in the cross section of the peripheral volume 1-21 adjacent to the central volume 1-22, the maximum average dopant dose is achieved. Due to the pattern structure, the injection dose decreases along the first lateral direction X, thereby achieving the above explained gradual decrease of the average dopant dose in the peripheral volume 1-22, i.e. this gradual decrease is provided by means of the VLD structure in the second doped semiconductor region 102.

[0154] Finally, reference is made to ​ ​The average dopant dose ("ADD") of the peripheral portion 102-22 of the second doped semiconductor region 102 can initially (i.e., in the vicinity of the transition between the central volume 1-21 and the peripheral volume 1-22) be substantially constant, schematically and exemplarily illustrated by the lateral dopant dose profile. With the onset of the VLD structure in the peripheral volume 1-22, the average dopant dose decreases along the first lateral direction X, wherein such decrease can occur gradually (solid line) (e.g., substantially linearly) or according to a step profile (dashed line). According to the exemplary provision indicated above, for example, the decrease of the peripheral average dopant dose of the second doped semiconductor region 102 along the first lateral direction X can be, for example, less than the maximum value; for example, the negative gradient of the peripheral average dopant dose of the second doped semiconductor region 102 (i.e., in the peripheral portion 102-22) along the lateral direction towards the edge 1-4 is less than, for example, 5% per 1 pm, or even less than 1% per 1 pm.

[0155] In the foregoing, embodiments regarding power semiconductor devices and corresponding processing methods have been explained.

[0156] For example, these semiconductor devices are silicon (Si) based. Thus, for example, the single crystalline semiconductor regions or layers of the semiconductor body 10 and its regions / bands (e.g., multiple regions, etc.) can be single crystalline Si regions or Si layers. In other embodiments, polycrystalline silicon or amorphous silicon can be employed.

[0157] However, it should be appreciated that the semiconductor body 10 and its regions / bands can be made of any semiconductor material suitable for fabricating semiconductor devices. Examples of such materials include, but are not limited to: elemental semiconductor materials such as silicon (Si) or germanium (Ge); IV- group compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II- VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The aforementioned semiconductor materials are also referred to as "homo-junction semiconductor materials". When two different semiconductor materials are combined, a hetero-junction semiconductor material is formed. Examples of hetero-junction semiconductor materials include, without limitation: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-carbon silicon (SixC1-x) and silicon-SiGe hetero-junction semiconductor materials. For power semiconductor switching applications, currently Si, SiC, GaAs and GaN materials are predominantly used.

[0158] For ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for describing an element's position as it relates to the position of a second element. These terms are intended to encompass different orientations of the respective devices in addition to the orientation depicted in the figures. Further, terms such as "first", "second", and the like can be used herein for describing various elements, regions, sections, and the like, and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0159] As used herein, the terms "have", "comprise", "include", "contain", "exhibit", and the like are open-ended terms that indicate the presence of stated elements or features but do not preclude additional elements or features.

[0160] With consideration of the above-described variations and applications, it should be understood that the present application is not limited by the foregoing description, nor is it limited by the accompanying figures. Instead, the present application is limited only by the following claims and their legal equivalents.

Claims

1. A power semiconductor device (1), comprising: - An active region (1-2) having at least one power unit (1-1), wherein the active region (1-2) has a total volume, the total volume having: The central volume (1-21) constitutes at least 20% of the total volume; The outer volume (1-22) forms at least 20% of the total volume and surrounds the central volume (1-21). as well as The outermost peripheral volume (1-23) forms at least 5% of the total volume and surrounds the peripheral volume (1-22). - An edge terminal region (1-3) surrounding the outermost peripheral volume (1-23) of the active region (1-2), wherein the peripheral volume (1-22) has a constant lateral distance from the edge terminal region (1-3); - A semiconductor body (10) having a front side (110) and a back side (120), wherein the semiconductor body (10) forms both a portion of the active region (1-2) and a portion of the edge terminal region (1-3); - A first load terminal (11) on the front side (110) of the semiconductor body and a second load terminal (12) on the back side (120) of the semiconductor body. - A first doped semiconductor region (101) is formed in the semiconductor body (10) and is electrically connected to the first load terminal (11); - A second doped semiconductor region (102) is formed in the semiconductor body (10) and is electrically connected to the second load terminal (12); At least one of the first doped semiconductor region (101) and the second doped semiconductor region (102) extends continuously along the lateral extension of the central volume, the peripheral volume, and the outermost peripheral volume, and has The central portion (101-21; 102-21) extends into the central volume (1-21) of the active region (1-2) and has a central average dopant dose; The peripheral portions (101-22; 102-22) extend into the peripheral volume (1-22) of the active region (1-2) and have a peripheral average dopant dose, and The portion extending within the outermost peripheral volume, wherein The central average dopant dose is at least 5% lower than the peripheral average dopant dose.

2. The power semiconductor device (1) according to claim 1, wherein the semiconductor body (10) in the active region (1-2) is configured to conduct load current between the first load terminal (11) and the second load terminal (12), and / or wherein the power semiconductor device (1) is a power semiconductor diode or IGBT or MOSFET.

3. A power semiconductor device (1), comprising: - An active region (1-2) having at least one power unit (1-1), wherein the active region (1-2) has a total volume having a central volume (1-21) that forms at least 80% of the total volume. - The outer volume (1-22) surrounding the central volume (1-21); and - Edge terminal area (1-3), which is arranged outside the active area (1-2) and around the peripheral volume (1-22). - A semiconductor body (10) having a front side (110) and a back side (120), wherein the semiconductor body (10) forms a portion of each of the active region (1-2), the peripheral volume (1-22), and the edge termination region (1-3), wherein The semiconductor body (10) has a total thickness along the vertical direction (Z) between the front side (110) and the back side (120); and The peripheral volume (1-22) has a lateral extension that is at least half the total semiconductor body thickness; - A first load terminal (11) on the front side (110) of the semiconductor body and a second load terminal (12) on the back side (120) of the semiconductor body. - A first doped semiconductor region (101) is formed in the semiconductor body (10) and is electrically connected to the first load terminal (11); - A second doped semiconductor region (102) is formed in the semiconductor body (10) and is electrically connected to the second load terminal (12); The second doped semiconductor region (102) has the same doping type and has The central portion (102-21) extends into the central volume (1-21) of the active region (1-2) and has a central average dopant dose; The peripheral portion (102-22) extends into the peripheral volume (1-22) and has a peripheral average dopant dose that extends laterally along the peripheral volume (1-22) and has a negative gradient in the lateral direction toward the edge terminal region (1-3). An edge portion (102-23) extends into the edge terminal region (1-3) to the edge of the power semiconductor device (1) and has an edge average dopant dose, wherein the edge average dopant dose is lower than the central average dopant dose.

4. The power semiconductor device (1) according to claim 3, wherein the semiconductor body (10) is configured in the active region (1-2) to conduct load current between the first load terminal (11) and the second load terminal (12), and / or wherein the power semiconductor device (1) is an IGBT or a MOSFET.

5. The power semiconductor device (1) according to any one of claims 3-4, wherein the first doped semiconductor region (101) and the second doped semiconductor region (102) are both configured to facilitate the formation of a load current path.

6. The power semiconductor device (1) according to claim 5, wherein the peripheral average dopant dose is greater than the central average dopant dose, and wherein at least one of the first doped semiconductor region (101) and the second doped semiconductor region (102) extends continuously into both the peripheral volume (1-22) and the central volume (1-21) of the active region (1-2), and wherein the first doped semiconductor region (101) is an anode region and the second doped semiconductor region (102) is a cathode region.

7. The power semiconductor device (1) according to claim 3 or 4, wherein the peripheral average dopant dose has a negative gradient of less than 5% per 1 μm along the lateral direction.

8. The power semiconductor device (1) according to any one of claims 3-4, wherein, The corresponding dopant dose is defined by the dopant concentration integrated along the vertical direction (Z) from the first load terminal (11) to the second load terminal (12).

9. The power semiconductor device (1) according to claim 8, wherein the corresponding average dopant dose is defined by a dopant metering averaged over a distance of at least 10 μm along a lateral direction (R; X; Y), which is perpendicular to the vertical direction (Z) and points from the central volume (1-21) toward the edge terminal region (1-3).

10. The power semiconductor device (1) according to claim 9, wherein, The corresponding average dopant dose is defined by the dopant dose averaged along the total lateral extension of the corresponding region, or correspondingly, by the volume averaged in the lateral direction (R; X; Y).

11. The power semiconductor device (1) according to any one of claims 3-4, wherein, In the vertical cross-section of the power semiconductor device (1), - The first load terminal (11) and the first doped semiconductor region (101) overlap each other laterally; - At least 75% of the transition along the vertical direction (Z) between the first load terminal (11) and the first doped semiconductor region (101) in the vertical cross section along the total lateral extension of the peripheral volume (1-22) is conductive.

12. The power semiconductor device (1) according to any one of claims 3-4, wherein, In the vertical cross-section of the power semiconductor device (1), - The second load terminal (12) and the second doped semiconductor region (102) overlap laterally with each other; - At least 75% of the transition along the vertical direction (Z) between the second load terminal (12) and the second doped semiconductor region (102) in the vertical cross section along the total lateral extension of the peripheral volume (1-22) is conductive.

13. The power semiconductor device (1) according to any one of claims 3-4, wherein, In the peripheral volume (1-22), at least one of the first doped semiconductor region (101) and the second doped semiconductor region (102) exhibits a VLD structure.

14. The power semiconductor device (1) according to any one of claims 3-4, wherein a first doped semiconductor region (101) is seamlessly bonded to a third doped semiconductor region (103), wherein the third doped semiconductor region (103) has the same conductivity type as the first doped semiconductor region (101) and extends along the front side (110) within the edge terminal regions (1-3).

15. The power semiconductor device (1) according to claim 1 or 2, wherein, The second doped semiconductor region (102) is bonded to the fourth doped semiconductor region (104), wherein the fourth doped semiconductor region (104) has the same conductivity type as the second doped semiconductor region (102) and extends along the back surface (120) within the edge terminal region (1-3).

16. The power semiconductor device (1) according to claim 15, wherein the central average dopant dose of the second doped semiconductor region (102) is at least four times greater than the average dopant dose of the fourth doped semiconductor region (104) in the edge terminal regions (1-3).

17. The power semiconductor device (1) according to claim 3, wherein the negative gradient of the peripheral average dopant dose of the second doped semiconductor region (102) along the lateral direction (R; X; Y) is less than 5% per 1 μm.

18. The power semiconductor device (1) according to claim 3, wherein in the peripheral volume (1-22), the peripheral average dopant dose of the second doped semiconductor region (102) is reduced from a value totaling at least 80% of the central average dopant dose to a value totaling at most 120% of the edge average dopant dose.

19. The power semiconductor device (1) according to claim 18, wherein, The reduction in the peripheral average dopant dose of the second doped semiconductor region (102) occurs gradually along a distance totaling at least 30% of the total lateral extension of the peripheral volume (1-22).

20. The power semiconductor device (1) according to any one of claims 3-4, wherein the average dopant dose of the second doped semiconductor region (102) decreases from a maximum value in the central volume (1-21) to a minimum value in the peripheral volume (1-22) along a lateral direction (R; X; Y) from the central volume (1-21) to the edge terminal region (1-22), wherein the decrease occurs gradually along a lateral distance ranging from 20% to 150% of the semiconductor body thickness.

21. A power semiconductor device (1), comprising: - An active region (1-2) having at least one power unit (1-1), wherein the active region (1-2) has a total volume, the total volume having: The central volume (1-21) constitutes at least 20% of the total volume; The outer volume (1-22) forms at least 20% of the total volume and surrounds the central volume (1-21). as well as The outermost peripheral volume (1-23) forms at least 5% of the total volume and surrounds the peripheral volume (1-22). - An edge terminal region (1-3) surrounding the outermost peripheral volume (1-23) of the active region (1-2), wherein the peripheral volume (1-22) has a constant lateral distance from the edge terminal region (1-3); - A semiconductor body (10) having a front side (110) and a back side (120), wherein the semiconductor body (10) forms both a portion of the active region (1-2) and a portion of the edge terminal region (1-3); - A first load terminal (11) at the front side (110) of the semiconductor body and a second load terminal (12) at the back side (120) of the semiconductor body; wherein The active region (1-2) is configured to conduct load current between the first load terminal (11) and the second load terminal (12), wherein the load current density in the central volume (1-21) is at least 5% lower than the load current density in the peripheral volume (1-22) by increasing the average dopant dose in the peripheral volume.

22. A method of processing a power semiconductor device (1), comprising providing the power semiconductor device (1), the power semiconductor device (1) having: - An active region (1-2) having at least one power unit (1-1), wherein the active region (1-2) has a total volume, the total volume having: The central volume (1-21) constitutes at least 20% of the total volume; The outer volume (1-22) forms at least 20% of the total volume and surrounds the central volume (1-21). as well as The outermost peripheral volume (1-23) forms at least 5% of the total volume and surrounds the peripheral volume (1-22). - An edge terminal region (1-3) surrounding the outermost peripheral volume (1-23) of the active region (1-2), wherein the peripheral volume (1-22) has a constant lateral distance from the edge terminal region (1-3); - A semiconductor body (10) having a front side (110) and a back side (120), wherein the semiconductor body (10) forms both a portion of the active region (1-2) and a portion of the edge terminal region (1-3); - A first load terminal (11) on the front side (110) of the semiconductor body and a second load terminal (12) on the back side (120) of the semiconductor body. The method further includes: - A first doped semiconductor region (101) is formed in the semiconductor body (10) such that it is electrically connected to the first load terminal (11); - A second doped semiconductor region (102) is formed in the semiconductor body (10) such that it is electrically connected to the second load terminal (12); At least one of the first doped semiconductor region (101) and the second doped semiconductor region (102) extends continuously along the lateral extension of the central volume, the peripheral volume, and the outermost peripheral volume, and has The central portion (101-21; 102-21) extends into the central volume (1-21) of the active region (1-2) and has a central average dopant dose; The peripheral portions (101-22; 102-22) extend into the peripheral volume (1-22) of the active region (1-2) and have a peripheral average dopant dose, and The portion extending within the outermost peripheral volume, wherein The central average dopant dose is at least 5% lower than the peripheral average dopant dose.

23. A method of processing a power semiconductor device (1), comprising providing the power semiconductor device (1), the power semiconductor device (1) having: - An active region (1-2) having at least one power unit (1-1), wherein the active region (1-2) has a total volume having a central volume (1-21) that forms at least 80% of the total volume. - The outer volume (1-22) surrounding the central volume (1-21); and - The edge terminal region (1-3) is arranged outside the active region (1-2) and around the peripheral volume (1-23). - A semiconductor body (10) having a front side (110) and a back side (120), wherein the semiconductor body (10) forms a portion of each of the active region (1-2), the peripheral volume (1-22), and the edge termination region (1-3), wherein The semiconductor body (10) has a total thickness along a vertical direction (Z) between the front side (110) and the back side (120); and The peripheral volume (1-22) has a lateral extension that is at least half the total semiconductor body thickness; - A first load terminal (11) on the front side (110) of the semiconductor body and a second load terminal (12) on the back side (120) of the semiconductor body. The method further includes: - A first doped semiconductor region (101) is formed in the semiconductor body (10) such that it is electrically connected to the first load terminal (11); - A second doped semiconductor region (102) is formed in the semiconductor body (10) such that it is electrically connected to the second load terminal (12); The second doped semiconductor region (102) has the same doping type and has The central portion (102-21) extends into the central volume (1-21) of the active region (1-2) and has a central average dopant dose; The peripheral portion (102-22) extends into the peripheral volume (1-22) and has a peripheral average dopant dose that extends laterally along the peripheral volume (1-22) and has a negative gradient in the lateral direction toward the edge terminal region (1-3). An edge portion (102-23) extends into the edge terminal region (1-3) to the edge of the power semiconductor device (1) and has an edge average dopant dose, wherein the edge average dopant dose is lower than the central average dopant dose.

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