Integrated component and electronic equipment

Abstract

The utility model discloses an integrated component and electronic equipment. The integrated assembly includes: a substrate; the patterned conductive layer is located on one side of the substrate and at least comprises a first conductive pattern and a second conductive pattern; the power device is positioned on one side, back to the substrate, of the first conductive pattern; and the buffer circuit is located on one side, back to the substrate, of the second conductive pattern, and the buffer circuit is connected with the power device. According to the embodiment of the invention, the problems of voltage / current waveform oscillation and voltage overshoot peak caused in the commutation process of the power semiconductor device can be solved.

Description

Technical Field

[0001] This application relates to the field of power device integration technology, specifically to an integrated component and electronic device. Background Technology

[0002] Circuits employing power semiconductor devices can control current and voltage through frequency conversion, voltage conversion, and current conversion, thereby achieving the conversion and control of electrical energy. Therefore, power semiconductor devices are widely used in various power electronic systems, such as inverter systems, power conversion systems, and frequency conversion and voltage conversion systems.

[0003] In power electronic systems, power semiconductor devices control current through switching processes, which often involve changes in the current flow path within the module, a process known as "commutation." The switching of power semiconductor devices causes rapidly changing voltages and currents along the power electronic system paths (such as the pins and copper layers of components on a printed circuit board (PCB), and the terminals and bond wires in a power module), leading to voltage / current waveform oscillations and voltage overshoot spikes. These oscillations and voltage overshoot spikes not only increase system losses but also increase the voltage experienced by the power semiconductor devices, reducing system reliability.

[0004] Therefore, how to solve the problems of electrical signal waveform oscillation and voltage overshoot spikes is a research issue for those skilled in the art. Utility Model Content

[0005] This application provides an integrated component and electronic device that can solve the problems of voltage / current waveform oscillation and voltage overshoot spikes caused by the commutation process of power semiconductor devices.

[0006] In a first aspect, embodiments of this application provide an integrated component, the integrated component comprising: a substrate; a patterned conductive layer located on one side of the substrate, including at least a first conductive pattern and a second conductive pattern; a power device located on the side of the first conductive pattern facing away from the substrate; and a buffer circuit located on the side of the second conductive pattern facing away from the substrate, wherein the buffer circuit is connected to the power device.

[0007] According to an embodiment of the first aspect of this application, the first conductive pattern includes a first conductive pattern A and a first conductive pattern B, and the second conductive pattern includes a second conductive pattern A and a second conductive pattern B; the power device includes a power device A and a power device B, with the power device A located on the side of the first conductive pattern A facing away from the substrate, and the power device B located on the side of the first conductive pattern B facing away from the substrate; the buffer circuit includes a buffer circuit A and a buffer circuit B, with the buffer circuit A located on the side of the second conductive pattern A facing away from the substrate, and the buffer circuit B located on the side of the second conductive pattern B facing away from the substrate, the buffer circuit A being connected to the power device A, and the buffer circuit B being connected to the power device B.

[0008] According to any of the foregoing embodiments of the first aspect of this application, power device A is adjacent to buffer circuit A, and power device B is adjacent to buffer circuit B.

[0009] According to any of the foregoing embodiments of the first aspect of this application, power device A and power device B are arranged in a first direction, and power device A and power device B are spaced apart in the first direction.

[0010] According to any of the foregoing embodiments of the first aspect of this application, a plurality of power devices A are divided into a first power device group and a second power device group, each including at least one power device A, and arranged in a second direction intersecting the first direction; the patterned conductive layer further includes a gate conductive pattern A, which is located between the first power device group and the second power device group A in the second direction; and / or, a plurality of power devices B are divided into a first power device group B and a second power device group B, each including at least one power device B, and arranged in a second direction; the patterned conductive layer further includes a gate conductive pattern B, which is located between the first power device group B and the second power device group B in the second direction.

[0011] According to any of the foregoing embodiments of the first aspect of this application, on the side of power device A away from power device B, a gate terminal A, a source terminal A, and a drain terminal A connected to power device A are provided; on the side of power device B away from power device A, a gate terminal B, a source terminal B, and a drain terminal B connected to power device B are provided.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the patterned conductive layer further includes a source conductive pattern B, which is connected to the source of a power device B; a first conductive pattern A is connected to a positive busbar connection structure via a first bonding wire; a source conductive pattern B is connected to a negative busbar connection structure via a second bonding wire; and a first conductive pattern B is connected to a neutral line connection structure via a third bonding wire; the positive busbar connection structure and the negative busbar connection structure are located on a first side of the substrate in a first direction, and the neutral line connection structure is located on a second side of the substrate in the first direction.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the patterned conductive layer further includes a third conductive pattern, and a temperature test terminal is provided on the side of the third conductive pattern facing away from the substrate.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the power device includes a drain and a source, the drain of the power device facing the first conductive pattern, and the source of the power device facing away from the first conductive pattern; the patterned conductive layer also includes a source conductive pattern, and the source of the power device and the source conductive pattern are connected by bonding wires.

[0015] Secondly, embodiments of this application provide an electronic device that includes integrated components as described in any of the first aspects.

[0016] In this embodiment, a first conductive pattern and a second conductive pattern are disposed on the same substrate. A power device is placed on the first conductive pattern, and a buffer circuit is placed on the second conductive pattern. The buffer circuit can be used to buffer problems such as electrical signal waveform oscillation and voltage overshoot spikes. In addition, the power device and the buffer circuit are integrated together, resulting in high integration and relatively close distance between the buffer circuit and the power device, which can improve the buffering effect.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0018] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0019] Figure 1 This illustration shows a structural schematic diagram of a power device in an integrated component provided in an embodiment of this application;

[0020] Figure 2This illustration shows an equivalent circuit structure diagram of a power device in an integrated component provided in an embodiment of this application;

[0021] Figure 3 This illustration shows a circuit diagram of power devices and buffer circuits in an integrated component provided in an embodiment of this application.

[0022] Figure 4 This illustration shows a structural diagram of a substrate and a patterned conductive layer in an integrated component provided in an embodiment of this application.

[0023] Figure 5 This illustration shows a schematic diagram of the distribution of components in an integrated component provided in an embodiment of this application;

[0024] Figure 6 This illustration shows an electrical connection diagram of components in an integrated assembly provided in an embodiment of this application;

[0025] Figure 7 This illustration shows another electrical connection diagram of the components in the integrated assembly provided in the embodiments of this application;

[0026] Figure 8 This illustration shows another electrical connection diagram of the components in the integrated assembly provided in the embodiments of this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 1. Substrate; 2. First conductive pattern (A); 3. Third conductive pattern (B);

[0029] 4. Source conduction pattern; 5. Second conduction pattern; 6. Gate conduction pattern;

[0030] 7. First conductive pattern (B); 8. Third conductive pattern; 9. Second conductive pattern (A);

[0031] 10. Gate A conductive pattern; 11. Fourth Gate A conductive pattern; 12. Third Gate A conductive pattern;

[0032] 13. Source terminal B; 14. Gate terminal B; 15. Drain terminal B;

[0033] 16. Power device B; 17. Power device A; 18. Temperature test terminal;

[0034] 19. Buffer resistor (Type A); 20. Buffer capacitor (Type A); 21. Source terminal (Type A);

[0035] 22. Gate terminal (A); 23. Drain terminal (A); 24. Buffer capacitor (B);

[0036] 25. Buffer resistor B. Detailed Implementation

[0037] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0038] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0039] It should be noted that when a component is described as "connected" or "electrically connected" to another component, it can be directly connected to the other component, or there may be one or more intermediate components in between.

[0040] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0041] As described in the background section, in power electronic systems, power semiconductor devices can cause voltage / current waveform oscillations and voltage overshoot spikes during the switching process.

[0042] In addition, during the layout design process, the internal metallization pattern design reduces parasitic inductance but also compresses the metallization pattern space, making it difficult to incorporate buffer circuits into the metallization pattern design.

[0043] To address the aforementioned technical problems, embodiments of this application provide an integrated component and an electronic device. The technical concept of this application includes: setting a first conductive pattern and a second conductive pattern on the same substrate; placing a power device on the first conductive pattern and a buffer circuit on the second conductive pattern; the buffer circuit can be used to buffer problems such as electrical signal waveform oscillation and voltage overshoot spikes; furthermore, integrating the power device and the buffer circuit together results in high integration, and the relatively close distance between the buffer circuit and the power device improves the buffering effect.

[0044] The embodiments of this application will be described below with reference to the accompanying drawings.

[0045] To facilitate understanding, the power devices in the integrated components provided in the embodiments of this application will be introduced first.

[0046] The power device can be a transistor. In this application, the embodiment of the power device is a metal-oxide-semiconductor field-effect transistor (MOSFET) as an example for illustration. Figure 1 This illustration shows a schematic diagram of a power device in an integrated component provided in an embodiment of this application, such as... Figure 1 As shown, a MOSFET includes a source S, a gate G, and a drain D, wherein the gate G and the source S are located on one side of the drain D. Figure 2 yes Figure 1 The equivalent circuit diagram of the power device, namely the equivalent circuit diagram of the MOSFET, has the gate (G), source (S), and drain (D) marked in the diagram.

[0047] During switching, power devices often experience voltage and current waveform oscillations and voltage overshoot spikes due to commutation. To mitigate these voltage spikes, common methods include reducing parasitic inductance through metallization patterns on the insulating substrate and adding buffer circuits to the system. Low parasitic inductance can reduce voltage oscillations during turn-on and turn-off, thus reducing switching losses.

[0048] Due to limitations imposed by parasitic inductance and standardized external connection terminals of power modules, this embodiment of the application uses a resistor-capacitor snubber circuit (RC snubber circuit) for high parallel power modules, as shown in the schematic diagram below. Figure 3 As shown, S1 is the power device of the upper bridge arm, which may include one power device or multiple power devices connected in parallel. S2 is the power device of the lower bridge arm, which may include one power device or multiple power devices connected in parallel.

[0049] The buffer circuit can be an RC circuit, meaning it can include a buffer capacitor and a buffer resistor connected in series. The buffer capacitor includes a first capacitor C1 and a second capacitor C2. The buffer resistor includes a first resistor R1 and a second resistor R2. The first resistor R1 is connected in series with the first capacitor C1, and then connected in parallel with the power module S1 of the upper bridge arm between the positive bus connection structure DC+ and the neutral connection structure AC. The second resistor R2 is connected in series with the second capacitor C2, and then connected in parallel with the power module S2 of the lower bridge arm between the neutral connection structure AC and the negative bus connection structure DC-.

[0050] During the power device's turn-off process, the buffer circuit absorbs the reverse electromotive force generated by the parasitic inductance through the buffer capacitor; during the power device's turn-on process, the buffer resistor slows down the rate of current change, thereby effectively suppressing voltage and current oscillations, reducing losses during the power device's switching process, and improving the reliability of the power module.

[0051] For example, when the power device S1 of the upper bridge arm is turned off, the second capacitor C2 absorbs the reverse electromotive force generated by the parasitic inductance; when the power device S1 of the upper bridge arm is turned on, the second resistor R2 slows down the rate of current change.

[0052] based on Figure 3 The circuitry within a system is integrated into a module, which is called a power module. A power module encapsulates multiple power devices (Insulated-Gate Bipolar Transistors, MOSFETs, and power diodes) in the same module, forming a circuit topology that meets the requirements. Power modules offer advantages such as high reliability, better heat dissipation, and high standardization. Their high integration simplifies system design and assembly. Therefore, power modules are commonly used for current and voltage control in high-power power electronic systems. A power module typically includes power devices, a heat-dissipating metal base plate, an insulating substrate, electrical connection terminals, bonding wires, molding compound, and an external protective housing. Different metallization patterns on the insulating substrate create different circuit topologies to achieve the desired functions.

[0053] based on Figure 3 The schematic diagram is provided to illustrate the integrated components provided in the embodiments of this application.

[0054] Figure 4 This illustration shows a structural diagram of a substrate and a patterned conductive layer in an integrated component provided in an embodiment of this application, such as... Figure 4 As shown, the integrated component provided in this application embodiment may include: a substrate 1, patterned conductive layers 2-12, power devices, and a buffer circuit. The power devices and buffer circuit are located in... Figure 4 The text is not shown in the provided text and can be combined with other text. Figure 5 Let's take a look. Figure 5 This diagram illustrates a distribution of components in an integrated component provided in an embodiment of this application.

[0055] Substrate 1 is an insulating substrate.

[0056] The patterned conductive layer 2-12 is located on one side of the substrate 1 and includes at least a first conductive pattern (the first conductive pattern may include the patterns marked 2 and 7 in the figure) and a second conductive pattern (the second conductive pattern may include the patterns marked 5 and 9 in the figure).

[0057] The patterned conductive layer 2-12 is a metallized pattern on the upper part of the substrate 1, which is generally copper plating.

[0058] The power devices (which may include power devices labeled 16 and 17 in the figures, where 16 represents eight power devices in parallel and 17 represents another eight power devices in parallel) are located on the side of the first conductive pattern (2 and 7) facing away from the substrate 1.

[0059] The buffer circuit (which may include devices labeled 19, 20, 24 and 25 in the figures) is located on the side of the second conductive pattern (5 and 9) facing away from the substrate 1, and the buffer circuit is connected to the power device.

[0060] It should be understood that the integrated component may also include a housing and a metal heat sink. The accompanying drawings of this application only show one phase of the power module as a typical example, and do not show the housing and metal heat sink.

[0061] In this embodiment, a first conductive pattern (2 and 7) and a second conductive pattern (5 and 9) are disposed on the same substrate 1. Power devices (16 and 17) are placed on the first conductive pattern (2 and 7), and buffer circuits (19, 20, 24 and 25) are placed on the second conductive pattern (5 and 9). The buffer circuits can be used to buffer problems such as electrical signal waveform oscillation and voltage overshoot spikes. In addition, integrating the power devices and the buffer circuits together results in high integration, and the relatively close distance between the buffer circuits and the power devices can improve the buffering effect.

[0062] Combination Figure 4 and Figure 5 In some embodiments, the first conductive pattern includes a first conductive pattern 2 and a first conductive pattern 7, and the second conductive pattern includes a second conductive pattern 9 and a second conductive pattern 5.

[0063] The power device includes power device A 17 and power device B 16. Power device A 17 is located on the side of the first conductive pattern 2 facing away from the substrate 1, and power device B 16 is located on the side of the first conductive pattern 7 facing away from the substrate 1.

[0064] The buffer circuit includes buffer circuit A (which includes devices labeled 19 and 20 in the attached figure) and buffer circuit B (which includes devices labeled 24 and 25 in the attached figure). Buffer circuit A (19 and 20) is located on the side of the second conductive pattern 9 facing away from the substrate 1, and buffer circuit B (24 and 25) is located on the side of the second conductive pattern 5 facing away from the substrate 1. Buffer circuit A (19 and 20) is connected to power device 17, and buffer circuit B (24 and 25) is connected to power device 16.

[0065] For example, power device 17 can be a power device of the upper bridge arm, that is, corresponding to Figure 3 S1 in the diagram. The surface of the drain electrode of power device 17, specifically the first conductive pattern 2, facing away from the substrate 1. Correspondingly, power device 16 can be a power device of the lower bridge arm, i.e., corresponding to... Figure 3 In S2, the drain of power device 16 is in close contact with the surface of the first conductive pattern 7 facing away from the substrate 1. The first conductive pattern 2 can also be called the upper bridge arm drain pattern, and the first conductive pattern 7 can also be called the upper bridge arm source pattern.

[0066] Buffer circuit A includes buffer resistor 19 and buffer capacitor 20, which are connected in series. Buffer circuit B includes buffer resistor 25 and buffer capacitor 24, which are connected in series.

[0067] For example, the resistors and capacitors in the RC buffer circuit of this application can both be surface mount components (SMT), wherein the location of buffer capacitor 20 is shown below. Figure 5 Its two pins are respectively on the first conductive pattern 2 and the second conductive pattern 9; the location of the buffer resistor 19 is shown below. Figure 5 Its two pins are on the second conductive pattern 9 and the first conductive pattern 7. That is, it is equivalent to the first buffer resistor 19 and the first buffer capacitor 20 being connected in series between the first conductive pattern 2 and the first conductive pattern 7.

[0068] The buffer capacitor 24 has its leads on the first conductive pattern 7 and the second conductive pattern 5, respectively. The buffer resistor 25 has its leads on the second conductive pattern 5 and the source conductive pattern 4, respectively. That is, the buffer resistor 25 and the buffer capacitor 24 are connected in series between the first conductive pattern 7 and the source conductive pattern 4.

[0069] The working principle of the RC snubber circuit is as follows: when voltage spikes and oscillations occur during the switching process of bridge arm A, they are absorbed by the snubber capacitor 20 connected in parallel to bridge arm A, and then the energy is released through the snubber resistor 19 while suppressing the oscillations generated by the snubber capacitor and the loop inductance; similarly, voltage spikes and oscillations occurring during the switching process of bridge arm B are absorbed by the snubber capacitor 24 connected in parallel to bridge arm B, and then the energy is released through the snubber resistor 25.

[0070] The placement of passive components in the buffer circuit of this application embodiment is not fixed, and the positions of its capacitors and resistors can be interchanged. However, it is necessary to consider that chip heating may affect the capacitor performance.

[0071] Since the overall process of power module manufacturing includes surface mount, soldering, and protection processes, the mounting of passive components in the buffer circuit follows the same process as the power components, without introducing any additional steps into the module production process. Furthermore, because the passive components are integrated within the power module, they have a better heat dissipation environment, allowing for a smaller package to achieve the buffering function.

[0072] In some embodiments, please refer to the reference Figure 4 , Figure 5 and Figure 6 The patterned conductive layer 2-12 also includes a source conductive pattern 4, which is connected to the source of the power device 16.

[0073] The first conductive pattern 2 is connected to the positive busbar connection structure DC+ through the first bonding wire 26;

[0074] The source electrode conductive pattern 4 is connected to the negative electrode busbar DC-connection structure via the second bonding line 27.

[0075] The first conductive pattern 7 is connected to the neutral connection structure AC via the third bonding line 28.

[0076] The bonding wire may include aluminum wire, copper wire, and aluminum strip, etc. The first bonding wire, the second bonding wire, and the third bonding wire can be selected arbitrarily from aluminum wire, copper wire, and aluminum strip.

[0077] In other examples, the first conductive pattern 2 (A) can be connected to the positive busbar connection structure DC+ via a first welding structure. The second source conductive pattern 4 (B) can be connected to the negative busbar connection structure DC- via a second welding structure. The first conductive pattern 7 (B) can be connected to the neutral line connection structure AC via a third welding structure. The welding structure can be an ultrasonic welding structure.

[0078] The positive bus connection structure DC+ and the negative bus connection structure DC- are located on a first side of the substrate 1 in the first direction X, and the neutral connection structure AC is located on a second side of the substrate 1 in the first direction X. For example, the first side is the left side of the substrate 1, and the second side is the right side of the substrate 1.

[0079] In this embodiment, the positive bus connection structure DC+ and the negative bus connection structure DC- are placed on one side of the substrate 1 in the first direction X, and the neutral line connection structure AC is placed on the other side of the substrate 1 in the first direction X. This can avoid interference between the positive bus connection structure DC+, the negative bus connection structure DC- and the neutral line connection structure AC.

[0080] Since the first conductive pattern 2 (A) is connected to the positive busbar connection structure DC+ via a first bonding wire or ultrasonic welding; the second source conductive pattern 4 (B) is connected to the negative busbar connection structure DC- via a second bonding wire or ultrasonic welding; and the first conductive pattern 7 (B) is connected to the neutral connection structure AC via a third bonding wire or ultrasonic welding, the buffer resistor 19 and the buffer capacitor 20 (A) are essentially connected in series between the positive busbar connection structure DC+ and the neutral connection structure AC. Similarly, the buffer resistor 25 (B) and the buffer capacitor 24 (B) are essentially connected in series between the neutral connection structure AC and the negative busbar connection structure DC-.

[0081] Thus, the buffer resistor A corresponds to 20. Figure 3 The first resistor R1 corresponds to the first capacitor C1, and the buffer capacitor 19 corresponds to the first capacitor C1. The second resistor R2 corresponds to the second buffer resistor 24, and the second capacitor C2 corresponds to the second buffer capacitor 25.

[0082] In this embodiment, buffer circuits A (19 and 20) are connected to power device A 17, and buffer circuits B (24 and 25) are connected to power device B 16. This ensures that each of the A and B bridge arms has a corresponding buffer circuit in the integrated assembly, enabling the A and B bridge arms to more effectively control voltage and current oscillations during commutation, reduce losses during power device switching, and improve the reliability of the power module.

[0083] In some embodiments, such as Figure 5 As shown, power device 17 is adjacent to buffer circuit 19 and 20, and power device 16 is adjacent to buffer circuit 24 and 25.

[0084] Because buffer circuits A (19 and 20) are connected to power device A (17), and buffer circuits B (24 and 25) are connected to power device B (16), and power device A (17) is positioned adjacent to buffer circuits A (19 and 20), and power device B (16) is positioned adjacent to buffer circuits B (24 and 25), the distance between the buffer circuits of bridge arm A and bridge arm A is short, and the distance between the buffer circuits of bridge arm B and bridge arm B is short. This reduces the length of the connecting lines, further reduces the generation of parasitic inductance, and effectively improves the performance of the buffer circuits.

[0085] In some embodiments, power device A 17 and power device B 16 are arranged in the first direction X, and power device A 17 and power device B 16 are spaced apart in the first direction X.

[0086] like Figure 5 As shown, power device A 17 and power device B 16 are arranged horizontally, and are spaced apart in the horizontal direction. This isolates power device A 17 and power device B 16 to avoid mutual interference.

[0087] In some embodiments, such as Figure 5 As shown, the multiple power devices 17 are divided into a first power device group and a second power device group. Both the first power device group and the second power device group include at least one power device 17. The first power device group and the second power device group are arranged in the second direction Y, which intersects with the first direction X.

[0088] Reference Figure 4 and Figure 5 The patterned conductive layer 2-12 also includes a gate conductive pattern 10, which is located between the first power device group and the second power device group in the second direction Y.

[0089] Combination Figures 4 to 6 As can be seen, the gate conductive pattern 10 is connected to the gate of the power device 17 via bonding wires.

[0090] And / or, the multiple power devices 16 are divided into a first power device group and a second power device group, each of which includes at least one power device 16, and the first power device group and the second power device group are arranged in the second direction Y.

[0091] The patterned conductive layer also includes a gate conductive pattern 6, which is located between the first power device group and the second power device group in the second direction Y.

[0092] Combination Figures 4 to 6 As can be seen, the gate conductive pattern 6 of device B is connected to the gate of power device B 16 through bonding wires.

[0093] In the integrated components of this application embodiment, the connection methods between power devices, passive devices (resistors and capacitors) and the patterned conductive layer can be the same mounting processes such as silver paste bonding, solder paste reflow soldering, and silver sintering, without introducing new process flows or increasing the complexity of the module assembly process. The connection methods between the upper surface of the power devices and the patterned conductive layer can be selected from processes such as bonding wires (aluminum wires, copper wires, aluminum strips) and copper sheet welding.

[0094] For example, such as Figure 5 As shown, Figure 5 It includes eight Class A power devices 17 and eight Class B power devices 16. The eight Class A power devices 17 are divided into a first group and a second group. The first group includes four Class A power devices 17, and the second group includes four Class A power devices 17. The first and second groups are arranged vertically. Figure 4 As can be seen, there is a gate conductive pattern 10 between the first A power device group and the second A power device group.

[0095] And / or, the eight power devices 16 are divided into a first power device group and a second power device group. The first power device group includes four power devices 16, and the second power device group includes four power device groups 16. The first power device group and the second power device group are arranged vertically. There is a gate conductive pattern 6 between the first power device group and the second power device group.

[0096] Power devices within each power device group can be arranged adjacent to each other.

[0097] In this embodiment, the A and B bridge arms are separated laterally to avoid mutual interference; and the multiple parallel power devices of the A and / or B bridge arms are divided into two groups vertically, with gate conductive patterns provided between them. The power devices in both groups can be connected to the gate patterns nearby, which is beneficial for heat dissipation.

[0098] Figure 6 This example uses eight power devices connected in parallel, but it is not intended to limit this application. The integrated components provided in this application have general applicability and are not limited to eight power devices connected in parallel. That is to say, the patterned conductive layer for high parallel number module design provided in this application can not only be used to design eight parallel power devices, but also accommodate internal layout designs with lower parallel numbers. A typical internal layout design for six parallel power devices is shown below. Figure 7 As shown, a typical internal layout design of four parallel power devices is as follows: Figure 8 As shown. The arrangement of its power devices can be the same as that in the above embodiment, and will not be described again here.

[0099] In some embodiments, please refer to the reference Figure 4 and Figure 5 The patterned conductive layer 2-12 also includes a third B conductive pattern 3, a B source conductive pattern 4, a third A conductive pattern 12, and a fourth A conductive pattern 11. All of the above conductive patterns are located on one side of the substrate.

[0100] On the side of power device A 17 away from power device B 16, there are gate terminal A 22, source terminal A 21 and drain terminal A connected to power device A 17.

[0101] In some embodiments, gate terminal 22 is located on the side of the fourth conductive pattern 11 facing away from the substrate, source terminal 21 is located on the side of the first conductive pattern 7 facing away from the substrate, and drain terminal 23 may be located on the side of the third conductive pattern 12 and / or the first conductive pattern 2 facing away from the substrate. Drain terminal 23 is connected to the first conductive pattern 2 via bonding wires. The side of the first conductive pattern 2 facing away from the substrate 1 is in close contact with the drain of the power device 17.

[0102] On the side of power device B 16 away from power device A 17, there is a gate terminal B 14, a source terminal B 13, and a drain terminal B connected to power device B 16.

[0103] In some embodiments, the B gate terminal 14 is located on the side of the B gate conductive pattern 6 facing away from the substrate; the B source terminal 13 is located on the side of the B source conductive pattern 4 facing away from the substrate; and the B drain terminal 15 is located on the side of the third B conductive pattern 3 facing away from the substrate. The B drain terminal 15 is connected to the first B conductive pattern 7 via a bonding wire. The side of the first B conductive pattern facing away from the substrate 1 is in close contact with the drain of the B power device 16. By providing these terminals, it is convenient to input signals to these terminals to facilitate the testing of the power device. In addition, the terminals of the A and B bridge arms are set separately to avoid mutual interference.

[0104] In some embodiments, combined with Figure 4 and Figure 5 The patterned conductive layer 2-12 also includes a third conductive pattern 8, and a temperature test terminal 18 is provided on the side of the third conductive pattern 8 facing away from the substrate 1.

[0105] For example, the temperature test terminal 18 may include a thermistor test terminal, which can measure the temperature of the integrated component, thereby avoiding safety hazards caused by excessive circuit temperature.

[0106] In some embodiments, the power device includes a drain and a source, with the drain of the power device facing the first conductive pattern (2 and 7) and the source of the power device facing away from the first conductive pattern (2 and 7).

[0107] Combination Figure 4 and Figure 6 The patterned conductive layer also includes source conductive patterns (4 and 7), and the source of the power device and the source conductive patterns (4 and 7) are connected by bonding wires.

[0108] Based on the same inventive concept, embodiments of this application also provide an electronic device, which includes the integrated components of any of the foregoing embodiments. It is understood that the electronic device possesses the beneficial effects of the integrated components provided in the embodiments of this application, namely, it can improve the performance of buffer circuits, simplify the manufacturing process, and avoid introducing additional process steps into the module manufacturing process.

[0109] It should be noted that in the embodiments shown in the figures above, the resistor is presented as a single resistor, and the capacitor as a single capacitor. In other embodiments, the resistor may be an integrated combination of series, parallel, or mixed resistors, and the capacitor may be an integrated combination of series, parallel, or mixed capacitors. The specific parameters of each device can be set according to actual needs, and this application does not limit this.

[0110] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other.

[0111] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An integrated component, characterized in that, include: substrate; A patterned conductive layer is located on one side of the substrate and includes at least a first conductive pattern and a second conductive pattern. A power device is located on the side of the first conductive pattern that faces away from the substrate; A buffer circuit is located on the side of the second conductive pattern facing away from the substrate, and the buffer circuit is connected to the power device.

2. The integrated component according to claim 1, characterized in that, The first conductive pattern includes a first conductive pattern A and a first conductive pattern B, and the second conductive pattern includes a second conductive pattern A and a second conductive pattern B; The power device includes power device A and power device B. Power device A is located on the side of the first conductive pattern A that faces away from the substrate, and power device B is located on the side of the first conductive pattern B that faces away from the substrate. The buffer circuit includes buffer circuit A and buffer circuit B. Buffer circuit A is located on the side of the second conductive pattern A facing away from the substrate, and buffer circuit B is located on the side of the second conductive pattern B facing away from the substrate. Buffer circuit A is connected to the power device A, and buffer circuit B is connected to the power device B.

3. The integrated component according to claim 2, characterized in that, The power device A is adjacent to the buffer circuit A, and the power device B is adjacent to the buffer circuit B.

4. The integrated component according to claim 2, characterized in that, The power device A and the power device B are arranged in a first direction, and the power device A and the power device B are spaced apart in the first direction.

5. The integrated component according to claim 4, characterized in that, The plurality of power devices are divided into a first power device group and a second power device group. Both the first power device group and the second power device group include at least one power device. The first power device group and the second power device group are arranged in a second direction, which intersects with the first direction. The patterned conductive layer further includes a gate conductive pattern, which is located between the first power device group and the second power device group in the second direction. And / or, the plurality of said power devices are divided into a first power device group and a second power device group, each of the first power device group and the second power device group including at least one said power device, and the first power device group and the second power device group are arranged in a second direction; The patterned conductive layer further includes a gate conductive pattern, which is located between the first power device group and the second power device group in the second direction.

6. The integrated component according to claim 4, characterized in that, On the side of the power device A away from the power device B, there is a gate terminal A, a source terminal A, and a drain terminal A connected to the power device A; On the side of the power device B that is away from the power device A, there is a gate terminal B, a source terminal B, and a drain terminal B connected to the power device B.

7. The integrated component according to claim 2, characterized in that, The patterned conductive layer further includes a source conductive pattern, which is connected to the source of the power device. The first conductive pattern is connected to the positive electrode busbar connection structure via a first bonding wire or a first welding structure. The source electrode conductive pattern is connected to the negative electrode busbar connection structure through a second bonding wire or a second welding structure. The first conductive pattern is connected to the centerline connection structure via a third bonding wire or a third welding structure. The positive busbar connection structure and the negative busbar connection structure are located on the first side of the substrate in the first direction, and the neutral line connection structure is located on the second side of the substrate in the first direction.

8. The integrated component according to claim 1, characterized in that, The patterned conductive layer also includes a third conductive pattern, and a temperature test terminal is provided on the side of the third conductive pattern facing away from the substrate.

9. The integrated component according to claim 1, characterized in that, The power device includes a drain and a source, with the drain of the power device facing the first conductive pattern and the source of the power device facing away from the first conductive pattern. The patterned conductive layer also includes a source conductive pattern, and the source of the power device and the source conductive pattern are connected by bonding wires.

10. An electronic device, characterized in that, Includes the integrated components as described in any one of claims 1 to 9.

Images