Digital-to-analog converter, data driving circuit and display device

Abstract

The utility model provides a digital-to-analog converter, a data driving circuit and a display device. The digital-to-analog converter disposed in the data driving circuit of the display device includes a gamma reference voltage generator that outputs a gamma reference voltage in response to a first set of signals among digital signals, a voltage selector outputting one of the gamma reference voltages as a gamma selection voltage in response to a second set of signals in the digital signals, a first amplifier receiving the gamma selection voltage and outputting a first conversion voltage, a booster circuit that converts the first converted voltage to a second converted voltage in response to the first set of signals in the digital signal, and a second amplifier that receives the second converted voltage and outputs an analog signal.

Description

TECHNICAL FIELD

[0001] The present utility model relates to display devices, and more particularly to a digital-to-analog converter, a data driving circuit including the same, and a display device including the data driving circuit. BACKGROUND

[0002] Electronic devices such as smartphones, digital cameras, notebook computers, navigation, displays, and smart TVs that provide images to users include display devices for displaying images. The display devices generate images and provide the generated images to the users through display screens.

[0003] The display device includes a display panel, a data driving circuit, and a driving controller. The driving controller provides an image data signal. The data driving circuit can provide a data signal corresponding to the image data signal to the display panel. SUMMARY

[0004] The present utility model aims to provide a digital-to-analog converter having a reduced size, and a data driving circuit and a display device including the same.

[0005] According to a feature of the utility model for achieving the above-mentioned purpose, the digital-to-analog converter includes a gamma reference voltage generator that outputs gamma reference voltages in response to a first group of signals in a digital signal, a voltage selector that outputs one of the gamma reference voltages as a gamma selection voltage in response to a second group of signals in the digital signal, a first amplifier that receives the gamma selection voltage and outputs a first conversion voltage, a boost circuit that converts the first conversion voltage to a second conversion voltage in response to the first group of signals in the digital signal, and a second amplifier that receives the second conversion voltage and outputs an analog signal.

[0006] In an embodiment, the gamma reference voltage generator can include a first voltage generator that generates a first gamma reference voltage in response to the first group of signals in the digital signal, and a second voltage generator that generates a second gamma reference voltage in response to the first group of signals in the digital signal. One of the first gamma reference voltage and the second gamma reference voltage can be output as the gamma reference voltage.

[0007] In an embodiment, the first voltage generator can include a first resistor string of a plurality of resistors for generating the first gamma reference voltage, and a first switch circuit that outputs the first gamma reference voltage as the gamma reference voltage in response to the first group of signals in the digital signal.

[0008] In an embodiment, the plurality of resistors of the first resistor string can have resistance values different from each other.

[0009] In an embodiment, the second voltage generator can include a second resistance string of a plurality of resistances for generating the second gamma reference voltage, a second switch circuit outputting a portion of the second gamma reference voltage as the gamma reference voltage, a third switch circuit outputting a portion of the second gamma reference voltage as the gamma reference voltage, and a fourth switch circuit outputting a portion of the second gamma reference voltage as the gamma reference voltage. One of the second switch circuit, the third switch circuit, and the fourth switch circuit can operate in response to the first group of signals in the digital signal.

[0010] In an embodiment, the plurality of resistances of the second resistance string can have the same resistance values as each other.

[0011] In an embodiment, the boost circuit can include a first capacitor connected between a first node receiving the first converted voltage and a second node, and a boost switch circuit transmitting one of a plurality of boosted voltages to the second node in response to the first group of signals in the digital signal.

[0012] In an embodiment, the boost switch circuit can include a first boost switch connected between the second node and a first voltage terminal, and a second boost switch connected between the second node and a second voltage terminal. One of the first boost switch and the second boost switch can be turned on in response to the first group of signals in the digital signal.

[0013] In an embodiment, the boost switch circuit can further include a second capacitor connected between the first node and a ground terminal.

[0014] In an embodiment, the first capacitor can be a MOS capacitor.

[0015] In an embodiment, the second amplifier can include a first input terminal receiving the second converted voltage, a second input terminal, and an output terminal outputting the analog signal, and the second input terminal and the output terminal can be electrically connected.

[0016] In an embodiment, the boost circuit can further include a first switch connected between an output terminal of the first amplifier and the first node, a second switch connected between the first node and a third node, a third switch connected between a voltage terminal receiving a reference voltage and the third node, and a fourth switch connected between the second node and the second input terminal of the second amplifier. The first input terminal of the second amplifier can be connected with the third node, each of the first switch, the third switch, and the fourth switch can be turned on in response to a reset signal, and the second switch can be turned on in response to an inverse reset signal.

[0017] In an embodiment, the second amplifier can include a first input terminal receiving the second conversion voltage, a second input terminal, and an output terminal outputting the analog signal and electrically connected with the second input terminal. The boost circuit can further include a first capacitor connected between a first node and a second node, a boost switch circuit transmitting one of a plurality of boost voltages to the first node in response to the first group of signals in the digital signal, a first switch connected between an output terminal of the first amplifier and the second node, a second switch connected between the first node and a third node, a third switch connected between a voltage terminal receiving a reference voltage and the third node, and a fourth switch connected between the second node and the second input terminal of the second amplifier. The first input terminal of the second amplifier can be connected with the third node, each of the third switch and the fourth switch can be turned on in response to a reset signal, and each of the first switch and the second switch can be turned on in response to an inverse reset signal.

[0018] A data driving circuit according to a feature of the present application includes a digital-to-analog converter converting an image data signal into an analog signal, and a demultiplexer outputting the analog signal as a data signal. The digital-to-analog converter includes a gamma reference voltage generator outputting a gamma reference voltage in response to a first group of signals in the image data signal, a voltage selector outputting one of the gamma reference voltages as a gamma selection voltage in response to a second group of signals in the image data signal, a first amplifier receiving the gamma selection voltage and outputting a first conversion voltage, a boost circuit converting the first conversion voltage into a second conversion voltage in response to the first group of signals in the image data signal, and a second amplifier receiving the second conversion voltage and outputting the analog signal.

[0019] In an embodiment, the gamma reference voltage generator can include a first voltage generator to generate a first gamma reference voltage in response to the first set of signals in the image data signal, and a second voltage generator to generate a second gamma reference voltage in response to the first set of signals in the image data signal. One of the first gamma reference voltage and the second gamma reference voltage can be output as the gamma reference voltage.

[0020] In an embodiment, the boost circuit can include a first capacitor connected between a first node receiving the first converted voltage and a second node, and a boost switch circuit to transfer one of a plurality of boost voltages to the second node in response to the first set of signals in the image data signal.

[0021] A display apparatus according to a feature of the present disclosure includes a display panel, a scan driving circuit to provide a scan signal to the display panel, a data driving circuit to provide a data signal to the display panel, and a driving controller to provide an image data signal to the data driving circuit. The data driving circuit includes a digital-to-analog converter to convert the image data signal into an analog signal, and a demultiplexer to output the analog signal as the data signal. The digital-to-analog converter includes a gamma reference voltage generator to output a gamma reference voltage in response to a first set of signals in the image data signal, a voltage selector to output one of the gamma reference voltages as a gamma selection voltage in response to a second set of signals in the image data signal, a first amplifier to receive the gamma selection voltage and output a first converted voltage, a boost circuit to convert the first converted voltage into a second converted voltage in response to the first set of signals in the image data signal, and a second amplifier to receive the second converted voltage and output the analog signal.

[0022] In an embodiment, the gamma reference voltage generator can include a first voltage generator to generate a first gamma reference voltage in response to the first set of signals in the image data signal, and a second voltage generator to generate a second gamma reference voltage in response to the first set of signals in the image data signal. One of the first gamma reference voltage and the second gamma reference voltage can be output as the gamma reference voltage.

[0023] In an embodiment, the boost circuit can include a first capacitor connected between a first node receiving the first converted voltage and a second node, and a boost switch circuit to transfer one of a plurality of boost voltages to the second node in response to the first set of signals in the image data signal.

[0024] In an embodiment, the first capacitor can be a MOS capacitor.

[0025] The digital-to-analog converter having the configuration as described above can operate at a low voltage, and can include a resistance string having a reduced number of resistors to convert a digital signal into an analog signal. Accordingly, a circuit area of a data driving circuit and a display device can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a block diagram of a display device according to an embodiment of the present application.

[0027] Figure 2 is a diagram illustrating a data driving circuit according to an embodiment of the present application.

[0028] Figure 3 is a diagram exemplarily illustrating a first voltage generator.

[0029] Figure 4 is a diagram exemplarily illustrating a second voltage generator.

[0030] Figure 5 is a timing diagram for explaining an operation of the data driving circuit shown in Figure 2

[0031] Figure 6 is a circuit diagram of a boost circuit according to an embodiment of the present application.

[0032] Figure 7 is a circuit diagram of a boost circuit according to an embodiment of the present application.

[0033] Figure 8 is a circuit diagram of a boost circuit and a second amplifier according to an embodiment of the present application.

[0034] Figure 9 is a circuit diagram of a boost circuit and a second amplifier according to an embodiment of the present application.

[0035] Figure 10 is a diagram exemplarily illustrating voltage levels of analog signals according to gray scale levels of image data signals.

[0036] Figure 11 is a diagram exemplarily illustrating emission current errors of pixels according to gray scale levels of image data signals.

[0037] EXPLANATION OF REFERENCE NUMERALS

[0038] DD: display device DP: display panel

[0039] 100: driving controller 200: data driving circuit

[0040] ​300: scan driving circuit 400: voltage generator

[0041] 500: gamma reference voltage generator 510: first voltage generator

[0042] 520: second voltage generator 530: voltage selector

[0043] 540: first amplifier 550: voltage boosting circuit

[0044] 560: second amplifier 570: demultiplexer DETAILED DESCRIPTION

[0045] In the present specification, in the case where it is mentioned that a certain constituent element (or a region, a layer, a part, etc.) is "on" another constituent element, is "connected to" or "joined to" another constituent element, it means that the certain constituent element can be directly disposed / connected / joined to the other constituent element, or a third constituent element can be further disposed between them.

[0046] The same reference numerals are used to designate the same constituent elements. Also, in the drawings, the thickness, ratio, and size of the constituent elements are exaggerated for the effective explanation of the technical content. "And / or" includes all of one or more combinations of the constituent elements related to each other.

[0047] The first, second, and the like terms can be used to explain a variety of constituent elements, but the constituent elements are not limited to the terms. The terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, a first constituent element can be referred to as a second constituent element, and similarly, a second constituent element can also be referred to as a first constituent element, without departing from the scope of the present disclosure. The singular representation includes the plural representation unless it is explicitly stated in the context.

[0048] Also, the terms "below", "lower", "above", "upper", and the like are used to explain the relative relationship of the constituent elements shown in the drawings. The terms are relative concepts, which are explained based on the direction shown in the drawings.

[0049] The terms "include" or "have" and the like should be understood as intending to designate the presence of features, numbers, steps, operations, constituent elements, components, or combinations thereof described in the specification, and not precluding the presence or possibility of one or more other features, numbers, steps, operations, constituent elements, components, or combinations thereof.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification have the same meaning as commonly understood by one of ordinary skill in the art to which this practical new type belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly idealized or formal sense unless expressly so defined herein.

[0051] Hereinafter, embodiments of the present practical new type will be described with reference to the accompanying drawings.

[0052] Figure 1 is a block diagram of a display device DD according to an embodiment of the present practical new type.

[0053] Referring to Figure 1 , the display device DD includes a driving controller 100, a data driving circuit 200, a scan driving circuit 300, a voltage generator 400, and a display panel DP.

[0054] The driving controller 100 receives an input image signal RGB and a control signal CTRL. The driving controller 100 provides a data control signal DCS and an image data signal DS to the data driving circuit 200. The driving controller 100 provides a scan control signal SCS to the scan driving circuit 300.

[0055] The data driving circuit 200 receives the data control signal DCS and the image data signal DS from the driving controller 100. The data driving circuit 200 converts the image data signal DS into a data signal, and outputs the data signal to a plurality of data lines DL1 to DLm described later. The data signal is an analog voltage corresponding to the image data signal DS.

[0056] The scan driving circuit 300 receives the scan control signal SCS from the driving controller 100. The scan driving circuit 300 outputs a scan signal to a plurality of scan lines SL1 to SLn described later. In an embodiment, the scan signals provided to the plurality of scan lines SL1 to SLn can be sequentially shifted to an active level.

[0057] The display panel DP according to an embodiment of the present practical new type can be a light emitting type display panel. For example, the display panel DP can be an organic light emitting display panel, an inorganic light emitting display panel, or a quantum dot light emitting display panel. The light emitting layer of the organic light emitting display panel can include an organic light emitting substance. The light emitting layer of the inorganic light emitting display panel can include an inorganic light emitting substance. The light emitting layer of the quantum dot light emitting display panel can include quantum dots, quantum rods, or the like. Hereinafter, in the present embodiment, the display panel DP is explained as an organic light emitting display panel.

[0058] The display panel DP includes scan lines SL1 to SLn, data lines DL1 to DLm, and pixels PX.

[0059] Each of the pixels PX can be connected with a corresponding one of the scan lines SL1 to SLn, and with a corresponding one of the data lines DL1 to DLm. Although one pixel PX is shown as being connected with one scan line in Figure 1 , the present application is not limited thereto. One pixel PX can be electrically connected with two or more scan lines.

[0060] Each of the pixels PX can include a light emitting element (not shown) and a pixel circuit (not shown) that controls light emission of the light emitting element. In an embodiment, the light emitting element can be an organic light emitting diode. However, the present application is not limited thereto.

[0061] The scan lines SL1 to SLn extend from the scan driving circuit 300 in the first direction DR1, and are arranged to be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend from the data driving circuit 200 in the second direction DR2, and are arranged to be spaced apart from each other in the first direction DR1.

[0062] The scan driving circuit 300 can be disposed on the display panel DP. In an embodiment, the pixels PX can be disposed in a display area DA of the display panel DP, and the scan driving circuit 300 can be disposed in a non-display area NDA. In an embodiment, the scan driving circuit 300 can be formed by the same process as the pixel circuit of each of the pixels PX, but the present application is not limited thereto.

[0063] The voltage generator 400 provides voltages required for operation of the display panel DP, for example, a first voltage ELVDD, a second voltage ELVSS, and a third voltage VINT. The number of voltages generated by the voltage generator 400 can be variously changed.

[0064] Figure 2 is a diagram illustrating a data driving circuit according to an embodiment of the present application. Figure 3 is a diagram exemplarily illustrating a first voltage generator. Figure 4 is a diagram exemplarily illustrating a second voltage generator.

[0065] Referring to Figure 2 , the data driving circuit 200 includes a digital-to-analog converter and a demultiplexer 570. The digital-to-analog converter includes a gamma reference voltage generator 500, a voltage selector 530, a first amplifier 540, a boost circuit 550, and a second amplifier 560. In an embodiment, each of the first amplifier 540 and the second amplifier 560 can operate as a buffer.

[0066] The gamma reference voltage generator 500 outputs a plurality of gamma reference voltages in response to a first group of signals among the digital signals. In an embodiment, the digital signals are the image data signals DS, and the first group of signals are the uppermost 2-bit signals DS<7:6> of the image data signals DS. The gamma reference voltage generator 500 can select one of the first gamma reference voltage VG1 and the second gamma reference voltage VG2 and output the plurality of gamma reference voltages.

[0067] The gamma reference voltage generator 500 includes a first voltage generator 510 and a second voltage generator 520. The first voltage generator 510 outputs the first gamma reference voltage VG1 in response to the uppermost 2-bit signals DS<7:6> of the image data signals DS. The second voltage generator 520 outputs the second gamma reference voltage VG2 in response to the uppermost 2-bit signals DS<7:6> of the image data signals DS.

[0068] Referring to Figure 3 The first voltage generator 510 includes a first resistance string 511 and a first switch circuit 512. The first resistance string 511 includes a plurality of resistors Rs1, Rs2, …, Rs63, Rs64 connected in series between a lowest voltage (e.g., 0 V) and a first highest voltage (e.g., 1.2 V). Although it is shown in Figure 3 that the first resistance string 511 includes 64 resistors Rs1, Rs2, …, Rs63, Rs64, the present application is not limited thereto. The number of resistors included in the first resistance string 511 can be variously changed. In an embodiment, each of the resistors Rs1, Rs2, …, Rs63, Rs64 can have a resistance value different from each other.

[0069] The first switch circuit 512 includes a plurality of first switches Ss1, Ss2, …, Ss63, Ss64. Although it is shown in Figure 3 that the first switch circuit 512 includes 64 first switches Ss1, Ss2, …, Ss63, Ss64, the present application is not limited thereto. The number of first switches included in the first switch circuit 512 can be variously changed.

[0070] In an embodiment, the first resistance string 511 can output the voltage of each of the connection nodes between the resistors Rs1, Rs2, …, Rs63, Rs64 as the first gamma reference voltages VG1<0>, VG1<1>, …, VG1<62>, VG1<63>. For example, the lowest voltage can be output as the first gamma reference voltage VG1<0>. For example, the voltage of the connection node between the resistors Rs1, Rs2 can be output as the first gamma reference voltage VG1<1>. Also, the voltage of the connection node between the resistors Rs63, Rs64 can be output as the first gamma reference voltage VG1<63>.

[0071] The first switch circuit 512 can output the first gamma reference voltages VG1<0>, VG1<1>, …, VG1<62>, VG1<63> from the first resistance string 511 as the gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63> in response to the uppermost 2-bit signals DS<7:6> of the image data signal DS. The gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63> output from the first switch circuit 512 can be provided to the voltage selector 530 shown in FIG. 5 as the first gamma reference voltages VG1. Figure 2

[0072] Referring to Figure 4 , the second voltage generator 520 includes a second resistance string 521, a second switch circuit 522, a third switch circuit 523, and a fourth switch circuit 524. The second resistance string 521 includes a plurality of resistors Rt1, Rt2, …, Rt127, Rt128 connected in series between a lowest voltage (e.g., 0 V) and a second highest voltage (e.g., 0.4 V). Although it is shown in FIG. 5 that the second resistance string 521 includes 128 resistors Rt1, Rt2, …, Rt127, Rt128, the present disclosure is not limited thereto. The number of resistors included in the second resistance string 521 can be variously changed. In an embodiment, each of the resistors Rt1, Rt2, …, Rt127, Rt128 can have the same resistance value as each other. Figure 4

[0073] The second switch circuit 522 includes a plurality of second switches St1, St2, …, St63, St64. Although it is shown in FIG. 5 that the second switch circuit 522 includes 64 second switches St1, St2, …, St63, St64, the present disclosure is not limited thereto. The number of second switches included in the second switch circuit 522 can be variously changed. Figure 4

[0074] In an embodiment, the second resistance string 521 can output the second gamma reference voltages in each of the connection nodes between the resistors Rt1, Rt2, …, Rt127, Rt128. For example, the second resistance string 521 can output 128 second gamma reference voltages.

[0075] ​​​The second switch circuit 522 can output 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> among the 128 second gamma reference voltages from the second resistance string 521 as gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63> in response to upper 2 bits of the image data signal DS DS<7:6>. The gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63> output from the second switch circuit 522 can be provided as a second gamma reference voltage VG21 to the voltage selector 530 illustrated in FIG. 6. Figure 2 The second gamma reference voltage VG21 can be provided to the voltage selector 530 illustrated in FIG. 6.

[0076] Some of the 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected by the second switch circuit 522 can be voltages identical to each other.

[0077] Although not illustrated, each of the third switch circuit 523 and the fourth switch circuit 524 can include a circuit configuration similar to that of the second switch circuit 522. That is, the third switch circuit 523 can output 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> among the 128 second gamma reference voltages from the second resistance string 521 as gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63>. The gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63> output from the third switch circuit 523 can be provided as a second gamma reference voltage VG22 to the voltage selector 530 illustrated in FIG. 6. Some of the 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected by the third switch circuit 523 can be voltages identical to each other. Figure 2

[0078] The fourth switch circuit 524 can output 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> among the 128 second gamma reference voltages from the second resistance string 521 as gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63>. The gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63> output from the fourth switch circuit 524 can be provided as a second gamma reference voltage VG23 to the voltage selector 530 illustrated in FIG. 6. Some of the 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected by the fourth switch circuit 524 can be voltages identical to each other. Figure 2 The second gamma reference voltage VG23 can be provided to the voltage selector 530 illustrated in FIG. 6.​

[0079] In an embodiment, the 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected by the second switch circuit 522 can be different voltages from the 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected by the third switch circuit 523 and the 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected by the fourth switch circuit 524. Also, the 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected by the third switch circuit 523 can be different voltages from the 64 second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected by the fourth switch circuit 524.

[0080] Referring to Figure 3 and Figure 4 If the upper two bits of the image data signal DS, DS<7:6> are "00", the first switch circuit 512 can output the first gamma reference voltages VG1<0>, VG1<1>, …, VG1<62>, VG1<63> from the first resistor string 511 as the gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63>. That is, when the gray scale level of the image data signal DS corresponds to from 1 gray scale level to 64 gray scale level, the first switch circuit 512 can output the gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63>.

[0081] If the upper two bits of the image data signal DS, DS<7:6> are "01", the second switch circuit 522 can output the second gamma reference voltages VG2<0>, VG2<1>, …, VG2<62>, VG2<63> selected from the 128 second gamma reference voltages of the second resistor string 521 as the gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63>. That is, when the gray scale level of the image data signal DS corresponds to from 65 gray scale level to 128 gray scale level, the second switch circuit 522 can output the gamma reference voltages VG<0>, VG<1>, …, VG<62>, VG<63>.

[0082] If the upper two bits of the image data signal DS, DS<7:6>, are "10", the third switch circuit 523 can output the second gamma reference voltages VG2<0>, VG2<1>,..., VG2<62>, VG2<63> selected from the 128 second gamma reference voltages of the second resistor string 521 as the gamma reference voltages VG<0>, VG<1>,..., VG<62>, VG<63>. That is, when the gray scale level of the image data signal DS corresponds to from 129 gray scale level to 192 gray scale level, the third switch circuit 523 can output the gamma reference voltages VG<0>, VG<1>,..., VG<62>, VG<63>.

[0083] If the upper two bits of the image data signal DS, DS<7:6>, are "11", the fourth switch circuit 524 can output the second gamma reference voltages VG2<0>, VG2<1>,..., VG2<62>, VG2<63> selected from the 128 second gamma reference voltages of the second resistor string 521 as the gamma reference voltages VG<0>, VG<1>,..., VG<62>, VG<63>. That is, when the gray scale level of the image data signal DS corresponds to from 193 gray scale level to 256 gray scale level, the fourth switch circuit 524 can output the gamma reference voltages VG<0>, VG<1>,..., VG<62>, VG<63>.

[0084] Referring again to Figure 2 , the voltage selector 530 outputs one of the plurality of gamma reference voltages VG<0>, VG<1>,..., VG<62>, VG<63> as a gamma selection voltage VSEL in response to a second set of signals in a digital signal. In one embodiment, the digital signal is the image data signal DS, and the second set of signals is the lower six bits of the image data signal DS, DS<5:0>.

[0085] That is, the voltage selector 530 can output one of the plurality of gamma reference voltages VG<0>, VG<1>,..., VG<62>, VG<63> as the gamma selection voltage VSEL in response to the lower six bits of the image data signal DS, DS<5:0>.

[0086] The plurality of gamma reference voltages VG<0>, VG<1>,..., VG<62>, VG<63> can be one of first gamma reference voltages VG1 provided from the first voltage generator 510 and second gamma reference voltages VG2 provided from the second voltage generator 520.

[0087] The first amplifier 540 includes a first input terminal (+) that receives the gamma selection voltage VSEL and a second input terminal (-) that is connected to an output terminal. The first amplifier 540 receives the gamma selection voltage VSEL and outputs a first conversion voltage V_RDAC.

[0088] The boost circuit 550 converts the first conversion voltage V_RDAC into a second conversion voltage V_STDAC in response to a first group of signals in the digital signal. The first group of signals in the digital signal can be uppermost 2-bit signals DS<7:6> of the image data signal DS.

[0089] The boost circuit 550 includes a switch SW1, a capacitor C_S, and a boost switching circuit. The boost switching circuit includes boost switches Sg1, Sg2, Sg3, Sg4.

[0090] The switch SW1 is connected between the output terminal of the first amplifier 540 and a first node N1 and operates in response to a reset signal RST.

[0091] The capacitor C_S is connected between the first node N1 and a second node N2.

[0092] The boost switch Sg1 is connected between the second node N2 and a first voltage terminal VIN1. The boost switch Sg2 is connected between the second node N2 and a second voltage terminal VIN2. The boost switch Sg3 is connected between the second node N2 and a third voltage terminal VIN3. The boost switch Sg4 is connected between the second node N2 and a fourth voltage terminal VIN4. A voltage of the second node N2 is V_STU.

[0093] The first voltage terminal VIN1, the second voltage terminal VIN2, the third voltage terminal VIN3, and the fourth voltage terminal VIN4 receive a first boost voltage GND, a second boost voltage VGAMH1, a third boost voltage VGAMH2, and a fourth boost voltage VGAMH3, respectively. In an embodiment, the first boost voltage GND, the second boost voltage VGAMH1, the third boost voltage VGAMH2, and the fourth boost voltage VGAMH3 can be provided from the voltage generator 400 shown in FIG. 4. Figure 1 A voltage level of each of the first boost voltage GND, the second boost voltage VGAMH1, the third boost voltage VGAMH2, and the fourth boost voltage VGAMH3 can have a relationship of GND < VGAMH1 < VGAMH2 < VGAMH3.

[0094] The step-up switches Sgl, Sg2, Sg3, Sg4 can operate in response to the upper 2-bit signal DS<7:6> of the image data signal DS. For example, if the upper 2-bit signal DS<7:6> of the image data signal DS is "00", the step-up switch Sgl is turned on. If the upper 2-bit signal DS<7:6> of the image data signal DS is "01", the step-up switch Sg2 is turned on. If the upper 2-bit signal DS<7:6> of the image data signal DS is "10", the step-up switch Sg3 is turned on. If the upper 2-bit signal DS<7:6> of the image data signal DS is "11", the step-up switch Sg4 is turned on.

[0095] The second amplifier 560 includes a first input terminal (+) that receives the second conversion voltage V_STDAC of the first node Nl, and a second input terminal (-) connected to an output terminal. The second amplifier 560 receives the second conversion voltage V_STDAC and outputs an analog signal V_OUT.

[0096] The demultiplexer 570 outputs the analog signal V_OUT as one of the data signals DR, DG, DB in response to a selection signal SEL_RGB.

[0097] Figure 5 is a timing chart for explaining the operation of the data drive circuit shown in Figure 2

[0098] Referring to Figure 1 , Figure 2 and Figure 5 If the reset signal RST is high, the switch SWl is turned on. At this time, the first conversion voltage V_RDAC corresponding to the upper 2-bit signal DS<7:6> of the image data signal DS and the lower 6-bit signal DS<5:0> of the image data signal DS can be transmitted to the first node Nl.

[0099] In addition, if one of the step-up switches Sgl, Sg2, Sg3, Sg4 is turned on in response to the upper 2-bit signal DS<7:6> of the image data signal DS, the voltage V_STU of the second node N2 changes to one of the first step-up voltage GND, the second step-up voltage VGAMHl, the third step-up voltage VGAMH2, and the fourth step-up voltage VGAMH3. At this time, the second conversion voltage V_STDAC of the first node Nl is step-up from the first conversion voltage V_RDAC by the capacitor C_S by the voltage V_STU of the second node N2.

[0100] As a result, the analog signal V_OUT output from the second amplifier 560 can correspond to a voltage level corresponding to the second conversion voltage V_STDAC of the first node Nl. ​

[0101] During the period in which the scan signal S1 provided by the scan line SL1 is at a high level, i.e., during the 1st period T, the demultiplexer 570 can output the analog signal V_OUT as the data signals DR, DG, DB in turn in response to the selection signal SEL_RGB.

[0102] As described above, the digital-to-analog converter can operate in 2 phases.

[0103] During the first phase, the digital signal in the voltage of the first resistance string 511 and the second resistance string 521, i.e., the voltage corresponding to the image data signal DS, is output as the first conversion voltage V_RDAC.

[0104] During the second phase, the second conversion voltage V_STDAC is generated which stacks up one of the first boost voltage GND, the second boost voltage VGAMH1, the third boost voltage VGAMH2, and the fourth boost voltage VGAMH3 on the first conversion voltage V_RDAC at the first node N1, and the analog signal V_OUT corresponding to the second conversion voltage V_STDAC is output. In an embodiment, although the first boost voltage GND is a ground voltage, the present application is not limited thereto. The first boost voltage GND can be a voltage level different from the ground voltage.

[0105] Since each of the first resistance string 511 and the second resistance string 521 operates at a low voltage, it is possible to reduce the power consumption in each of the first resistance string 511 and the second resistance string 521.

[0106] The first resistance string 511 of 6 bits (i.e., including 64 resistances) and the second resistance string 521 of 7 bits (i.e., including 128 resistances) can be used to generate the first conversion voltage V_RDAC corresponding to the image data signal (DS<7:0>) of 8 bits (i.e., 256). Therefore, the circuit area of the digital-to-analog converter can be minimized.

[0107] Figure 6 is a circuit diagram of a boost circuit 550a according to an embodiment of the present application.

[0108] Referring to Figure 6 , the boost circuit 550a includes a switch SW1, a capacitor C_S, boost switches Sg1, Sg2, Sg3, Sg4, and a compensation capacitor C_M.

[0109] The switch SW1, the capacitor C_S, and the boost switches Sg1, Sg2, Sg3, Sg4 are the same as those of the boost circuit 550 shown in Figure 2 , and thus a repeated description thereof is omitted.

[0110] The compensation capacitor C_M is connected between the first node N1 and a fifth voltage terminal VIN5. The fifth voltage terminal VIN5 can be a ground terminal receiving a ground voltage (e.g., the first boosted voltage GND).

[0111] The compensation capacitor C_M can be a Metal-Insulator-Metal (MIM) capacitor same as the capacitor C_S.

[0112] Each of the boost switches Sg1, Sg2, Sg3, Sg4 can be implemented by a transistor, and the second amplifier 560 can include a transistor. The transistor includes a parasitic capacitance. Such a parasitic capacitance generates an offset error in the digital-to-analog converter, which can cause an erroneous conversion.

[0113] In a case where the compensation capacitor C_M has a sufficiently large capacitance, the influence caused by the parasitic capacitances of the boost switches Sg1, Sg2, Sg3, Sg4 and the second amplifier 560 can be minimized.

[0114] Figure 7 is a circuit diagram of a boost circuit 550b according to an embodiment of the present application.

[0115] Referring to Figure 7 , the boost circuit 550b includes a switch SW1, a capacitor C_MS, and boost switches Sg1, Sg2, Sg3, Sg4.

[0116] The switch SW1 and the boost switches Sg1, Sg2, Sg3, Sg4 are the same as the switch SW1 and the boost switches Sg1, Sg2, Sg3, Sg4 of the boost circuit 550 shown in Figure 2 , and thus a repeated explanation thereof is omitted.

[0117] In an embodiment, the capacitor C_MS can be a MOS capacitor (MOSCAP).

[0118] When one of the boost switches Sg1, Sg2, Sg3, Sg4 is turned on, an offset error of the digital-to-analog converter is generated according to a ratio of a parasitic capacitance of the turned-on boost switch and a capacitance of the capacitor C_MS.

[0119] The capacitor C_MS can be formed by the same process as the boost switches Sg1, Sg2, Sg3, Sg4. As a result, the parasitic capacitances of the boost switches Sg1, Sg2, Sg3, Sg4 can be offset (or compensated) by the parasitic capacitance of the capacitor C_MS.

[0120] Figure 8is a circuit diagram of a boost circuit 550c and a second amplifier 560 according to an embodiment of the present utility model.

[0121] Referring to Figure 8 , the boost circuit 550c includes switches SW1, SW2, SW3, SW4, a capacitor C_MS, and boost switches Sg1, Sg2, Sg3, Sg4.

[0122] The switches SW1 and the boost switches Sg1, Sg2, Sg3, Sg4 are the same as the switches SW1 and the boost switches Sg1, Sg2, Sg3, Sg4 of the boost circuit 550 shown in Figure 2 , and thus repeated description thereof is omitted.

[0123] In an embodiment, the capacitor C_MS can be a MOS capacitor (MOSCAP).

[0124] When one of the boost switches Sg1, Sg2, Sg3, Sg4 is turned on, an offset error of the digital-to-analog converter is generated according to a ratio of a parasitic capacitance of the turned-on boost switch and a capacitance of the capacitor C_MS.

[0125] The capacitor C_MS can be formed by the same process as the boost switches Sg1, Sg2, Sg3, Sg4. As a result, the parasitic capacitance of the boost switches Sg1, Sg2, Sg3, Sg4 can be offset (or compensated) by the parasitic capacitance of the capacitor C_MS.

[0126] The switch SW2 is connected between the first node N1 and the third node N3 and operates in response to a reverse reset signal RSTB. The switch SW3 is connected between a sixth voltage terminal VIN6 receiving a reference voltage V_REF and the third node N3 and operates in response to a reset signal RST. The switch SW4 is connected between the second node N2 and a second input terminal (-) of the second amplifier 560 and operates in response to the reset signal RST.

[0127] In an embodiment, the reverse reset signal RSTB can be a signal complementary to the reset signal RST.

[0128] If the reset signal RST is high, the switches SW1, SW3, SW4 are turned on. As a result, the reference voltage V_REF is provided to the third node N3, i.e., a first input terminal (+) of the second amplifier 560, and the second node N2 is connected with a second input terminal (-) of the second amplifier 560.

[0129] That is, the capacitor sampling the offset of the second amplifier 560 and the capacitor superimposing (or boosting) the voltage of the first node N1 can be commonly used as the capacitor C_MS. Therefore, the parasitic capacitance of the second amplifier 560 can be canceled (or compensated) by the parasitic capacitance of the capacitor C_MS.

[0130] Figure 9 is a circuit diagram of a boost circuit 550d and a second amplifier 560 according to an embodiment of the present application.

[0131] Referring to Figure 9 , the boost circuit 550d includes switches SW11, SW12, SW13, SW14, a capacitor C_MS, and boost switches Sg1, Sg2, Sg3, Sg4.

[0132] The switches SW11 and the boost switches Sg1, Sg2, Sg3, Sg4 are the same as the switches SW1 and the boost switches Sg1, Sg2, Sg3, Sg4 of the boost circuit 550 shown in Figure 2 , and thus a repeated explanation thereof will be omitted.

[0133] In an embodiment, the capacitor C_MS can be a MOS capacitor (MOSCAP).

[0134] The switch SW11 is connected between an output terminal of the first amplifier 540 shown in Figure 2 and the second node N2 and operates in response to a reverse reset signal RSTB. The switch SW12 is connected between the first node N1 and a third node N3 and operates in response to the reverse reset signal RSTB. The switch SW13 is connected between a sixth voltage terminal VIN6 receiving a reference voltage V_REF and the third node N3 and operates in response to a reset signal RST. The switch SW14 is connected between the second node N2 and a second input terminal (-) of the second amplifier 560 and operates in response to the reset signal RST.

[0135] In an embodiment, the reverse reset signal RSTB can be a signal complementary to the reset signal RST.

[0136] If the reset signal RST is at a high level, the switches SW13 and SW14 are turned on. As a result, the reference voltage V_REF is supplied to the third node N3, i.e., the first input terminal (+) of the second amplifier 560, and the second node N2 is connected to the second input terminal (-) of the second amplifier 560.

[0137] That is, the capacitor sampling the offset of the second amplifier 560 and the capacitor superimposing (or boosting) the voltage of the first node Nl can be commonly used as the capacitor C MS. Therefore, the parasitic capacitance of the second amplifier 560 can be canceled (or compensated) by the parasitic capacitance of the capacitor C MS.

[0138] In addition, if one of the boost switches Sgl, Sg2, Sg3, Sg4 is made to be on in response to the uppermost 2-bit signal DS<7:6> of the image data signal DS, the voltage of the first node Nl will change to one of the first boost voltage GND, the second boost voltage VGAMHl, the third boost voltage VGAMH2, and the fourth boost voltage VGAMH3.

[0139] If the reverse reset signal RSTB is high, the switches SWl l, SW12 are on. The first conversion voltage V RDAC from the first amplifier 540 shown in Figure 2 The first conversion voltage V RDAC from the first amplifier 540 shown in

[0140] The analog signal V OUT output from the second amplifier 560 can correspond to the voltage level corresponding to the second conversion voltage V STDAC of the third node N3.

[0141] Figure 10 is a graph exemplarily showing the voltage level of the analog signal V OUT according to the gray scale level of the image data signal DS.

[0142] In Figure 10 , the dotted line V OUT I indicates the voltage level of the analog signal V OUT according to the gray scale level of the image data signal DS in an ideal case.

[0143] In Figure 10 , the solid line V OUT R indicates the voltage level of the analog signal V OUT according to the gray scale level of the image data signal DS in the actual operating environment of the data driving circuit 200 shown in Figure 2

[0144] As can be seen from Figure 10 , the actual operating characteristics of the data driving circuit 200 are similar to those in the ideal case.

[0145] Figure 11 ​is a graph that exemplarily shows an emission current error (ECE) of a pixel according to a gray scale level of the image data signal DS.

[0146] With reference to Figure 11 It is known that the emission current error (ECE) of each of all the gray scale levels of the image data signal DS is included within +1 and -1 in the least significant bit (LSB).

[0147] Although the above has been described with reference to the preferred embodiments of the present application, it is clear that, for those skilled in the art or ordinary skilled in the art, various modifications and changes can be made to the present application without departing from the scope of the idea and technical field of the present application recorded in the appended claims. Therefore, the technical scope of the present application should not be limited to the content recorded in the detailed description of the specification, but should be defined by the appended claims.

Claims

1. A digital-to-analog converter, characterized by, comprises: a gamma reference voltage generator that outputs a gamma reference voltage in response to a first group of signals among digital signals; a voltage selector that outputs one of the gamma reference voltages as a gamma selection voltage in response to a second group of signals among the digital signals; a first amplifier that receives the gamma selection voltage and outputs a first converted voltage; a boost circuit that converts the first converted voltage into a second converted voltage in response to the first group of signals among the digital signals; and a second amplifier that receives the second converted voltage and outputs an analog signal.

2. The digital-to-analog converter of claim 1, wherein, The gamma reference voltage generator comprises: a first voltage generator that generates a first gamma reference voltage in response to the first group of signals among the digital signals; and a second voltage generator that generates a second gamma reference voltage in response to the first group of signals among the digital signals, one of the first gamma reference voltage and the second gamma reference voltage is output as the gamma reference voltage.

3. The digital-to-analog converter of claim 2, wherein, The first voltage generator comprises: a first resistance string including a plurality of resistors for generating the first gamma reference voltage; and a first switch circuit that outputs the first gamma reference voltage as the gamma reference voltage in response to the first group of signals among the digital signals.

4. The digital-to-analog converter of claim 3, wherein, The plurality of resistors of the first resistance string have resistance values different from each other.

5. The digital-to-analog converter of claim 2, wherein, The second voltage generator comprises: a second resistance string including a plurality of resistors for generating the second gamma reference voltage; a second switch circuit that outputs a portion of the second gamma reference voltage as the gamma reference voltage; a third switch circuit that outputs a portion of the second gamma reference voltage as the gamma reference voltage; and a fourth switch circuit that outputs a portion of the second gamma reference voltage as the gamma reference voltage, one of the second switch circuit, the third switch circuit, and the fourth switch circuit operates in response to the first group of signals among the digital signals.

6. The digital-to-analog converter of claim 5, wherein, The plurality of resistors of the second resistance string have resistance values identical to each other.

7. The digital-to-analog converter of claim 1, wherein, The boost circuit comprises: a first capacitor connected between a first node that receives the first converted voltage and a second node; and a boost switch circuit that transmits one of a plurality of boost voltages to the second node in response to the first group of signals among the digital signals.

8. The digital-to-analog converter of claim 7, wherein, The boost switch circuit comprises: a first boost switch connected between the second node and a first voltage terminal; and a second boost switch connected between the second node and a second voltage terminal, one of the first boost switch and the second boost switch is turned on in response to the first group of signals among the digital signals.

9. A data driving circuit, comprising: comprises: a digital-to-analog converter that converts an image data signal into an analog signal; and a demultiplexer that outputs the analog signal as a data signal, The digital-to-analog converter comprises: a gamma reference voltage generator that outputs a gamma reference voltage in response to a first group of signals among the image data signal; and a voltage selector that outputs one of the gamma reference voltages as a gamma selection voltage in response to a second group of signals among the image data signal. a voltage selector to output one of the gamma reference voltages as a gamma selection voltage in response to a second set of signals in the image data signals; a first amplifier to receive the gamma selection voltage and output a first converted voltage; a boost circuit to convert the first converted voltage to a second converted voltage in response to the first set of signals in the image data signals; and a second amplifier to receive the second converted voltage and output the analog signal.

10. A display device, characterized by comprising: comprising: a display panel; a scan driving circuit to provide a scan signal to the display panel; a data driving circuit to provide a data signal to the display panel; and a driving controller to provide an image data signal to the data driving circuit, the data driving circuit comprising: a digital-to-analog converter to convert the image data signal to an analog signal; and a demultiplexer to output the analog signal as the data signal, the digital-to-analog converter comprising: a gamma reference voltage generator to output gamma reference voltages in response to a first set of signals in the image data signal; a voltage selector to output one of the gamma reference voltages as a gamma selection voltage in response to a second set of signals in the image data signals; a first amplifier to receive the gamma selection voltage and output a first converted voltage; a boost circuit to convert the first converted voltage to a second converted voltage in response to the first set of signals in the image data signals; and a second amplifier to receive the second converted voltage and output the analog signal.

Images