Terminal structure and power semiconductor device

Abstract

The utility model relates to the technical field of semiconductors, in particular to a terminal structure, which comprises a wafer, a main junction and N field limiting ring groups, the N field limiting ring groups are sequentially distributed at intervals by taking the main junction as a starting point, and the main junction and the field limiting ring groups close to the main junction are distributed at intervals; each field limiting ring group comprises a P-field limiting ring and a P + complementary injection region, the P-field limiting ring and the P + complementary injection region are arranged in an overlapped and staggered manner, the P + complementary injection region is arranged in a direction close to the main junction, and the doping concentration of the P + complementary injection region is higher than that of the P-field limiting ring. According to the terminal structure, the breakdown voltage of the power semiconductor device is improved, meanwhile, the chip terminal area is saved, the reliability of the device is higher when the device bears high voltage, and the production cost can be reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technical field especially relates to a terminal structure and power semiconductor device. BACKGROUND

[0002] Power semiconductor device is easy to appear electric field concentration effect at active region main junction edge, make the curvature radius of device depletion region reduce, cause device to be easy to take place edge breakdown problem. Therefore, need to add terminal structure to device surface PN junction to slow down electric field concentration effect, improve electric field distribution, improve the pressure resistance and reliability of device.

[0003] The existing terminal structure adopts P+ field limiting ring technology to reduce the influence of junction surface bending effect, weaken the surface electric field intensity, improve the PN junction breakdown voltage of power semiconductor device. However, the P+ field limiting ring technology is used high doped concentration P+ field limiting ring, and the expansion of the depletion layer to the inside of the field limiting ring is very small when withstanding voltage, and the electric field intensity is distributed at the ring spacing position of the P+ field limiting ring. In this way, the position of the P+ field limiting ring bears limited pressure but occupies a large area. Moreover, in higher voltage power semiconductor devices, more P+ field limiting rings are usually needed to be added to expand the depletion layer to improve the withstand voltage, resulting in an increase in the occupied area of the terminal structure and a waste of chip area. SUMMARY

[0004] The embodiments of the present application provide a terminal structure and a power semiconductor device, which solve the technical problem of the terminal structure of the power semiconductor device in the prior art that the terminal structure adopts P+ field limiting ring technology and has limited pressure bearing but a large occupied area, achieve the technical effects of improving the breakdown voltage of the power semiconductor device while saving the terminal area of the chip, making the device have higher reliability when bearing high voltage, and reducing production cost.

[0005] In a first aspect, the embodiments of the utility model provide a terminal structure, which comprises a wafer and a main junction and N field limiting ring groups on the wafer, and N is greater than or equal to 1.

[0006] The N field limiting ring groups are distributed in sequence with the main junction as the starting point and are distributed with intervals between the main junction and the field limiting ring groups close to the main junction.

[0007] Each field limiting ring group comprises a P-field limiting ring and a P+ supplementary injection region, the P-field limiting ring and the P+ supplementary injection region are arranged with an overlap misplacement, and the P+ supplementary injection region is arranged in a direction close to the main junction, wherein the doping concentration of the P+ supplementary injection region is higher than that of the P-field limiting ring.

[0008] Optionally, in each field limiting ring group, the depth of the P-field limiting ring is greater than that of the P+ supplementary injection region.

[0009] Optionally, in each of the field limiting ring groups, the width of the P-field limiting ring is greater than the width of the P+ complementary injection region.

[0010] Optionally, the interval distance between the P-field limiting rings in the field limiting ring group increases in turn in the direction from the main junction to the outside of the N field limiting ring groups.

[0011] Optionally, further comprising: a P-type cutoff region, wherein the P-type cutoff region is located on the wafer and outside the N field limiting ring groups.

[0012] Optionally, further comprising: a field oxide layer, wherein the field oxide layer is located above the main junction, the field limiting ring group and the P-type cutoff region, and covers the surface partial region of the main junction, the surface region of the P-field limiting ring of the field limiting ring group and the surface partial region of the P-type cutoff region.

[0013] Optionally, further comprising: an insulating layer, wherein the insulating layer is located above the field oxide layer and covers the field oxide layer.

[0014] Optionally, further comprising: a contact hole penetrating through the insulating layer and a metal field plate filling the contact hole, wherein the contact hole and the metal field plate are one-to-one corresponding, one end of the contact hole and the metal field plate contacts the corresponding region, and the other end is located above the insulating layer.

[0015] Optionally, the wafer comprises: a substrate, a buffer layer and a drift region, wherein the buffer layer is located above the substrate, the drift region is located above the buffer layer, and the main junction and the field limiting ring group are located on the drift region.

[0016] Based on the same inventive concept, in a second aspect, the utility model also provides a power semiconductor device, comprising: the terminal structure as described in the first aspect.

[0017] The one or more technical schemes in the embodiments of the utility model have at least the following technical effects or advantages:

[0018] In each field limiting ring group of the wafer, the embodiment adopts a lightly doped P-field limiting ring, when bearing a high reverse voltage, the junction depletion layer not only drifts downward to the high-resistivity buffer layer drift region, but also expands to the inside of the P-field limiting ring, and the position of the P-field limiting ring also bears the voltage resistance. When the P-field limiting ring is mostly depleted or just depleted, a smaller ring width and ring spacing can be set than the P+ field limiting ring (i.e. the P-type high-doped field limiting ring in the prior art), so as to maintain a larger breakdown voltage with a smaller area. Moreover, on the basis of the P-field limiting ring structure, a P+ replenishment region is arranged and the P+ replenishment region is close to the main junction direction, and the P+ replenishment region and the P-field limiting ring have a certain overlapping area to assist in reducing the electric field close to the main junction direction and improving the reverse breakdown voltage. The field limiting ring group formed by the P-field limiting ring combined with the P+ replenishment region can maintain a larger breakdown voltage with a smaller area, so that the device obtains a larger breakdown voltage under the same terminal area or obtains the same breakdown voltage size with a smaller terminal area, reduces the production cost, and improves the voltage resistance characteristics and device reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0019] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of preferred embodiments, and are not meant to limit the present disclosure. Moreover, the same reference numerals in different figures represent the same or similar components. In the drawings:

[0020] Figure 1 A structure diagram of a terminal structure in the embodiment of the present application is shown;

[0021] In the drawings, 100, wafer; 200, main junction; 300, field limiting ring group; 400, P-type cutoff region; 501, field oxide layer; 502, insulating layer; 503, metal field plate

[0022] 101, substrate; 102, buffer layer; 103, drift region;

[0023] 301, P-field limiting ring; 302, P+ replenishment region. DETAILED DESCRIPTION

[0024] Exemplary embodiments of the present disclosure will be described in greater detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0025] Embodiment one

[0026] The utility model discloses a terminal structure of first embodiment provides, like Figure 1 As shown in the figure, it comprises: wafer 100, and the main knot 200 and N field limiting ring group 300 on wafer 100, N≥1.N field limiting ring group 300 is the starting point with main knot 200 and is distributed in succession interval, and main knot 200 is distributed with the interval of field limiting ring group 300 close to main knot 200.Each field limiting ring group 300 includes: P-field limiting ring 301 and P+ supplementary note area 302, P-field limiting ring 301 and P+ supplementary note area 302 overlap misplacement setting, and P+ supplementary note area 302 is set with the direction close to main knot 200, wherein, the doping concentration of P+ supplementary note area 302 is higher than the doping concentration of P-field limiting ring 301.

[0027] It needs to be explained that the terminal structure of this embodiment surrounds the active region of device, and the main knot 200 is located in the active region, that is, the main knot 200 is located in the active region inside N field limiting ring group 300, as shown in Figure 1 The main knot 200 is located on the left side of N field limiting ring. The width range of main knot 200 can be selected as 10um~20um. Main knot 200 and N field limiting ring group 300 are located on wafer 100. The surface of wafer 100, main knot 200 and field limiting ring group 300 is located at the same horizontal plane. In Figure 1 N field limiting ring group 300 is distributed in succession interval from left to right with main knot 200 as the starting point, and main knot 200 is also distributed with interval with the first field limiting ring group 300.Each field limiting ring group 300 includes: P-field limiting ring 301 and P+ supplementary note area 302, P-field limiting ring 301 is P type lightly doped field limiting ring, and P+ supplementary note area 302 is the area with the doping concentration higher than P-field limiting ring 301. Figure 1 In Figure 1 Each field limiting ring group 300, P-field limiting ring 301 and P+ supplementary note area 302 overlap misplacement setting, indicating that there is an overlapping area between P+ supplementary note area 302 and P-field limiting ring 301, P+ supplementary note area 302 is set with the direction close to main knot 200, and P-field limiting ring 301 is set with the direction away from main knot 200, that is, P+ supplementary note area 302 is set on the left side, and P-field limiting ring 301 is set on the right side.

[0028] In each field limiting ring group 300, the embodiment adopts a lightly doped P-field limiting ring 301. When a high reverse voltage is applied, the depletion layer not only extends downward to the drift region 103 of the high-resistivity buffer layer 102, but also extends to the interior of the P-field limiting ring 301, and the position of the P-field limiting ring 301 also bears the voltage. When the voltage is withstood, the P-field limiting ring 301 is mostly depleted or just depleted. Smaller ring width and ring spacing can be set than the P+ field limiting ring (i.e. the P-type high-doped field limiting ring in the prior art), so as to maintain a larger breakdown voltage with a smaller area. Furthermore, on the basis of the P-field limiting ring 301 structure, a P+ replenishment region 302 is arranged and the P+ replenishment region 302 is close to the main junction 200, and the P+ replenishment region 302 and the P-field limiting ring 301 have a certain overlapping area to assist in reducing the electric field close to the main junction 200 and improving the reverse breakdown voltage. The field limiting ring group 300 formed by the P-field limiting ring 301 combined with the P+ replenishment region 302 can maintain a larger breakdown voltage with a smaller area, so that the device has a larger breakdown voltage under the same terminal area or has the same breakdown voltage size with a smaller terminal area, reduces the production cost, and improves the voltage withstand characteristic and the device reliability.

[0029] Next, the terminal structure of the embodiment will be described in detail. Figure 1 Next, the terminal structure of the embodiment will be described in detail.

[0030] The wafer 100 includes a substrate 101, a buffer layer 102, and a drift region 103. The buffer layer 102 is located above the substrate 101, and the drift region 103 is located above the buffer layer 102. The main junction 200 and the field limiting ring group 300 are located on the drift region 103. The surface of the main junction 200 and the field limiting ring group 300 is at the same level as the surface of the drift region 103.

[0031] Specifically, the substrate 101 is an N-type heavily doped substrate. The buffer layer 102 is an N-type buffer layer. The buffer layer 102 includes at least one N-type field termination layer ， Alternatively, the buffer layer is composed of one or more layers by setting different doping concentrations. The drift region 103 is an N-type drift region. The doping concentration and thickness of the substrate 101 and the buffer layer 102 can be selected and set according to different product voltage requirements. The thickness of the substrate 101 of the embodiment can be selected in the range of 10-20 um, and the thickness of the buffer layer 102 can be selected in the range of 35-75 um.

[0032] N field limiting ring groups 300 are located on the drift region 103. The number of field limiting ring groups 300 can be set according to the device voltage requirement, for example, it can be set to one or more. In each field limiting ring group 300, the P-field limiting ring 301 is arranged in an offset position with the P+ compensation region 302, so that there is an overlapping area between the P+ compensation region 302 and the P-field limiting ring 301, the P+ compensation region 302 is arranged in the direction close to the main junction 200, and the P-field limiting ring 301 is arranged in the direction away from the main junction 200. The specific arrangement in each field limiting ring group 300 is that the depth of the P-field limiting ring 301 is greater than the depth of the P+ compensation region 302, and the width of the P-field limiting ring 301 is greater than the width of the P+ compensation region 302.

[0033] The depth of the P-field limiting ring 301 can be selected in the range of 4-5um, and the depth of the P+ compensation region 302 can be selected in the range of 1.5-3um. The width of the P-field limiting ring 301 can be set in the range of 8-12um, the implantation energy of the P-field limiting ring 301 can be 60-80Kev, and the dose can be 1E13cm -2 -2E14cm -2 The implantation energy of the P+ compensation region 302 is 60-80Kev, and the dose is 1E15cm -2 -1E16cm -2 The overlapping width of the overlapping area between the P+ compensation region 302 and the P-field limiting ring 301 can be in the range of 3-6um. The specific width and depth of the P-field limiting ring 301 and the P+ compensation region 302 can be designed according to different device product voltage requirements, epitaxial resistivity, thickness, field limiting ring width and other factors, and specific process conditions. The actual implantation energy and dose of the P-field limiting ring 301 and the P+ compensation region 302 can be adjusted according to different product requirements and process conditions. The overlapping area between the two needs to be adjusted to obtain the optimal effect according to the device voltage requirement, the field limiting ring width and the ring spacing set by the device.

[0034] The depth of the P+ compensation region 302 is designed to be smaller than the depth of the P-field limiting ring 301. Through simulation adjustment and optimization of this design, the surface electric field of the device can be reduced without damaging the original electric field control function of the P-field limiting ring 301 and the ring spacing. If the depth of the P+ compensation region 302 is too large, the doping concentration distribution close to the surface of the device will be reduced, affecting the surface electric field reduction effect. If the depth of the P+ compensation region 302 is too large, lateral diffusion will also occur, which will cause the overlapping area between the P+ compensation region 302 and the P-field limiting ring 301 to expand, and the depth is comparable, which may affect the original design of the P-field limiting ring 301 voltage effect and device reliability.

[0035] The P+ compensation region is introduced to optimize the electric field distribution, reduce the surface electric field, and improve the breakdown voltage. The width of the P+ compensation region 302 is set smaller than the width of the P-field limiting ring 301 to ensure that the electric field distribution can be effectively improved after adding P+ compensation injection without affecting the depletion breakdown voltage of the P-field limiting ring 301 body region, while avoiding excessive increase in the overall device size. The P+ compensation region 302 is located close to the main junction 200 to better reduce the electric field intensity at the edge of the main junction 200.

[0036] If the width of the P+ injection region 302 is too small, it will lead to: 1. It may be limited by process constraints and fail to meet design requirements (such as injection lithography opening and injection effect). 2. Poor compensation effect, which cannot effectively optimize the electric field distribution and improve the withstand voltage.

[0037] If the width of the P+ injection region 302 is too large, the optimization effect of the electric field distribution will be reduced. The main function of the P+ injection region 302 is to improve the electric field distribution and reduce electric field concentration. An excessively wide P+ injection region 302 may cause the electric field distribution in the termination region to become uneven, thereby affecting the breakdown voltage and reliability of the device. If the ring width (i.e., the width of the P+ injection region 302) is too large, a larger area of ​​the termination structure needs to be designed to achieve a better electric field distribution. With the total area remaining unchanged, some area of ​​the active region will be sacrificed, thereby affecting the current carrying capacity of the device and increasing manufacturing costs.

[0038] Furthermore, the spacing between the P-field limiting rings 301 in the field limiting ring group 300 increases sequentially outward from the main junction 200 towards the outside of the N field limiting ring groups 300. Optionally, the ring spacing (i.e., the distance between the P-field limiting rings 301) of the field limiting ring group 300 gradually increases from the P-field limiting ring 301 of the first field limiting ring group 300 to the P-field limiting ring 301 of the last field limiting ring group 300, ranging from 1µm to 4µm. The ring spacing can be set from 18µm to 28µm, and the specific ring spacing is set according to the voltage withstand requirements of different products. The ring spacing is the distance between adjacent P-field limiting rings 301.

[0039] This embodiment also includes a P-type cutoff region 400. The P-type cutoff region 400 is located on the wafer 100, specifically on the drift region 103, and outside the N field limiting ring groups 300. The surface of the P-type cutoff region 400 is at the same horizontal plane as the surface of the drift region 103. Figure 1 As shown, the P-type cutoff region 400 is located to the right of the N field-limiting ring groups 300. The injection energy of the P-type cutoff region 400 is 60–80 keV, and the dose is 2E12cm. -2 ~1E13m -2The actual injection energy and dose can be adjusted according to different product requirements and process conditions. The spacing between the P-type cutoff region 400 and the field limiting ring group 300 (i.e., the last field limiting ring group) close to the P-type cutoff region 400 can range from 60 to 150 um. The width of the P-type cutoff region 400 is set according to different product requirements. The position of the P-type cutoff region 400 is designed to ensure that the widening of the depletion layer formed by the main junction 200 and the field limiting ring and the N-type epitaxial layer is within a safe range, and the crystal defect region generated by subsequent chip edge cutting and the like is a certain distance away from the depletion layer, thereby enhancing the reliability of the device. The P-type cutoff region 400 of the present embodiment is formed together with the main junction 200, without the need for additional photomasks. By introducing the P-type cutoff region 400 at the edge of the termination structure, the concentration of electric field at the edge of the device can be effectively reduced, the surface electric field at the edge of the chip can be reduced, and the reliability of the device can be improved.

[0040] In addition, the main junction 200 is arranged to be free of contact with each field limiting ring, i.e., the main junction 200 is free of contact with the field limiting ring group 300 and the P-type cutoff region 400, and each field limiting ring is floating. This can effectively adjust the electric field distribution inside the device and reduce the concentration of electric field. Moreover, this contactless structure can reduce the coupling effect and reduce the leakage current of the device under reverse bias. Since the field limiting ring is not in direct contact with the main junction 200 and each ring, the conduction path that can occur in the termination structure can be reduced, further improving the reverse withstand voltage capability of the device.

[0041] The present embodiment further includes a field oxide layer 501. The field oxide layer 501 is located above the main junction 200, the field limiting ring group 300, and the P-type cutoff region 400, and covers a surface partial region of the main junction 200, a surface region of the P-field limiting ring 301 of the field limiting ring group 300, and a surface partial region of the P-type cutoff region 400. Figure 1 In the present embodiment, the main junction 200, the P+ complementary injection region 302, and the P-type cutoff region 400 are each provided with a field oxide layer 501 on both sides, and the field oxide layer 501 covers the P-field limiting ring 301. The field oxide layer 501 can be made of an insulating material such as silicon dioxide. The thickness of the field oxide layer 501 can range from 0.8 um to 1.2 um. The field oxide layer 501 can have a gradient shape, or can be set according to actual requirements.

[0042] The present embodiment further includes an insulating layer 502. The insulating layer 502 is located above the field oxide layer 501 and covers the field oxide layer 501, i.e., covers the entire field oxide layer 501. The insulating layer 502 can be made of an insulating material such as silicon dioxide or silicon nitride.

[0043] The embodiment also includes contact holes penetrating the insulating layer 502 and metal field plates 503 filling the contact holes. The contact holes are arranged one-to-one with the metal field plates 503, one end of the contact holes and the metal field plates 503 contacts the corresponding region, and the other end is above the insulating layer 502. Specifically, the number of the contact holes and the metal field plates 503 depends on the number of the main junction 200, the field limiting ring group 300, and the P-type cutoff region 400. The main junction 200, the P+ supplemental injection region 302 of each field limiting ring group 300, and the P-type cutoff region 400 each correspond to a contact hole penetrating the insulating layer 502, each contact hole is filled with deposited metal, and the metal is also above the insulating layer 502, forming a metal field plate 503. The metal field plate 503 corresponding to each contact hole is discontinuous.

[0044] The working principle of the terminal structure of the embodiment is as follows: the embodiment uses light doping to form the P-field limiting ring 301, and when high voltage is applied, the junction depletion layer extends downward to the drift region 103 of the high-resistivity buffer layer 102 and also extends to the inside of the P-field limiting ring 301. The light-doped field limiting ring is mostly depleted or just depleted when the voltage is applied, and the body region of the P-field limiting ring 301 also withstands the voltage. In comparison, a smaller ring width and a smaller ring spacing can be set for the P+ field limiting ring, so that a larger breakdown voltage is maintained with a smaller area. The P-field limiting ring 301 is formed by only using shallow doping, and when the voltage is applied, the P-field limiting ring 301 is mostly depleted, which is easily affected by fixed oxide charges or surface interface charges generated in the production process. The surface electric field is concentrated at the edge region of the main junction 200, and the curvature effect is increased, which affects the voltage withstand effect. Therefore, on the basis of the improved P-field limiting ring 301, a P+ supplemental injection region 302 with a certain offset from the P-field limiting ring 301 and a higher doping concentration is added to the position of the P-field limiting ring 301 close to the main junction 200 to assist in reducing the surface electric field of the edge of the main junction 200 and improving the reverse breakdown voltage. The relative position of the P-field limiting ring 301 and the P+ supplemental injection region 302 has a greater impact on the surface breakdown voltage. In order to effectively reduce the edge field effect of the main junction 200, the P+ supplemental injection region 302 is set to be close to the main junction 200, and there is an overlapping region with the P-field limiting ring 301. The width, depth, relative position of the P+ supplemental injection region 302 and the P-field limiting ring 301, and the doping concentration of the P-field limiting ring 301 need to be designed according to the device parameters. The doping concentration of the P-field limiting ring 301 cannot be too low. If the doping concentration of the P-field limiting ring 301 is too low, fixed oxide charges and interface state charges will easily cause surface depletion, so that the electric field is concentrated at the position close to the main junction 200, the curvature effect is obvious, and the device cannot withstand high voltage. In addition, there are positive charges such as trap charges on the surface of the semiconductor device, which can attract electrons in silicon to move to the surface, so that the surface electric field is concentrated, resulting in a decrease in the breakdown voltage. Therefore, on the basis of the P-field limiting ring 301 combined with the P+ supplemental injection region 302, a metal field plate 503 structure is added. When the metal field plate 503 is not applied with voltage or is applied with negative voltage, electrons can be repelled away from the silicon surface, the depletion line will expand outward, the surface electric field peak value will be reduced, and the reverse breakdown voltage will be further improved. In this way, by using the P-field limiting ring 301, the P-type cutoff region 400 combined with the P+ supplemental injection region 302, and the field limiting ring group 300, the P-type cutoff region 400 combined with the metal field plate 503, and other technologies, a larger breakdown voltage can be maintained with a smaller area, the production cost is reduced, and the voltage withstand characteristics and reliability of the device are improved.

[0045] The one or more technical solutions in the embodiments of the utility model have at least the following technical effects or advantages:

[0046] The embodiment realizes the high-voltage terminal structure by combining P-field limiting ring, P-type cutoff zone and P+ supplementing zone, and combining with the metal field plate technology. According to the product voltage requirement, the P-field limiting ring with light doping is designed, most of the inside of the P-field limiting ring is depleted or just depleted when high voltage is borne, so as to increase the voltage while not wasting the terminal area. In each field limiting ring group, the P+ supplementing zone is added, and the width of the P+ supplementing zone is less than the width of the P-field limiting ring. In order to more effectively reduce the electric field intensity near the main junction, the P-field limiting ring and the P+ supplementing zone have an overlapping area near the main junction direction. The design combines the metal field plate technology, so as to better reduce the surface electric field peak value and improve the reverse breakdown voltage.

[0047] Embodiment two

[0048] Based on the same inventive concept, the utility model second embodiment still provides a kind of power semiconductor device, comprising: the terminal structure of the power semiconductor device as described in embodiment one.

[0049] Those skilled in the art will appreciate that although preferred embodiments of the utility model have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the utility model.

[0050] Obviously, those skilled in the art can make various modifications and variations to the utility model without departing from the spirit and scope of the utility model. Thus, if these modifications and variations of the utility model fall within the scope of the claims of the utility model and their equivalent technologies, the utility model also intends to include these modifications and variations.

Claims

1. A terminal structure, characterized in that, The power semiconductor device comprises: a wafer, a main junction and N field limiting ring groups on the wafer, N≥1; N field limiting ring groups are sequentially distributed with the main junction as a starting point, and the main junction is distributed with the field limiting ring group close to the main junction. Each field limiting ring group comprises a P-field limiting ring and a P+ complementary injection region, the P-field limiting ring and the P+ complementary injection region are arranged in a staggered manner, and the P+ complementary injection region is arranged close to the main junction, wherein the doping concentration of the P+ complementary injection region is higher than the doping concentration of the P-field limiting ring.

2. The terminal structure of claim 1, wherein In each field limiting ring group, the depth of the P-field limiting ring is greater than the depth of the P+ complementary injection region.

3. The terminal structure of claim 2, wherein In each field limiting ring group, the width of the P-field limiting ring is greater than the width of the P+ complementary injection region.

4. The terminal structure of claim 3, wherein The spacing distance between the P-field limiting rings in the field limiting ring group increases in the direction away from the main junction to the outside of the N field limiting ring groups.

5. A terminal structure as claimed in any one of claims 1 to 4, characterized in that Further comprising: a P-type cutoff region; The P-type cutoff region is located on the wafer and outside the N field limiting ring groups.

6. The terminal structure of claim 5, wherein Further comprising: a field oxide layer, the field oxide layer is located on the main junction, the field limiting ring group and the P-type cutoff region, and covers the surface partial region of the main junction, the surface region of the P-field limiting ring of the field limiting ring group and the surface partial region of the P-type cutoff region.

7. The terminal structure of claim 6, wherein Further comprising: an insulating layer, the insulating layer is located on the field oxide layer and covers the field oxide layer.

8. The terminal structure of claim 7, wherein Further comprising: a contact hole penetrating through the insulating layer and a metal field plate filling the contact hole, the contact hole and the metal field plate are one-to-one corresponding, one end of the contact hole and the metal field plate contacts the corresponding area, and the other end is located on the insulating layer.

9. The terminal structure of claim 1, wherein The wafer comprises: a substrate, a buffer layer and a drift region, the buffer layer is located on the substrate, the drift region is located on the buffer layer, and the main junction and the field limiting ring group are located on the drift region.

10. A power semiconductor device, characterized by The power semiconductor device comprises: a terminal structure of the power semiconductor device according to any one of claims 1-9.

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