Double-sided selective passivation contact battery

Abstract

The utility model belongs to the field of photovoltaic technology. The utility model provides a double-sided selective passivation contact cell. Non-electrode areas and electrode areas which are alternately arranged are arranged on the front surface and the back surface of a silicon substrate of the double-sided selective passivation contact cell; the electrode region comprises at least one group of passivation contact layer structures, each passivation contact layer structure comprises a tunneling layer and a doped silicon passivation layer, and the non-electrode region comprises an anti-reflection passivation layer structure; on one surface of the silicon substrate, an emitter layer is arranged between the anti-reflection passivation layer structure and the silicon substrate, so that the emitter layer and the doped silicon passivation layer arranged on the surface form an SE, and the doping concentration of the emitter layer is lower than that of the doped silicon passivation layer on the surface. Compared with passivation contact integrally implemented on a single surface, the passivation contact layer structures and the anti-reflection passivation layer structures are alternately formed on double surfaces, so that the passivation contact effect can be optimized, the recombination loss can be reduced, and the problem of large-area parasitic absorption can be avoided, thereby effectively improving the short-circuit current and improving the overall efficiency of the battery.

Description

TECHNICAL FIELD

[0001] The utility model belongs to photovoltaic technical field relates to a kind of double-sided selective passivation contact cell. BACKGROUND

[0002] With the increasing demand for clean energy worldwide, solar cells as a green and environmentally friendly energy conversion device have received widespread attention. Among them, the passivated contact technology of crystalline silicon, as one of the effective technologies to improve the conversion efficiency of solar cells, has made significant progress in industry and scientific research in recent years. Compared with the traditional crystalline silicon structure, this technical solution forms an extremely thin interfacial oxide layer on the surface of crystalline silicon and deposits a doped polysilicon layer on it. The interfacial oxide layer can effectively passivate the dangling bonds on the surface of crystalline silicon, reduce surface state defects and reduce the recombination rate of carriers. By introducing a polysilicon layer, direct contact between metal and crystalline silicon surface is avoided, reducing metal-induced recombination loss and improving carrier collection efficiency.

[0003] TOPCon (Tunnel Oxide Passivated Contact) cell is a battery structure widely using the above-mentioned passivated contact scheme of crystalline silicon, which has shown the potential to gradually replace the traditional PERC (Passivated Emitter and Rear Cell) battery scheme and is expected to become the mainstream crystalline silicon battery technology of the next generation. As a kind of double-sided contact battery technology, the structure of TOPCon cell includes a P-type doped emitter on the front side and an extremely thin interfacial oxide layer and a doped polysilicon layer on the back surface of crystalline silicon, forming a passivated contact structure.

[0004] In order to obtain a higher carrier concentration, the emitter on the front side needs a deeper doping concentration. However, deep doping will result in more recombination centers, causing greater recombination loss. Especially under high sheet resistance conditions, the contact resistance is larger, which further increases the transmission loss of carriers and reduces the overall efficiency of the battery. At the same time, due to the use of full-area doped polysilicon structure on the back side, although it can provide good passivation effect, the polysilicon material itself has a certain absorption coefficient and will absorb part of the incident light in a certain wavelength range, i.e. there is a parasitic absorption problem, resulting in a lower short-circuit current.

[0005] Therefore, although the existing TOPCon battery technology has made significant progress in improving conversion efficiency, it still faces challenges such as large emitter recombination loss, high sheet resistance contact difficulty and parasitic absorption problem. In order to overcome these problems, a more efficient and reliable solution needs to be developed. UTILITY MODEL CONTENT

[0006] In view of the problems in the prior art, the utility model discloses a double -sided selective passivation contact cell, and the front and back of its silicon substrate are provided with the non -electrode area and electrode area of alternate arrangement, and the electrode area includes at least one group of passivation contact layer structure, and the passivation contact layer structure includes the tunneling layer and the doped silicon passivation layer, and the non -electrode area includes the antireflection passivation layer structure, and the emitter layer is arranged between the antireflection passivation layer structure and the silicon substrate on one side of the silicon substrate to constitute SE with the doped silicon passivation layer arranged on the surface, and the doping concentration of the emitter layer is lower than the doping concentration of the doped silicon passivation layer arranged on the surface.Compared with the passivation contact of the whole implementation on the single surface, the passivation contact layer structure and the antireflection passivation layer structure are alternately formed on the front and back, so that the passivation contact effect can be optimized, the recombination loss and light loss are reduced on the front, and the large-area parasitic absorption problem is avoided on the back, thereby effectively improving the short-circuit current, and the overall efficiency of the cell is improved.

[0007] To achieve this purpose, the utility model adopts the following technical scheme:

[0008] First, the utility model provides a double -sided selective passivation contact cell, including silicon substrate, with opposite front and back, and the non -electrode area and electrode area of alternate arrangement are arranged on the front and back,

[0009] The non -electrode area includes the antireflection passivation layer structure from the silicon substrate outwardly,

[0010] The electrode area includes at least one group of passivation contact layer structure, the antireflection passivation layer structure and electrode from the silicon substrate outwardly, and each passivation contact layer structure includes the tunneling layer and the doped silicon passivation layer, and the electrode is electrically connected with the doped silicon passivation layer,

[0011] The conductive doping type of the doped silicon passivation layer is different on different surfaces of the silicon substrate,

[0012] On one side of the silicon substrate, the emitter layer is arranged between the silicon substrate and the antireflection passivation layer structure arranged on the surface to constitute SE with the doped silicon passivation layer arranged on the surface, and the doping concentration of the emitter layer is lower than the doping concentration of the doped silicon passivation layer arranged on the surface.

[0013] The utility model discloses a silicon substrate is provided with the electrode area and non electrode area alternately on both sides (namely the front and back), wherein the electrode area has the passivation contact layer structure, and the non electrode area only has the antireflection passivation layer structure, to form the passivation contact layer structure and the antireflection passivation layer structure of the alternation arrangement on the both sides of the battery, that is, in the same side, only the passivation contact structure is formed in the specific area, and is not set on the whole surface. It can be understood that one side of the silicon substrate should be provided with an emitter layer, and when the emitter layer is arranged in the non electrode area, the doping concentration thereof is smaller than that of the doped silicon passivation layer of the electrode area to form SE together with the doped silicon passivation layer. Compared with the prior art of forming the emitter layer on the whole surface of the silicon substrate and deeply doping the corresponding electrode position, the deep (high) doping area of the utility model is arranged in the doped silicon passivation layer instead of the substrate, and due to the blocking effect of the tunneling layer, the amount of doping elements of the doped silicon passivation layer entering the silicon substrate is small or even tends to zero, so that the silicon substrate does not have many recombination centers, and the recombination loss is reduced. Since the doped silicon passivation layer and the emitter form SE together, the high doping concentration of the doped silicon passivation layer of the electrode makes the contact resistance of the electrode low, and the lightly doped emitter layer ensures the lateral transmission efficiency. More preferably, when the side provided with the emitter has light incidence, the non electrode area is not provided with the doped silicon passivation layer, thereby reducing the light loss caused by the light absorption of the doped silicon passivation layer. Since the non electrode area of the back of the silicon substrate is not provided with the doped silicon passivation layer, the parasitic absorption of the doped silicon passivation layer is reduced, thereby improving the short-circuit current of the battery. The overall efficiency of the battery is improved.

[0014] It can be understood that the conductive doping type refers to n-type and p-type. For example, the silicon substrate can be selected as an n-type silicon substrate, at this time, the doped silicon passivation layer on the front is p-type, and the doped silicon passivation layer on the back is n-type. When the emitter layer is arranged on the front, the conductive doping type of the emitter layer is the same as that of the doped silicon passivation layer on the front, which is p-type, but the doping concentration of the emitter layer is lower. In addition, the silicon substrate can also be selected as a p-type silicon substrate according to needs, and the doping conductive type of the emitter layer is different from that of the silicon substrate and is n-type. Of course, the emitter layer can also be located on the back of the silicon substrate, and the conductive doping type thereof is different from that of the silicon substrate.

[0015] It should be further pointed out that the different surfaces of the silicon substrate refer to the front and the opposite back. The one surface of the silicon substrate refers to one of the front or the back.

[0016] The following is the preferred technical scheme of the utility model, but not as a limitation of the technical scheme provided by the utility model. Through the following technical scheme, the technical purpose and beneficial effects of the utility model can be better achieved and realized.

[0017] As the preferred technical scheme of the utility model, when the conductive doping type of the doped silicon passivation layer is p type, the total thickness of the doped silicon passivation layer in all passivation contact layer structures ranges from 150 to 350 nm, for example, can be 150 nm, 180 nm, 200 nm, 210 nm, 230 nm, 250 nm, 280 nm, 300 nm, 320 nm or 350 nm, etc.; when the conductive doping type of the doped silicon passivation layer is n type, the total thickness of the doped silicon passivation layer in all passivation contact layer structures ranges from 80 to 200 nm, for example, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm or 200 nm, etc., but is not limited to the listed values, and other values not listed in the above numerical range are also applicable.

[0018] It should be noted that when there is only one set of passivation contact structure and only one layer of doped silicon passivation layer in one electrode area, the total thickness of the doped silicon passivation layer in all passivation contact layer structures refers to the thickness of this layer of doped silicon passivation layer; when there are two or more sets of passivation contact structures and multiple layers of doped silicon passivation layers in one electrode area, the total thickness of the doped silicon passivation layer in all passivation contact layer structures refers to the sum of the thicknesses of the doped silicon passivation layers.

[0019] As the preferred technical scheme of the utility model, two sets of passivation contact layer structures are arranged in the electrode area of the front surface and / or back surface of the silicon substrate, wherein the ratio of the thickness of the doped silicon passivation layer farther from the silicon substrate to the thickness of the doped silicon passivation layer closer to the silicon substrate ranges from (1.6-9):1, for example, 1.6:1, 1.7:1, 1.8:1, 2:1, 2.3:1, 2.5:1, 2.8:1, 3:1, 3.3:1, 3.6:1, 4:1, 4.3:1, 4.7:1, 5:1, 5.2:1, 5.6:1, 6:1, 6.3:1, 6.8:1, 7:1, 7.3:1, 7.7:1, 8:1, 8.2:1, 8.5:1, 8.8:1 or 9:1, etc., but is not limited to the listed values, and other values not listed in the above numerical range are also applicable.

[0020] As the preferred technical scheme of the utility model, when the conductive doping type of the emitter layer is p type, the sheet resistance of the emitter layer ranges from 300 to 1000 Ω / sq, for example, 300 Ω / sq, 400 Ω / sq, 500 Ω / sq, 600 Ω / sq, 700 Ω / sq, 800 Ω / sq, 900 Ω / sq or 1000 Ω / sq, etc., but is not limited to the listed values, and other values not listed in the above numerical range are also applicable.

[0021] As the preferred technical scheme of the utility model, the sheet resistance of the doped silicon passivation layer arranged on the same surface of the emitter layer is less than that of the emitter layer and ranges from 50 to 300 Ω / sq, for example, 50 Ω / sq, 80 Ω / sq, 100 Ω / sq, 120 Ω / sq, 150 Ω / sq, 180 Ω / sq, 200 Ω / sq, 230 Ω / sq, 250 Ω / sq, 280 Ω / sq or 300 Ω / sq, but is not limited to the listed values, and other values within the above range are also applicable.

[0022] As the preferred technical scheme of the utility model, when the conductive doping type of the emitter layer is p type, the sheet resistance of the emitter layer ranges from 300 to 1000 Ω / sq, and the sheet resistance of the doped silicon passivation layer arranged on the same surface of the emitter layer is less than that of the emitter layer and ranges from 50 to 300 Ω / sq.

[0023] As the preferred technical scheme of the utility model, the sheet resistance of the doped silicon passivation layer arranged on different surfaces of the emitter layer ranges from 30 to 60 Ω / sq, for example, 30 Ω / sq, 33 Ω / sq, 35 Ω / sq, 38 Ω / sq, 40 Ω / sq, 43 Ω / sq, 45 Ω / sq, 48 Ω / sq, 50 Ω / sq, 53 Ω / sq, 55 Ω / sq, 58 Ω / sq or 60 Ω / sq, but is not limited to the listed values, and other values within the above range are also applicable.

[0024] As the preferred technical scheme of the utility model, the doped silicon passivation layer comprises one or more of a polysilicon layer and a microcrystalline silicon.

[0025] As the preferred technical scheme of the utility model, the tunneling layer comprises a SiO2 layer, and the thickness of the SiO2 layer ranges from 1 to 3 nm, for example, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm or 3 nm, but is not limited to the listed values, and other values within the above range are also applicable. Of course, in other technical schemes of the utility model, the tunneling layer can also comprise one or more of aluminum oxide, silicon nitride and intrinsic silicon.

[0026] As the preferred technical scheme of the utility model, in the orthogonal projection to the plane where the silicon substrate is located, the electrode area on the front surface coincides with the electrode area on the back surface. In this technical scheme, the front and back electrode areas are oppositely arranged, so that the front light-shielding and the back parasitic absorption passivation contact layer structure overlap, the light loss and parasitic absorption caused by the non-overlapping of the two are reduced, and the overall efficiency of the battery is improved.

[0027] As the preferred technical scheme of the utility model, in at least one side: the surface of the silicon substrate of the electrode area and the surface of the silicon substrate of the non-electrode area exist height difference. In this technical scheme, the height difference between the electrode area and the non-electrode area can reduce the influence caused by the doping element in the doped silicon passivation layer crossing the tunneling layer and entering the silicon substrate. Of course, the height difference can also be caused by the texturing in the non-electrode area, so that the light trapping effect of the silicon substrate can be improved, and the battery efficiency is improved. Of course, the height difference caused by removing the tunneling layer of the non-electrode area and other reasons can also be two or more of the above reasons.

[0028] As the preferred technical scheme of the utility model, in at least one side: the surface of the silicon substrate of the electrode area has a polishing structure, and the reflectivity of the polishing structure ranges from 35% to 45%, such as 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44% or 45%, etc. The surface of the silicon substrate of the non-electrode area has a texturing structure, and the reflectivity of the texturing structure ranges from 9% to 11%, such as 9%, 9.3%, 9.5%, 9.8%, 10%, 10.3%, 10.5%, 10.8% or 11%, etc. However, it is not limited to the listed values, and other values not listed in the above numerical range are also applicable.

[0029] As the preferred technical scheme of the utility model, the antireflection passivation layer structure includes an aluminum oxide layer and / or a silicon nitride layer. The thickness of the aluminum oxide layer ranges from 3 to 10 nm, such as 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, etc. The thickness of the silicon nitride layer ranges from 70 to 85 nm, such as 70 nm, 72 nm, 75 nm, 78 nm, 80 nm, 82 nm or 85 nm, etc. The refractive index ranges from 2.0 to 2.05, such as 2.0, 2.01, 2.02, 2.03, 2.04 or 2.05, etc. However, it is not limited to the listed values, and other values not listed in the above numerical range are also applicable. Exemplarily, the utility model provides a manufacturing method suitable for the double-sided selective passivation contact battery, which includes the following steps:

[0030] Step 1: Prepare an n-type silicon wafer as a silicon substrate, perform alkali etching and polishing treatment, form a polishing surface with a pyramid base on the front surface (light receiving surface) of the silicon substrate, and the reflectivity is 35% to 45%;

[0031] Step 2: depositing a silicon oxide layer as a tunneling layer on the front side of the silicon substrate, then depositing an intrinsic polysilicon layer and performing boron doping to form a p-type doped polysilicon layer, the thickness of the p-type doped polysilicon layer ranges from 150 to 350 nm, and the sheet resistance ranges from 50 to 300 Ω / sq, as a doped silicon passivation layer; one layer of the tunneling layer and one layer of the doped silicon passivation layer form a group of layer structures, and at least one group is prepared before step 3 is performed;

[0032] Step 3: using pulsed laser to selectively open the front side tunneling layer and doped silicon passivation layer, exposing the silicon substrate, the exposed area being a non-electrode area, and the remaining front side tunneling layer and doped silicon passivation layer forming a passivation contact layer structure, and the area where it is located being an electrode area; in order to reduce the passivation damage caused by laser, the laser pulse energy density (HP) should not be too large, and the HP processing window is 0.1-1 J / cm 2 ;

[0033] Step 4: using alkali etching to perform texturing treatment on the front side non-electrode area, the reflectivity ranging from 9% to 11%;

[0034] Step 5: performing secondary boron diffusion, so that the surface of the silicon substrate in the front side non-electrode area forms an emitter layer with a p-type conductive doping type, and the sheet resistance of the emitter layer ranges from 300 to 1000 Ω / sq;

[0035] Step 6: wet etching to remove the back side BSG of the silicon substrate, and performing back side micro-etching treatment, forming a polished surface of the tower base on the back side, and the reflectivity is 35%-45%;

[0036] Step 7: depositing a silicon oxide layer as a tunneling layer on the back side, then depositing intrinsic polysilicon and performing phosphorus diffusion to form an n-type doped polysilicon layer, the thickness being 80-200 nm, and the sheet resistance being 30-60 Ω / sq, as a doped silicon passivation layer on the back side; one layer of the tunneling layer and one layer of the doped silicon passivation layer form a group of layer structures, and at least one group is prepared before step 8 is performed;

[0037] Step 8: using pulsed laser to selectively open the back side tunneling layer and doped silicon passivation layer, exposing the silicon substrate, the exposed area being a back side non-electrode area, and the remaining back side tunneling layer and doped silicon passivation layer forming a passivation contact layer structure, and the area where it is located being an electrode area; in order to reduce the passivation damage caused by laser, the laser pulse energy density (HP) should not be too large, and the HP processing window is 0.1-0.6 J / cm 2 ;

[0038] Step 9: wet de-winding, removing the PSG and BSG on the front and back surfaces, etching to remove the polysilicon on the front side, and etching the front side non-electrode area to the silicon wafer, with a corrosion depth of 2-5 μm.

[0039] Step 10: ALD (Atomic Layer Deposition) treatment is performed to deposit an aluminum oxide layer on the front side and the back side, with a thickness of 3-10 nm;

[0040] Step 11: Plasma-assisted layer-by-layer deposition of silicon nitride is performed on the front side and the back side, with a thickness of 70-80 nm for the silicon nitride layer on the front side and a refractive index of 2.0-2.05, and a thickness of 75-85 nm for the silicon nitride layer on the back side and a refractive index of 2.05; the aluminum oxide layer and the silicon nitride layer on the front side form a front-side anti-reflection passivation layer structure, and the aluminum oxide layer and the silicon nitride layer on the back side form a back-side anti-reflection passivation layer structure;

[0041] Step 12: Screen printing, sintering, and photo-injection treatment are performed on the front side and the back side to form electrodes on the electrode regions of the front side and the back side and to form electrical connections with the doped silicon passivation layer in the passivation contact layer structure on the front side and the back side, respectively, to obtain a double-sided selective passivation contact cell.

[0042] In the present embodiment, the emitter layer and the doped silicon passivation layer on the same side thereof are not formed in the same process step. Of course, in other embodiments, the emitter layer and the doped silicon passivation layer on the same side thereof are formed in the same process step, and the difference is that the passivation contact layer structure layer in the non-electrode region is subsequently removed, i.e., the emitter layer is formed due to the doping elements of the doped silicon passivation layer penetrating into the silicon substrate through the tunneling layer.

[0043] It is worth noting that the electrode region and the non-electrode region can form a height difference at this time in step 4. Of course, by controlling the etching conditions, the electrode region and the non-electrode region can also not form a height difference (within 20% of the process error range) at this time.

[0044] Preferably, the manufacturing method step 2 produces two sets of layer structures, wherein the thickness of the doped silicon passivation layer closer to the silicon substrate is 35-81 nm, such as 35 nm, 40 nm, 42 nm, 45 nm, 48 nm, 50 nm, 55 nm, 60 nm, 63 nm, 68 nm, 71 nm, 75 nm, 78 nm, 80 nm, or 81 nm, etc.

[0045] Preferably, the manufacturing method step 7 produces two sets of layer structures, wherein the thickness of the doped silicon passivation layer closer to the silicon substrate is 20-30 nm, such as 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, or 30 nm, etc.

[0046] In another embodiment of the present application, the back-side anti-reflection passivation layer structure includes silicon nitride from the silicon substrate outward, which is different from the above-mentioned embodiments.

[0047] In another embodiment of the utility model, different from the above embodiment, the backside anti-reflective passivation layer structure comprises silicon nitride and silicon oxynitride from the silicon substrate outward.

[0048] Compared with the prior art, the utility model has at least the following beneficial effects:

[0049] The utility model discloses a silicon substrate, and the electrode area and the non-electrode area are alternately arranged on the two side surfaces (i.e. the front side and the backside) of the silicon substrate, the passivation contact layer structure is arranged in the electrode area, and the anti-reflective passivation layer structure is arranged in the non-electrode area, so that the double sides of the battery have selective passivation contacts, and in the same side, the selective passivation contacts are formed in the specific area only, instead of being arranged on the whole surface. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 It is the structural schematic diagram of the double-side selective passivation contact battery of embodiment 1.

[0051] In the drawing: 1-silicon substrate, 2-front side first tunneling layer, 3-front side first doped silicon passivation layer, 4-front side aluminum oxide layer, 5-front side silicon nitride layer, 6-front side electrode, 7-backside first tunneling layer, 8-backside first doped silicon passivation layer, 9-backside aluminum oxide layer, 10-backside silicon nitride layer, 11-backside electrode. DETAILED DESCRIPTION

[0052] The technical scheme of the utility model will be further illustrated by specific embodiments.

[0053] Those skilled in the art should understand that the embodiments are only for helping understanding the utility model, and should not be regarded as the specific limitation to the utility model.

[0054] Embodiment 1

[0055] The embodiment provides a double-side selective passivation contact battery, which comprises a silicon substrate, and the silicon substrate comprises a front side and a backside. Figure 1As shown, including silicon substrate 1, with opposite front and back; The front is provided with alternating front electrode area and front non-electrode area; The back is provided with alternating back electrode area and back non-electrode area; The front electrode area includes the front surface of the silicon substrate 1 outwardly by the first tunneling layer 2, the front first doped silicon passivation layer 3, the front aluminum oxide layer 4, the front silicon nitride layer 5 and the front electrode 6, the front electrode 6 and the front first doped silicon passivation layer 3 form an electrical connection; The front first tunneling layer 2 and the front first doped silicon passivation layer 3 form a set of passivation contact layer structure in the front electrode area, the front aluminum oxide layer 4 and the front silicon nitride layer 5 form the antireflection passivation layer structure in the front electrode area; The back electrode area includes the back surface of the silicon substrate 1 outwardly by the first tunneling layer 7, the back first doped silicon passivation layer 8, the back aluminum oxide layer 9, the back silicon nitride layer 10 and the back electrode 11, the back electrode 11 and the back first doped silicon passivation layer 8 form an electrical connection; The back first tunneling layer 7 and the back first doped silicon passivation layer 8 form a set of passivation contact layer structure in the back electrode area, the back aluminum oxide layer 9 and the back silicon nitride layer 10 form the antireflection passivation layer structure in the back electrode area; The surface of the silicon substrate 1 in the front non-electrode area forms an emitter layer, which includes the front aluminum oxide layer 4 and the front silicon nitride layer 5 outwardly, forming an antireflection passivation layer structure in the front non-electrode area; The emitter layer and the front first doped silicon passivation layer 3 in the front electrode area constitute SE, and the doping concentration of the emitter layer is lower than that of the front first doped silicon passivation layer 3; The back non-electrode area includes the back aluminum oxide layer 9 and the back silicon nitride layer 10 outwardly from the surface of the silicon substrate 1, forming an antireflection passivation layer structure in the back non-electrode area; In the front, the antireflection passivation layer structure of the front electrode area and the antireflection passivation layer structure of the front non-electrode area are continuous; In the back, the antireflection passivation layer structure of the back electrode area and the antireflection passivation layer structure of the back non-electrode area are continuous;

[0056] The silicon substrate 1 is an n-type silicon wafer; The front is the light receiving surface, and the back is the back light surface; The surface of the silicon substrate 1 in the front electrode area and the back electrode area has a polishing structure, which is a pyramid base polishing structure with a reflectivity of 40%; The surface of the silicon substrate 1 in the front non-electrode area has a texturing structure, and the reflectivity of the texturing structure is 10%; The sheet resistance of the emitter layer is 600Ω / sq;

[0057] The front first doped silicon passivation layer 3 is a p-type doped passivation layer and a polysilicon layer, with a thickness of 260nm and a sheet resistance of 180Ω / sq;

[0058] The back first doped silicon passivation layer 8 is an n-type doped passivation layer and a polysilicon layer, with a thickness of 135nm and a sheet resistance of 45Ω / sq;

[0059] The front first tunneling layer 2 and the back first tunneling layer 7 are both SiO2 layers, and the thicknesses are both 1.2 nm;

[0060] The front electrode area and the back electrode area coincide with the orthographic projection of the silicon substrate 1;

[0061] The thicknesses of the front aluminum oxide layer 4 and the back aluminum oxide layer 9 are both 5.2 nm;

[0062] The thickness of the front silicon nitride layer 5 is 75 nm, and the refractive index is 2.03; the thickness of the back silicon nitride layer 10 is 80 nm, and the refractive index is 2.05.

[0063] The embodiment also provides a manufacturing method suitable for the double-sided selective passivation contact cell, and the manufacturing method comprises the following steps:

[0064] Step 1: prepare an n-type silicon wafer as the silicon substrate 1, perform alkali etching and polishing treatment, form a polished surface of a pyramid base on the front side of the silicon substrate 1, and the reflectivity is 40%;

[0065] Step 2: deposit a silicon oxide layer on the front side of the silicon substrate 1 as a front first tunneling layer 2, then deposit an intrinsic polysilicon layer, and perform boron doping to form a p-type doped polysilicon layer, the thickness of the p-type doped polysilicon layer is 260 nm, and the sheet resistance is 180 Ω / sq, as a front first doped silicon passivation layer 3;

[0066] Step 3: use pulsed laser to selectively open the front first tunneling layer 2 and the front first doped silicon passivation layer 3, expose the silicon substrate 1, and the exposed area is a front non-electrode area; the remaining front first tunneling layer 2 and the front first doped silicon passivation layer 3 form a passivation contact layer structure, and the area where the passivation contact layer structure is located is an electrode area; in order to reduce the passivation damage caused by laser, the laser pulse energy density (HP) should not be too large, and the HP processing window is 0.5 J / cm 2 ;

[0067] Step 4: perform alkali etching on the front non-electrode area to perform texturing treatment, and the reflectivity is 10%;

[0068] Step 5: perform secondary boron diffusion, so that the surface of the silicon substrate 1 in the front non-electrode area forms an emitter layer with a p-type conductive doping type, and the sheet resistance of the emitter layer is 600 Ω / sq;

[0069] Step 6: remove the back side BSG of the silicon substrate 1 by wet etching, and perform back side micro-etching treatment, form a polished surface of a pyramid base on the back side, and the reflectivity is 40%;

[0070] Step 7: A silicon oxide layer is deposited on the back surface of the silicon substrate 1 as a back surface first tunneling layer 7, then intrinsic polysilicon deposition and phosphorus diffusion are performed to form an n-type doped polysilicon layer with a thickness of 135 nm and a sheet resistance of 45 Ω / sq as a back surface first doped silicon passivation layer 8;

[0071] Step 8: A pulsed laser is used to selectively open the film of the back surface first tunneling layer 7 and the back surface first doped silicon passivation layer 8, exposing the silicon substrate 1, and the exposed area is the back surface non-electrode area. The remaining back surface first tunneling layer 7 and back surface first doped silicon passivation layer 8 form a passivation contact layer structure, and the area where they are located is the electrode area. In order to reduce the passivation damage caused by the laser, the laser pulse energy density (HP) should not be too large, and the HP processing window is 0.25 J / cm 2 ;

[0072] Step 9: Wet etching is used to remove the PSG and BSG on the front and back surfaces, and etching is used to remove the polysilicon on the front surface, and the front surface non-electrode area is etched to the silicon wafer with a depth of 2.2 μm.

[0073] Step 10: ALD processing is performed to deposit an aluminum oxide layer on the front and back surfaces with a thickness of 5.2 nm, respectively forming a front surface aluminum oxide layer 4 and a back surface aluminum oxide layer 9;

[0074] Step 11: Plasma-assisted layer-by-layer silicon nitride deposition is performed on the front and back surfaces, respectively. The front surface silicon nitride layer has a thickness of 75 nm and a refractive index of 2.03, and the back surface silicon nitride layer has a thickness of 80 nm and a refractive index of 2.05, respectively forming a front surface silicon nitride layer 5 and a back surface silicon nitride layer 10. The front surface aluminum oxide layer and the front surface silicon nitride layer form a front surface anti-reflection passivation layer structure, and the back surface aluminum oxide layer and the back surface silicon nitride layer form a back surface anti-reflection passivation layer structure.

[0075] Step 12: Screen printing, sintering and photo-injection processing are performed on the front and back surfaces to form a front electrode 6 on the front electrode area and form an electrical connection with the front surface first doped silicon passivation layer 3 in the front surface passivation contact layer structure, and to form a back electrode 11 on the back electrode area and form an electrical connection with the back surface first doped silicon passivation layer 8 in the back surface passivation contact layer structure, thereby obtaining a double-sided selective passivation contact cell.

[0076] Example 2

[0077] The present embodiment provides a double-sided selective passivation contact cell, wherein the front electrode area is further provided with a second group of passivation contact layer structures composed of a front surface second tunneling layer and a front surface second doped silicon passivation layer, and the front electrode 6 is electrically connected to the front surface second doped silicon passivation layer.

[0078] That is, in the manufacturing method step 2 comprises: on the front side of the silicon substrate 1 deposition of a layer of silicon oxide layer as the front side of the first tunneling layer 2, then deposition of a layer of intrinsic polysilicon layer, and boron doping, forming a p-type doped polysilicon layer, p-type doped polysilicon layer thickness is 60 nm, square resistance 180 Ω / sq, as the front side of the first doped silicon passivation layer 3; then on the first doped silicon passivation layer 3 again deposition of a layer of silicon oxide layer (for SiO2 layer, thickness is 1.2 nm) as the front side of the second tunneling layer, then deposition of a layer of intrinsic polysilicon layer, and boron doping, forming a p-type doped polysilicon layer, p-type doped polysilicon layer thickness is 200 nm, square resistance 180 Ω / sq, as the front side of the second doped silicon passivation layer;

[0079] In addition to the above, other conditions are exactly the same as example 1.

[0080] Example 3

[0081] The embodiment provides a double-sided selective passivation contact cell, wherein in the back electrode area, a second group of passivation contact layer structures composed of a back side second tunneling layer and a back side second doped silicon passivation layer are further arranged, and the back electrode 11 is electrically connected with the back side second doped silicon passivation layer.

[0082] That is, in the manufacturing method step 7 comprises: on the back side of the silicon substrate 1 deposition of a layer of silicon oxide layer as the back side of the first tunneling layer 7, then intrinsic polysilicon deposition and phosphorus extension, forming an n-type doped polysilicon layer, thickness 25 nm, square resistance 45 Ω / sq, as the back side of the first doped silicon passivation layer 8; then on the back side of the first doped silicon passivation layer 8 again deposition of a layer of silicon oxide layer as the back side of the second tunneling layer, then intrinsic polysilicon deposition and phosphorus extension, forming an n-type doped polysilicon layer, thickness 110 nm, square resistance 45 Ω / sq, as the back side of the second doped silicon passivation layer 8;

[0083] In addition to the above, other conditions are exactly the same as example 1.

[0084] Example 4

[0085] The embodiment provides a double-sided selective passivation contact cell, wherein in the front electrode area, a front side second tunneling layer and a front side second doped silicon passivation layer are further arranged, and the front electrode 6 is electrically connected with the front side second doped silicon passivation layer; specifically, the manufacturing method step 2 is the same as that in example 2; meanwhile, in the back electrode area of the double-sided selective passivation contact cell, a back side second tunneling layer and a back side second doped silicon passivation layer are further arranged, and the back electrode 11 is electrically connected with the back side second doped silicon passivation layer; specifically, the manufacturing method step 7 is the same as that in example 3.

[0086] In addition to the above, other conditions are exactly the same as example 1.

[0087] As can be seen from the above, the utility model discloses a selective passivation contact region and conventional passivation region are alternately arranged on both sides of the surface (i.e. front and back) of the silicon substrate, so that the double sides of the battery have selective passivation contact structure, and in the same side, only the selective passivation contact structure is formed in the specific area, and is not set on the whole surface. Can effectively reduce the contact recombination loss of the emitter, improve the contact resistance of the emitter metal electrode at the same time, in addition, the light absorption and parasitic absorption of the non-contact area (i.e. non-electrode area) can be eliminated, thereby improving the short-circuit current of the battery and improving the overall efficiency of the battery. It is worth mentioning that due to the influence of processing environment and conditions, the parameters involved in the utility model are the mean value or point value of the corresponding area or the local area, and the detection method and equipment are any one detection method and equipment suitable for the parameter detection, and the utility model does not limit this.

[0088] The preferred embodiments of the utility model are described in detail above, but the utility model is not limited to the specific details in the above-described embodiments, and various simple modifications can be made to the technical solutions of the utility model within the technical concept of the utility model, and these simple modifications all belong to the protection scope of the utility model.

[0089] In addition, it should be noted that various specific technical features described in the above specific embodiments can be combined in any appropriate manner without contradiction, and in order to avoid unnecessary repetition, the utility model will not further describe various possible combination manners.

[0090] In addition, various different embodiments of the utility model can also be combined arbitrarily, as long as it does not deviate from the idea of the utility model, and it should be considered as the disclosed content of the utility model.

Claims

1. A bifacially selectively passivated contact cell, characterized in that, The silicon substrate has opposite front and back surfaces, and both the front and back surfaces are provided with alternating non-electrode regions and electrode regions; The non-electrode regions comprise, from the silicon substrate outward, an anti-reflection passivation layer structure; The electrode regions comprise, from the silicon substrate outward, at least one set of passivation contact layer structures, the anti-reflection passivation layer structure, and an electrode; Each set of passivation contact layer structures comprises a tunneling layer and a doped silicon passivation layer; The electrode is electrically connected to the doped silicon passivation layer; On different surfaces of the silicon substrate, the conductive doping type of the doped silicon passivation layer is different; On one surface of the silicon substrate, an emitter layer is provided between the silicon substrate and the anti-reflection passivation layer structure provided on the surface, so as to form an SE with the doped silicon passivation layer provided on the surface; the doping concentration of the emitter layer is lower than that of the doped silicon passivation layer provided on the surface.

2. The bifacial, selectively passivated contact cell of claim 1, wherein, When the conductive doping type of the doped silicon passivation layer is p-type, the total thickness of the doped silicon passivation layer in all passivation contact layer structures ranges from 150 nm to 350 nm; when the conductive doping type of the doped silicon passivation layer is n-type, the total thickness of the doped silicon passivation layer in all passivation contact layer structures ranges from 80 nm to 200 nm.

3. The bifacial, selectively passivated contact solar cell of claim 1, wherein, The electrode regions of the front and / or back surfaces of the silicon substrate are provided with two sets of passivation contact layer structures, wherein the ratio of the thickness of the doped silicon passivation layer farther away from the silicon substrate to the thickness of the doped silicon passivation layer closer to the silicon substrate ranges from 1.6 to 9:

1.

4. The double-sided selectively passivated contact cell according to claim 1, wherein: When the conductive doping type of the emitter layer is p-type, the sheet resistance of the emitter layer ranges from 300 Ω / sq to 1000 Ω / sq; and / or, The sheet resistance of the doped silicon passivation layer provided on the same surface as the emitter layer is less than that of the emitter layer and ranges from 50 Ω / sq to 300 Ω / sq; and / or, The sheet resistance of the doped silicon passivation layer provided on a different surface from the emitter layer ranges from 30 Ω / sq to 60 Ω / sq.

5. The dual-sided, selectively-passivated contact solar cell of any of claims 1-4, wherein, The doped silicon passivation layer comprises one or more of a polysilicon layer and a microcrystalline silicon layer.

6. The dual-sided, selectively-passivated contact solar cell of any of claims 1-4, wherein, The tunneling layer comprises a SiO2 layer, and the thickness of the SiO2 layer ranges from 1 nm to 3 nm.

7. The dual-sided, selectively-passivated contact solar cell of any of claims 1-4, wherein, In the orthographic projection onto the plane in which the silicon substrate is located, the electrode regions of the front surface overlap the electrode regions of the back surface.

8. The dual-sided, selectively-passivated contact solar cell of any of claims 1-4, wherein, In at least one surface, the surface of the silicon substrate in the electrode region is higher than the surface of the silicon substrate in the non-electrode region.

9. The dual-sided, selectively-passivated contact solar cell of any of claims 1-4, wherein, In at least one surface: the surface of the silicon substrate in the electrode region has a polishing structure, and the reflectivity of the polishing structure ranges from 35% to 45%; the surface of the silicon substrate in the non-electrode region has a texturing structure, and the reflectivity of the texturing structure ranges from 9% to 11%.

10. The dual-sided, selectively-passivated contact solar cell of any of claims 1-4, wherein, The anti-reflection passivation layer structure comprises an aluminum oxide layer and / or a silicon nitride layer; the thickness of the aluminum oxide layer ranges from 3 nm to 10 nm; the thickness of the silicon nitride layer ranges from 70 nm to 85 nm, and the refractive index of the silicon nitride layer ranges from 2.0 to 2.05.

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