Display device

Abstract

A display device is provided. The display device includes a substrate including a display region in which light emitting regions are arranged, and a non-display region disposed at a periphery of the display region, a circuit layer disposed on the substrate, an element layer disposed on the circuit layer, a sealing layer disposed on the element layer, and a touch sensor layer disposed on the sealing layer. And a display driving circuit mounted in a partial region of the non-display region of the substrate. The circuit layer includes a gate insulating layer disposed on the substrate, an interlayer insulating layer disposed on the gate insulating layer, a planarization layer disposed on the interlayer insulating layer, and a first opening portion overlapping the display driving circuit and penetrating the planarization layer. The first opening portion includes a main opening portion overlapping with the display driving circuit, and a first sub-opening portion extending from a first side opposite to the display area among edges of the main opening portion and disposed between the main opening portion and the display area.

Description

TECHNICAL FIELD

[0001] The utility model relates to display device. BACKGROUND

[0002] With the development of information society, the demand for display device for displaying image increases in various forms. For example, display device is applied to various electronic devices such as smart phone, digital camera, notebook computer, navigation and smart television.

[0003] Display device can be flat panel display device such as liquid crystal display device (Liquid Crystal Display Device), field emission display device (Field Emission Display Device), light emitting display device (Light Emitting Display Device) and the like. Among them, light emitting display device can include organic light emitting display device containing organic light emitting element, inorganic light emitting display device containing inorganic light emitting element such as inorganic semiconductor, and super miniature light emitting display device containing super miniature light emitting element.

[0004] Organic light emitting display device displays image by using light emitting element containing light emitting layer of organic light emitting material respectively. As described above, compared with other display devices, organic light emitting display device can have more excellent performance in power consumption, response speed, light emitting efficiency, brightness and wide viewing angle and the like by using self light emitting element to realize image display.

[0005] One side of display device can include display area for displaying image and non-display area as the periphery of display area. Light emitting area emitting light with corresponding brightness and color can be arranged in display area. SUMMARY

[0006] Display device can include display driving circuit realized by integrated circuit chip.

[0007] Display driving circuit can be directly mounted in substrate. In this case, during the process of mounting display driving circuit, high temperature and high pressure stress is applied to inorganic insulating material and conductive material of circuit layer including substrate, so that crack can occur in inorganic insulating material. Crack of inorganic insulating material becomes the path of oxygen or moisture penetration, so that corrosion of conductive material or expansion of organic insulating material can be caused by oxygen or moisture. Therefore, open circuit defect, warpage defect and the like are caused, so that there is a problem that the service life of display device can be sharply reduced.

[0008] Therefore, the technical problem to be solved by the utility model is to provide display device which can reduce stress during mounting display driving circuit and improve service life.

[0009] The technical problems of the utility model are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art through the following description.

[0010] The display device according to the embodiment for solving the technical problem includes a substrate including a display area in which a light emitting area is arranged and a non-display area configured at a periphery of the display area, a circuit layer configured on the substrate, an element layer configured on the circuit layer, a sealing layer configured on the element layer, a touch sensor layer configured on the sealing layer, and a display driving circuit mounted in a circuit bonding area of the non-display area of the substrate. The circuit layer includes a gate insulating layer configured on the substrate, an interlayer insulating layer configured on the gate insulating layer, a planarization layer configured on the interlayer insulating layer, and a first opening portion overlapping the display driving circuit and penetrating the planarization layer. The first opening portion includes a main opening portion overlapping the display driving circuit, and a first sub opening portion extending from a first side of the edge of the main opening portion opposite the display area and configured between the main opening portion and the display area.

[0011] The minimum interval between each of the vertices connected by two edges extending in different directions from each other in the edge of the main opening portion and the planarization layer can be smaller than the minimum interval between the first side of the main opening portion and the planarization layer.

[0012] The edge of the main opening portion can further include a second side facing the first side, and a third side and a fourth side connected between the first side and the second side and facing each other. The planarization layer can include a first protruding portion adjacent to a first vertex between the first side and the third side, and a second protruding portion adjacent to a second vertex between the first side and the fourth side.

[0013] The planarization layer can further include a third protruding portion configured adjacent to a third vertex between the second side and the third side and a portion of the third side, and a fourth protruding portion configured adjacent to a fourth vertex between the second side and the fourth side and a portion of the fourth side.

[0014] The first opening portion can further include a second sub opening portion extending from another portion of the third side and connected to the first protruding portion and the third protruding portion, and a third sub opening portion extending from another portion of the fourth side and connected to the second protruding portion and the fourth protruding portion.

[0015] Each of the first protruding portion, the second protruding portion, the third protruding portion, and the fourth protruding portion can have an arc shape on a side facing the main opening portion.

[0016] The first opening portion can further include a second sub opening portion extending from the third side and meeting the first protruding portion, and a third sub opening portion extending from the fourth side and meeting the second protruding portion.

[0017] The display device can further include a circuit board configured to be adjacent to the display driving circuit and to be bonded at an edge of the substrate. The circuit layer can further include circuit bonding pads arranged within the main opening portion and for the display driving circuit to be bonded, circuit connection wirings electrically connected to the circuit bonding pads, respectively, and substrate bonding pads arranged in parallel to an edge of the substrate adjacent to the circuit bonding pads and for the circuit board to be met. The circuit bonding pads can include data output pads configured to be adjacent to the first side, and data input pads configured to be adjacent to the second side. The circuit connection wirings can include data supply wirings electrically connected to the data output pads, overlapping the first sub opening portion, and extending toward an edge of the display area, and data pad wirings electrically connected to the data input pads and extending toward a part of the substrate bonding pads.

[0018] In a direction in which the first side and the second side face each other, a gap between the first side and the planarization layer can be greater than a gap between the second side and the planarization layer due to a width of the first sub opening portion.

[0019] In a direction in which the first side and the second side face each other, a gap between the first side and the planarization layer can be within a range of 50 μm to 100 μm.

[0020] The planarization layer can include a first planarization layer disposed on the interlayer insulating layer, and a second planarization layer covering the first planarization layer. The second planarization layer can include a first step portion disposed on the first planarization layer at a first thickness, a bottom surface extension facing the first side and meeting the interlayer insulating layer, and a second step portion disposed between the first step portion and the bottom surface extension. A part of the second step portion adjacent to the first step portion can be disposed on the first planarization layer at a second thickness smaller than the first thickness. In a direction in which the first side and the second side face each other, a part of the second step portion of the second planarization layer facing the first side can be disposed at a width greater than a gap between the first side and the planarization layer.

[0021] The touch sensor layer can include a touch buffer layer disposed on the sealing layer, a touch interlayer insulating layer disposed on the touch buffer layer, and a touch planarization layer disposed on the touch interlayer insulating layer. The touch planarization layer can overlap the first stepped portion.

[0022] The touch sensor layer can include a touch buffer layer disposed on the sealing layer, and a touch interlayer insulating layer disposed on the touch buffer layer. The circuit layer can further include a lighting circuit overlapping the display driving circuit and surrounded by the main opening portion, and disposed between the data output pad and the data input pad and covered by the planarization layer. The lighting circuit can be electrically connected with at least a part of the data output pad.

[0023] Each of the gate insulating layer, the interlayer insulating layer, the touch buffer layer, and the touch interlayer insulating layer can include an inorganic insulating material. The planarization layer can include an organic insulating material. The touch buffer layer can overlap the lighting circuit and meet the interlayer insulating layer in the first opening portion.

[0024] The circuit layer can further include a second opening portion between the data output pad and the lighting circuit and extending in parallel with the first edge in a direction in which the first edge and the second edge face each other and at least through the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer, and a third opening portion between the data input pad and the lighting circuit and extending in parallel with the second edge in a direction in which the first edge and the second edge face each other and at least through the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer.

[0025] The circuit layer can further include an auxiliary opening portion within the first sub opening portion and extending in parallel with the first edge and at least through the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer. In a direction in which the first edge and the second edge face each other, a gap between the auxiliary opening portion and the planarization layer can be smaller than a gap between the auxiliary opening portion and the first edge.

[0026] A display device according to an embodiment for solving the technical problem includes a substrate including a display area in which a light emitting area is arranged, and a non-display area configured at a periphery of the display area, a circuit layer configured on the substrate, an element layer configured on the circuit layer, a sealing layer configured on the element layer, a touch sensor layer configured on the sealing layer, and a display driving circuit mounted in a part of the non-display area of the substrate. The circuit layer includes a gate insulating layer configured on the substrate, an interlayer insulating layer configured on the gate insulating layer, a planarization layer configured on the interlayer insulating layer, and a first opening portion overlapping the display driving circuit and penetrating the planarization layer. The first opening portion includes a main opening portion overlapping the display driving circuit, and a first sub opening portion extending from a first edge of the main opening portion facing the display area and configured between the main opening portion and the display area. The edge of the main opening portion further includes a second edge facing the first edge, and a third edge and a fourth edge connected between the first edge and the second edge and facing each other. The planarization layer includes a first protruding portion adjacent to a first vertex between the first edge and the third edge, and a second protruding portion adjacent to a second vertex between the first edge and the fourth edge.

[0027] A minimum interval between the first vertex and the planarization layer can be smaller than a minimum interval between the first edge and the planarization layer due to the first protruding portion.

[0028] A minimum interval between the second vertex and the planarization layer can be smaller than a minimum interval between the first edge and the planarization layer due to the second protruding portion.

[0029] The display device can further include a circuit board configured adjacent to the display driving circuit and bonded at an edge of the substrate. The circuit layer can further include circuit bonding pads arranged within the main opening portion and for the display driving circuit to be bonded, circuit connection wirings electrically connected to the circuit bonding pads, respectively, and substrate bonding pads arranged in parallel with one side of the edge of the substrate adjacent to the circuit bonding pads and for the circuit board to be bonded. The circuit bonding pads can include data output pads configured adjacent to the first side, and data input pads configured adjacent to the second side. The circuit connection wirings can include data supply wirings electrically connected to the data output pads, overlapping the first sub opening portion, and extending toward the edge of the display area, and data pad wirings electrically connected to the data input pads and extending toward a part of the substrate bonding pads. The touch sensor layer can include a touch buffer layer configured on the sealing layer, and a touch interlayer insulating layer configured on the touch buffer layer. The circuit layer can further include a lighting circuit overlapping the display driving circuit, surrounded by the main opening portion, configured between the data output pads and the data input pads, and covered by the planarization layer. The lighting circuit can be electrically connected to at least a part of the data output pads. Each of the gate insulating layer, the interlayer insulating layer, the touch buffer layer, and the touch interlayer insulating layer can include an inorganic insulating material. The planarization layer can include an organic insulating material. The touch buffer layer can overlap the lighting circuit and meet the interlayer insulating layer in the first opening portion. The circuit layer can further include a second opening portion between the data output pads and the lighting circuit in a direction in which the first side and the second side face each other, extending in parallel with the first side, and at least through the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer, and a third opening portion between the data input pads and the lighting circuit in the direction in which the first side and the second side face each other, extending in parallel with the second side, and at least through the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer.

[0030] The circuit layer can further include an auxiliary opening portion within the first sub opening portion, extending in parallel with the first side, and at least through the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer. In the direction in which the first side and the second side face each other, a gap between the auxiliary opening portion and the planarization layer can be smaller than a gap between the auxiliary opening portion and the first side.

[0031] Specific contents of other embodiments are included in the detailed description and the drawings.

[0032] A display device according to an embodiment includes a substrate, a circuit layer on the substrate, an element layer on the circuit layer, a sealing layer on the element layer, a touch sensor layer on the sealing layer, and a display driving circuit. The substrate includes a display area in which light emitting areas are arranged, and a non-display area disposed at a periphery of the display area. The display driving circuit can be mounted in a part of the non-display area of the substrate. The circuit layer can include a gate insulating layer on the substrate, an interlayer insulating layer on the gate insulating layer, a planarization layer on the interlayer insulating layer, and a first opening portion overlapping the display driving circuit and penetrating the planarization layer. The first opening portion includes a main opening portion overlapping the display driving circuit, and a first sub opening portion extending from a first side of edges of the main opening portion opposite the display area.

[0033] As described above, since the first side in the main opening portion overlapping the display driving circuit is spaced apart from the planarization layer by the first sub opening portion, deformation of the organic insulating material of the planarization layer adjacent to the first side due to stress of high temperature and high pressure can be mitigated when mounting the display driving circuit. Thus, since cracking defects or warpage defects of the inorganic insulating layer around the first side can be mitigated, open defects or short defects of a wire extending from the first side toward the display area can be mitigated.

[0034] Also, according to an embodiment, the edges of the main opening portion can further include a second side facing the first side, and a third side and a fourth side connected between the first side and the second side and facing each other, and the planarization layer can include a first protrusion portion adjacent to a first vertex between the first side and the third side, and a second protrusion portion adjacent to a second vertex between the first side and the fourth side.

[0035] When configured as described above, since the inorganic insulating layer of the circuit layer in the corner facing the display area and being bent in the edges of the display driving circuit is protected by the planarization layer of the organic insulating material, warpage defects or corrosion defects can be mitigated.

[0036] Thus, the lifespan of the display device can be improved.

[0037] Effects according to an embodiment are not limited to the above-illustrated contents, and more various effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 is a plan view illustrating a display device according to an embodiment.

[0039] Figure 2 is a sectional view illustrating A-A' of Figure 1 .

[0040] Figure 3 is a layout view showing Figure 1 Part B.

[0041] Figure 4 is an equivalent circuit view showing Figure 3 the light-emitting pixel drive section.

[0042] Figure 5 is a plan view showing a touch sensor layer of Figure 2 according to an embodiment.

[0043] Figure 6 is an enlarged view showing Figure 5 Part C.

[0044] Figure 7 is a sectional view showing Figure 6 D-D' of

[0045] Figure 8 is a plan view showing a substrate and a circuit layer of Figure 2 according to an embodiment.

[0046] Figure 9 is a plan view showing Figure 8 Part E according to an embodiment.

[0047] Figure 10 is a sectional view showing Figure 9 F-F' of

[0048] Figure 11 is a sectional view showing Figure 9 G-G' of

[0049] Figure 12 and Figure 13 is a plan view showing Figure 8 Part E according to an embodiment.

[0050] Figure 14 is a sectional view showing Figure 13 F-F' of

[0051] Figure 15 is a plan view showing Figure 8 Part E according to an embodiment.

[0052] Explanation of Reference Numerals

[0053] 100: display device 110: substrate

[0054] DA: display area NDA: non-display area

[0055] 120: circuit layer 130: element layer

[0056] 140: sealing layer 150: touch sensor layer

[0057] 200: display drive circuit 300: circuit board

[0058] BBPD: substrate bonding pad DPD: display pad

[0059] CBDA: circuit bonding area TSC: lighting circuit

[0060] CBPD: circuit bonding pad CCNL: circuit connection wiring

[0061] DOPD: data output pad DIPD: data input pad

[0062] DSPL: data supply wiring DPDL: data pad wiring

[0063] 124: planarization layer

[0064] SD1, SD2, SD3, SD4: first side, second side, third side, fourth side

[0065] OP1, OP2, OP3: first opening, second opening, third opening

[0066] 1241, 1242: first planarization layer, second planarization layer

[0067] ST1, ST2: first step, second step BET: bottom surface extension

[0068] AOP: auxiliary opening DETAILED DESCRIPTION

[0069] The advantages, features and methods of realizing the present application can be clearly understood by referring to the embodiments described in detail below together with the accompanying drawings. Figure 1 The present application is not limited to the embodiments disclosed below, but is realized in various forms different from each other, and is defined only by the scope of the claims attached hereto. The embodiments are provided in order to completely disclose the present application and to completely inform those skilled in the art to which the present application pertains of the scope of the present application, and are provided for the purpose of complete disclosure.

[0070] Elements or layers are referred to as "on" another element or layer in a case where it is positioned directly above the other element or in a case where other layers or other elements are provided therebetween. Throughout the specification, the same reference numerals are used to denote the same constituent elements. The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for explaining the embodiments are merely illustrative, and the present application is not limited to the illustrated content.

[0071] Although first, second, etc. are used to describe various structural elements, these structural elements are not limited by these terms. These terms are used only to distinguish one structural element from other structural elements. Thus, the first structural element mentioned below can also be the second structural element within the technical idea of the present application.

[0072] Various features of various embodiments of the present application can be partially or wholly combined with or combined with each other, and various linkages and drives can be technically realized. Each embodiment can be independently implemented with respect to each other, or can be implemented together in an associated relationship.

[0073] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0074] Figure 1 is a plan view showing a display device according to an embodiment. Figure 2 is a sectional view of A-A' of Figure 1

[0075] Referring to Figure 1 , the display device 100 is a device that displays dynamic images or static images, which can be used not only as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet PC, a smart watch, a watch phone, a mobile communication terminal, an electronic manual, an electronic book, a portable multimedia player (PMP), a navigation, an ultra mobile PC (UMPC), etc., but also as a display screen of various products such as a television, a notebook computer, a monitor, a billboard, an internet of things (IOT), etc.

[0076] The display device 100 can be a light emitting display device such as an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a super small light emitting display device using a super small light emitting diode (micro LED or nano LED). Hereinafter, the display device 100 will be described centering on an organic light emitting display device. However, the present application is not limited thereto, but can be applied to a display device including an organic insulating material, an organic light emitting material, and a metal material.

[0077] ​The display device 100 may be formed as flat, but is not limited thereto. For example, the display device 100 may include curved surfaces formed at the left and right ends and having a constant or varying curvature. In addition, the display device 100 may be formed as flexible, thereby enabling buckling, bending, folding, or rolling.

[0078] The display device 100 includes a substrate 110.

[0079] The substrate 110 may include a display area DA disposed in the central part of the display surface of the display device 100, and a non-display area NDA disposed around the periphery of the display area DA.

[0080] The display area DA can be formed as a rectangular plane with a short side of a first direction DR1 and a long side of a second direction DR2 intersecting the first direction DR1. The corner where the short side of the first direction DR1 and the long side of the second direction DR2 meet can be rounded to have a specified curvature or formed as a right angle. The planar shape of the display area DA is not limited to a quadrilateral, but can be formed as other polygons, circles, or ellipses.

[0081] The non-display area NDA can be configured at the edge of the substrate 110 to surround the display area DA.

[0082] As an example, a portion of the non-display area NDA can be deformed into a curved shape. In this case, another portion of the non-display area NDA connected to the portion deformed into a curved shape can be disposed on the back of the display device 100.

[0083] According to an embodiment, the display device 100 may further include a display driving circuit 200 mounted in the non-display area NDA of the substrate 110.

[0084] The display driver circuit 200 can transmit to the circuit layer ( Figure 2 120) data wiring ( Figure 8 DL) supply data signal ( Figure 4 (Vdata).

[0085] According to an embodiment, the display device 100 may further include a circuit board 300 bonded to the edge of the substrate 110.

[0086] Circuit board 300 can be connected to the circuit layer ( Figure 2 The 120) and display driver circuit 200 supply signals and power.

[0087] Reference Figure 2According to an embodiment, the display device 100 can include a substrate 110, a circuit layer 120 disposed on the substrate 110, an element layer 130 disposed on the circuit layer 120, a sealing layer 140 disposed on the element layer 130, and a touch sensor layer 150 disposed on the sealing layer 140.

[0088] In addition, in order to reduce reflection of external light, the display device 100 according to an embodiment can further include a polarization layer 160 disposed on the touch sensor layer 150.

[0089] The substrate 110 can be composed of an insulating material such as a high molecular resin. For example, the substrate 110 can be composed of polyimide. The substrate 110 can be a flexible substrate that can be bent, folded, rolled, or the like.

[0090] Alternatively, the substrate 110 can be composed of an insulating material such as glass.

[0091] The substrate 110 can include a display area DA in which light emitting areas (EA) are arranged, and a non-display area NDA disposed at a periphery of the display area DA. Figure 3

[0092] The circuit layer 120 can include a gate insulating layer 122 disposed on the substrate 110, an interlayer insulating layer 123 disposed on the gate insulating layer 122, and a planarization layer 124 disposed on the interlayer insulating layer 123. Figure 7 Figure 7 Figure 7 Figure 7 Figure 7

[0093] The element layer 130 can include light emitting elements (LE) disposed in the light emitting areas (EA), respectively. Figure 3 Figure 4 Figure 7

[0094] The sealing layer 140 can include a first sealing layer 141 disposed on the element layer 130, a second sealing layer 142 disposed on the first sealing layer 141 and including a material different from that of the first sealing layer 141, and a third sealing layer 143 covering the second sealing layer 142. The first sealing layer 141 and the third sealing layer 143 can be composed of the same material. Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 ​​​​​​​​​​​​​​​​Each of the 143) can include an inorganic insulating material. The second sealing layer Figure 7 The 142) can include an organic insulating material.

[0095] The touch sensor layer 150 can include a touch buffer layer (151) disposed on the sealing layer 140, and a touch interlayer insulating layer (152) disposed on the touch buffer layer (151). Figure 7 The touch sensor layer 150 can further include a touch planarization layer (153) disposed on the touch interlayer insulating layer (152). Figure 7 The touch sensor layer 150 can further include a touch planarization layer (153) disposed on the touch interlayer insulating layer (152). Figure 7 The touch sensor layer 150 can further include a touch planarization layer (153) disposed on the touch interlayer insulating layer (152). Figure 3 The touch sensor layer 150 can further include a touch planarization layer (153) disposed on the touch interlayer insulating layer (152). Figure 1 The touch sensor layer 150 can further include a touch planarization layer (153) disposed on the touch interlayer insulating layer (152).

[0096] Figure 3 is a layout diagram illustrating a B portion of Figure 4

[0097] Referring to Figure 7 , the display area DA in the substrate 110 of the display apparatus 100 according to an embodiment can include light emitting areas EA. Also, the display area DA can further include non-light emitting areas disposed at the partition portions between the light emitting areas EA.

[0098] The element layer 130 can include light emitting elements (LE) disposed in the light emitting areas EA, respectively. Figure 4 The element layer 130 can include light emitting elements (LE) disposed in the light emitting areas EA, respectively. Figure 7 The circuit layer 120 can include light emitting pixel driving portions EPD electrically connected to the light emitting elements (LE) of the element layer 130, respectively.

[0099] The circuit layer 120 can include light emitting pixel driving portions EPD electrically connected to the light emitting elements (LE) of the element layer 130, respectively. Figure 3 The circuit layer 120 can include light emitting pixel driving portions EPD electrically connected to the light emitting elements (LE) of the element layer 130, respectively. Figure 4 The circuit layer 120 can include light emitting pixel driving portions EPD electrically connected to the light emitting elements (LE) of the element layer 130, respectively. The circuit layer 120 can include light emitting pixel driving portions EPD electrically connected to the light emitting elements (LE) of the element layer 130, respectively.

[0100] The light emitting pixel driving portions EPD can be arranged in parallel with each other in the first direction DR1 and the second direction DR2. The light emitting pixel driving portions EPD can be arranged in parallel with each other in the first direction DR1 and the second direction DR2.

[0101] The light emitting areas EA can be in a planar form of a rhombus or a rectangle. However, this is merely exemplary, and the planar form of the light emitting areas EA according to an embodiment is not limited to the quadrilateral as illustrated in Figure 3 That is, in addition to having a quadrilateral, each of the light emitting areas EA can have a planar form of a polygon such as a pentagon, a hexagon, etc., or a circular or elliptical shape including a curved edge. The light emitting areas EA can include a first light emitting area EA1 emitting light of a first color based on a prescribed wavelength band, a second light emitting area EA2 emitting light of a second color based on a wavelength band lower than the first color, and a third light emitting area EA3 emitting light of a third color based on a wavelength band lower than the second color.

[0102] The light emitting areas EA can include a first light emitting area EA1 emitting light of a first color based on a prescribed wavelength band, a second light emitting area EA2 emitting light of a second color based on a wavelength band lower than the first color, and a third light emitting area EA3 emitting light of a third color based on a wavelength band lower than the second color. The light emitting areas EA can include a first light emitting area EA1 emitting light of a first color based on a prescribed wavelength band, a second light emitting area EA2 emitting light of a second color based on a wavelength band lower than the first color, and a third light emitting area EA3 emitting light of a third color based on a wavelength band lower than the second color.

[0103] As an example, the first color can be red based on a wavelength band of about 600 nm to 750 nm. The second color can be green based on a wavelength band of about 480 nm to 560 nm. The third color can be blue based on a wavelength band of about 370 nm to 460 nm.

[0104] The first light emitting area EA1 and the third light emitting area EA3 can be alternately configured in at least one of the first direction DR1 and the second direction DR2.

[0105] The second light emitting area EA2 can be arranged in parallel with each other in at least one of the first direction DR1 and the second direction DR2.

[0106] In addition, the second light emitting area EA2 can be adjacent to the first light emitting area EA1 and the third light emitting area EA3 in a diagonal direction DR4 or DR5 crossing the first direction DR1 and the second direction DR2.

[0107] Pixels PX displaying respective brightness and colors are provided by the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 adjacent to each other in such light emitting areas EA.

[0108] In other words, the pixel PX can be a basic unit of displaying various colors including white in a prescribed brightness.

[0109] Each of the pixels PX can include at least one first light emitting area EA1, at least one second light emitting area EA2, and at least one third light emitting area EA3 adjacent to each other. Thereby, each of the pixels PX can display a plurality of colors by mixing light emitted from the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 adjacent to each other.

[0110] Figure 4 is an equivalent circuit diagram showing a light emitting pixel driving part of Figure 4

[0111] Referring to Figure 4 , the light emitting pixel driving part EPD of the circuit layer 120 can be electrically connected with the first power source ELVDD, and one of the light emitting elements LE of the element layer 130 can be electrically connected between one of the light emitting pixel driving parts EPD of the circuit layer 120 and the second power source ELVSS.

[0112] That is, the anode electrode of the light emitting element LE can be electrically connected with the first power source ELVDD through the light emitting pixel driving part EPD, and the cathode electrode of the light emitting element LE can be electrically connected with the second power source ELVSS having a lower voltage level than the first power source ELVDD. ​

[0113] The circuit layer 120 can further include a first power supply line VDL that transfers a first power supply ELVDD, a scan write line GWL that transfers a scan write signal GW, and a data line DL that transfers a data signal Vdata.

[0114] One light emitting pixel driving part EPD in the circuit layer 120 can include a first transistor T1 that generates a driving current Ids for driving the light emitting element LE, a second transistor T2 that is electrically connected between the first transistor T1 and the data line DL, and a first pixel capacitor PC1 that is electrically connected between the first transistor T1 and the first power supply line VDL.

[0115] The first transistor T1 can be electrically connected between the first power supply ELVDD and the light emitting element LE.

[0116] That is, a first electrode (for example, a source electrode) of the first transistor T1 can be electrically connected with the first power supply line VDL.

[0117] A second electrode (for example, a drain electrode) of the first transistor T1 can be electrically connected with an anode electrode of the light emitting element LE.

[0118] The first electrode of the first transistor T1 can be electrically connected with the data line DL through the second transistor T2.

[0119] The second transistor T2 can be electrically connected between the data line DL and the first electrode of the first transistor T1.

[0120] The second transistor T2 can be turned on according to the scan write signal GW of the scan write line GWL.

[0121] In a state in which a potential of a gate electrode of the first transistor T1 is maintained as a charging voltage of the first pixel capacitor PC1, when the second transistor T2 is turned on, the data signal Vdata of the data line DL can be transferred to the first electrode of the first transistor T1.

[0122] Further, when a voltage difference between the gate electrode and the first electrode of the first transistor T1 reaches a threshold voltage or more due to a difference voltage between the first power supply ELVDD and the data signal Vdata, the first transistor T1 can be turned on. At this time, the driving current Ids of the first transistor T1 can be generated as a size corresponding to the data signal Vdata.

[0123] Thereby, since the driving current Ids of the size corresponding to the data signal Vdata can be supplied to the light emitting element LE through the first transistor T1, the light emitting element LE can emit light of a brightness corresponding to the data signal Vdata.

[0124] As Figure 5As shown, the first transistor T1 and the second transistor T2 can be provided as P-type MOSFETs. However, this is merely illustrative, and at least one of the first transistor T1 and the second transistor T2 can also be provided as an N-type MOSFET.

[0125] Meanwhile, the light emitting pixel driving portion EPD according to the embodiment is not limited to Figure 2 the illustration, and in order to compensate or initialize each node, one or more transistors and one or more pixel capacitors electrically connected to the first transistor T1 or the light emitting element LE can also be included.

[0126] Figure 6 is a plan view showing a touch sensor layer according to an embodiment. Figure 5 Figure 7 is an enlarged view showing a portion C of Figure 6 Figure 5 is a cross-sectional view showing D-D' of Figure 1

[0127] Figure 5 The touch sensor layer 150 is shown as a capacitive touch sensor layer. In this case, the display device 100 can further include a touch driving circuit (not shown) mounted on a circuit board (300) of Figure 5 and senses a touch based on whether a capacitance varies or not. Just as Figure 5 the illustration is merely illustrative for easy explanation, and the touch sensor layer 150 according to the embodiment is not limited to Figure 5 the illustration.

[0128] For the convenience of explanation, Figure 2 only a portion of constituent elements of the touch sensor layer 150 is shown.

[0129] Referring to Figure 1 , the touch sensor layer 150 can include a touch sensing area TSA for sensing a touch of a user and a touch peripheral area TPA periphery of the touch sensing area TSA.

[0130] The touch sensing area TSA can be wider than the display area DA and similar to the display area DA. Thereby, the touch peripheral area TPA as a periphery of the touch sensing area TSA can be similar to the non-display area NDA as a periphery of the display area DA.

[0131] As an example, the touch sensing area TSA can overlap with an edge of the display area DA and the non-display area NDA bordering the display area DA. In this case, the touch peripheral area TPA can overlap with a remaining portion of the non-display area NDA not corresponding to the touch sensing area TSA.

[0132] ​​​The touch sensor layer 150 may include sensor electrodes SE and dummy electrodes DE arranged in a matrix and exhibiting mutual capacitance in the touch sensing area TSA, as well as sensor wiring TL1, TL2 and RE configured in the touch peripheral area TPA.

[0133] The sensor electrode SE may include a driving electrode TE (Touch driving Electrode) to which a driving signal is applied, and a sensing electrode RE (Receiving Electrode) for sensing the voltage charged in the mutual capacitance with the driving electrode TE.

[0134] Sensor wiring TL1, TL2 and RL can be configured in the touch peripheral area TPA and electrically connected to touch pads TPD1 and TPD2 arranged on one side of the edge of the substrate 110, respectively.

[0135] The sensor wiring TL1, TL2 and RL may include a first drive wiring TL1, a second drive wiring TL2 and a sensing wiring RL.

[0136] According to an embodiment, the circuit layer of the display device 100 ( Figure 6 The 120 may also include components arranged along one side of the edge of the substrate 110 and for supplying the circuit board ( Figure 7 The BBPD is connected to the substrate bonding pads of the 300 (300).

[0137] The substrate bonding pads BBPD may include touch pads TPD1 and TPD2 and display pads DPD.

[0138] Touch pads TPD1 and TPD2 may include a first touch pad TPD1 electrically connected to a first drive wiring TL1 and a second drive wiring TL2, and a second touch pad TPD2 electrically connected to a sensing wiring RL.

[0139] Display pads DPD can be electrically connected to display driver circuit 200. As an example, display pads DPD can be arranged in the first direction DR1 between the first touch pad TPD1 and the second touch pad TPD2.

[0140] Each of the first drive wiring TL1 and the second drive wiring TL2 can be electrically connected to two or more drive electrodes TE that are consecutively located in the second direction DR2.

[0141] The first drive wiring TL1 can extend from one side of the touch sensing area TSA adjacent to the touch pads TPD1 and TPD2 toward a portion of the first touch pad TPD1.

[0142] End portions of the first drive wiring lines TL1 can be arranged in the first direction DR1 along one side of the touch sensing area TSA.

[0143] The second drive wiring lines TL2 can extend from another side of the touch sensing area TSA facing the one side in which the first drive wiring lines TL1 are arranged to the remaining another part of the first touch pad TPD1.

[0144] End portions of the second drive wiring lines TL2 can be arranged in the first direction DR1 along the other side of the touch sensing area TSA.

[0145] Each of the sense wiring lines RL can be electrically connected with two or more of the sense electrodes RE that are continuous in the first direction DR1.

[0146] The sense wiring lines RL can extend from the yet another side extending in the second direction DR2 to the second touch pad TPD2.

[0147] The sense electrodes RE can be arranged in parallel in the first direction DR1. Adjacent sense electrodes RE in the first direction DR1 can be electrically connected with each other by a protruding portion in the first direction DR1.

[0148] The drive electrodes TE can be arranged in parallel in the second direction DR2. Adjacent drive electrodes TE in the second direction DR2 can be electrically connected with each other by a bridge electrode (BE) in the second direction DR2. Figure 5 and Figure 5

[0149] Each of the drive electrodes TE and the sense electrodes RE can be in a form of surrounding a dummy electrode DE disposed at a corresponding center.

[0150] The dummy electrode DE can be spaced apart from the drive electrodes TE and the sense electrodes RE surrounding the corresponding dummy electrode DE. The dummy electrode DE can be maintained in a floating state.

[0151] Although Figure 7 the drive electrodes TE, the sense electrodes RE, and the dummy electrodes DE are illustrated as being in a planar form of a rhombus, one embodiment is not limited to the illustration. Figure 5 As an example, the planar form of the drive electrodes TE, the sense electrodes RE, and the dummy electrodes DE can be other quadrilaterals than a rhombus, other polygons than quadrilaterals, a circle, or an ellipse.

[0152] Referring to Figure 6 , the drive electrodes TE and the sense electrodes RE can be disposed on the touch interlayer insulating layer 152 covering the bridge electrode BE.

[0153] As Figure 6 and​Figure 6 As shown, the driving electrode TE and the sensing electrode RE can be spaced apart from each other.

[0154] like Figure 6 As shown, the bridging electrode BE can be shaped to include at least one bend. However, this is merely illustrative, and the shape of the bridging electrode BE according to one embodiment is not limited to... Figure 6 The illustration.

[0155] Adjacent drive electrodes TE in the second direction DR2 can be electrically connected to each other through two or more bridging electrodes BE. When configured as described above, the reliability of the electrical connection between the drive electrodes TE can be improved.

[0156] Although Figure 7 This illustration shows a case where two parallel bridging electrodes BE are arranged between adjacent driving electrodes TE in the second direction DR2, but one embodiment is not limited to this. Figure 4 The illustration.

[0157] The bridging electrode BE can be electrically connected to the driving electrode TE through the touch electrode connection hole TCNT.

[0158] Each of the driving electrode TE, sensing electrode RE, and bridging electrode BE can have a planar shape with a grid or mesh structure. The dummy electrode DE can also have a planar shape with a grid or mesh structure. When configured as described above, since the width of overlap between the light-emitting region EA and the driving electrode TE, sensing electrode RE, dummy electrode DE, and bridging electrode BE can be reduced, the reduction in light extraction efficiency of the light-emitting region EA caused by the driving electrode TE, sensing electrode RE, dummy electrode DE, and bridging electrode BE can be reduced.

[0159] Reference Figure 7 The display device 100 according to the embodiment may include a substrate 110, a circuit layer 120 on the substrate 110, a component layer 130 on the circuit layer 120, a sealing layer 140 on the component layer 130, and a touch sensor layer 150 on the sealing layer 140.

[0160] The circuit layer 120 may include a gate insulating layer 122 disposed on the substrate 110, an interlayer insulating layer 123 disposed on the gate insulating layer 122, and a planarization layer 124 disposed on the interlayer insulating layer 123.

[0161] The circuit layer 120 may also include a buffer layer 121 covering the substrate 110. In this case, the gate insulating layer 122 may be disposed on the buffer layer 121.

[0162] Each of the gate insulating layer 122 and the interlayer insulating layer 123 may include an inorganic insulating material.

[0163] The planarization layer 124 can include an organic insulating material.

[0164] The touch sensor layer 150 can include a touch buffer layer 151 disposed on the sealing layer 140, a touch interlayer insulating layer 152 disposed on the touch buffer layer 151, and a touch planarization layer 153 disposed on the touch interlayer insulating layer 152.

[0165] Each of the touch buffer layer 151 and the touch interlayer insulating layer 152 can include an inorganic insulating material.

[0166] The touch planarization layer 153 can include an organic insulating material.

[0167] The element layer 130 can include light emitting elements LE respectively disposed in the light emitting areas EA.

[0168] According to an embodiment, the circuit layer 120 can further include light emitting pixel driving parts EPD respectively electrically connected with the light emitting elements LE of the element layer 130.

[0169] As shown in FIG. 1A, the light emitting pixel driving part EPD can include a first transistor T1 and one or more transistors (e.g., a second transistor T2) and one or more pixel capacitors (e.g., a first pixel capacitor PC1) electrically connected with the first transistor T1. Figure 4 As shown in FIG. 1A, according to an embodiment, the first transistor T1 can include a channel portion CH1, a first electrode portion E11, a second electrode portion E21, and a gate electrode GE1.

[0170] Figure 4 The channel portion CH1, the first electrode portion E11, and the second electrode portion E21 of the first transistor T1 can be disposed in a semiconductor layer on the buffer layer 121.

[0171] The first electrode portion E11 can be connected at one side of the channel portion CH1, and the second electrode portion E21 is connected at the other side of the channel portion CH1.

[0172] The first electrode portion E11 of the first transistor T1 can be electrically connected with a VDL of a first power supply wiring (not shown).

[0173] The gate electrode GE1 of the first transistor T1 can be electrically connected with a gate line (not shown). Figure 4 The gate insulating layer 122 can include a first gate insulating layer 1221 covering the semiconductor layer, and a second gate insulating layer 1222 covering a first gate conductive layer on the first gate insulating layer 1221.

[0174] The interlayer insulating layer 123 can cover a second gate conductive layer on the second gate insulating layer 1222.

[0175] The interlayer insulating layer 123 can cover a second gate conductive layer on the second gate insulating layer 1222.

[0176] ​The gate electrode GE1 can be disposed in the first gate conductive layer on the first gate insulating layer 1221.

[0177] The gate electrode GE1 can overlap with the channel CH1.

[0178] Additionally, the second transistor in each of the light-emitting pixel driving units (EPD) Figure 8 If T2 is configured as a P-type MOSFET like the first transistor T1, it has the same structure as the first transistor T1, so repeated descriptions will be omitted.

[0179] Each light-emitting pixel driving unit EPD of circuit layer 120 may also include a capacitor electrode CAE disposed in the second gate conductive layer on the second gate insulating layer 1222 and overlapping with the gate electrode GE1 of the first transistor T1.

[0180] First pixel capacitor ( Figure 2 PC1 can be set through the overlapping area between the gate electrode GE1 and the capacitor electrode CAE of the first transistor T1.

[0181] The planarization layer 124 may include a first planarization layer 1241 covering the first source-drain conductive layer on the interlayer insulating layer 123, and a second planarization layer 1242 covering the second source-drain conductive layer on the first planarization layer 1241.

[0182] Each light-emitting pixel driving unit EPD of circuit layer 120 may further include a first anode connection electrode ANCE1 disposed in a first source-drain conductive layer on the interlayer insulating layer 123, and a second anode connection electrode ANCE2 disposed in a second source-drain conductive layer on the first planarization layer 1241.

[0183] The first anode connection electrode ANCE1 can be electrically connected to the second electrode portion E21 of the first transistor T1 through a connection hole that penetrates the interlayer insulating layer 123, the second gate insulating layer 1222 and the first gate insulating layer 1221.

[0184] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1 through the connection hole penetrating the first planarization layer 1241.

[0185] Each of the buffer layer 121, the first gate insulating layer 1221, the second gate insulating layer 1222, and the interlayer insulating layer 123 may be composed of at least one inorganic film. As an example, each of the buffer layer 121, the first gate insulating layer 1221, the second gate insulating layer 1222, and the interlayer insulating layer 123 may comprise one or more inorganic films of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0186] Each of the first planarization layer 1241 and the second planarization layer 1242 can include an organic film such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0187] The semiconductor layer can include one of a Poly Silicon, an amorphous silicon, and an oxide semiconductor.

[0188] Each of the first gate conductive layer, the second gate conductive layer, the first source-drain conductive layer, and the second source-drain conductive layer can be formed as a multi-layer of two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0189] Each of the first source-drain conductive layer and the second source-drain conductive layer can include a multi-layer structure in which two or more metal layers are stacked.

[0190] The element layer 130 can be disposed on the planarization layer 124 and include light emitting elements LE respectively disposed in the light emitting areas EA.

[0191] The element layer 130 can include anode electrodes 131 respectively disposed in the light emitting areas EA, a pixel definition layer 132 disposed in a non-light emitting area NEA that is a separation area between the light emitting areas EA and covering edges of each of the anode electrodes 131, a spacer layer 132' disposed on a portion of the pixel definition layer 132, light emitting layers 133 respectively disposed on the anode electrodes 131, and a cathode electrode 134 disposed on the pixel definition layer 132, the spacer layer 132', and the light emitting layers 133.

[0192] That is, each of the light emitting elements LE can include the anode electrode 131 and the cathode electrode 134 facing each other, and the light emitting layer 133 disposed therebetween.

[0193] The element layer 130 can further include a first common layer respectively disposed between the anode electrode 131 and the light emitting layer 133, and a second common layer disposed between the light emitting layer 133 and the cathode electrode 134.

[0194] The anode electrode 131 can be disposed on the second planarization layer 1242 and electrically connected with the second anode connection electrode ANSE2 through a connection hole penetrating the second planarization layer 1242.

[0195] Thus, the anode 131 can be electrically connected with the second anode connection electrode ANCE2 and the first anode connection electrode ANCE1 to the second electrode part E21 of the first transistor T1.

[0196] The first common layer on the anode 131 can include a hole transport layer. Alternatively, the first common layer can further include a hole injection layer between the anode 131 and the hole transport layer.

[0197] The light emitting layer 133 can be disposed on the first common layer.

[0198] The light emitting layer 133 of the first light emitting area EA1, the light emitting layer 133 of the second light emitting area EA2, and the light emitting layer 133 of the third light emitting area EA3 can include organic light emitting materials having different materials or contents from each other.

[0199] As an example, the light emitting layer 133 can be composed of an organic light emitting substance that converts an electron-hole pair into light. The organic light emitting material can include a host substance and a dopant. The dopant can include a phosphorescent substance or a fluorescent substance.

[0200] The cathode 134 and the second common layer below the cathode 134 can be disposed in the display area DA including the light emitting area EA and the non-light emitting area NEA as a whole.

[0201] The second common layer can include an electron transport layer. Alternatively, the second common layer can further include an electron injection layer between the cathode 134 and the electron transport layer.

[0202] The sealing layer 140 can be disposed on the element layer 130 and cover the element layer 130.

[0203] The sealing layer 140 can include a first sealing layer 141 disposed on the element layer 130, a second sealing layer 142 disposed on the first sealing layer 141 and overlapping the element layer 130, and a third sealing layer 143 disposed on the second sealing layer 142 and covering the second sealing layer 142.

[0204] Each of the first sealing layer 141 and the third sealing layer 143 can include a structure in which one or more inorganic film layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are laminated.

[0205] The second sealing layer 142 can include an organic insulating material such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0206] According to an embodiment, the bridge electrode BE in the touch sensor layer 150 can be configured in a first touch conductive layer on the touch buffer layer 151, and the driving electrode TE and the sensing electrode RE can be configured in a second touch conductive layer on the touch interlayer insulating layer 152.

[0207] The dummy electrode DE configured inside each of the driving electrode TE and the sensing electrode RE, the first driving wiring TL1 and the second driving wiring TL2 connected with the driving electrode TE, and the sensing wiring RL connected with the sensing electrode RE can be configured in the second touch conductive layer on the touch interlayer insulating layer 152, the same as the driving electrode TE and the sensing electrode RE.

[0208] The driving electrode TE can be electrically connected with the bridge electrode BE through a touch electrode connection hole TCNT that penetrates the touch interlayer insulating layer 152.

[0209] The touch planarization layer 153 can cover the second touch conductive layer on the touch interlayer insulating layer 152.

[0210] Each of the touch buffer layer 151 and the touch interlayer insulating layer 152 can include a structure in which one or more inorganic film layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are laminated.

[0211] The touch planarization layer 153 can include an organic insulating material such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0212] Figure 8 is a top view showing a substrate and a circuit layer according to an embodiment. Figure 3

[0213] Referring to Figure 4 , the display device 100 according to an embodiment can include a substrate 110, a circuit layer 120, a display driving circuit 200, and a circuit board 300.

[0214] The substrate 110 can include a display area DA in which light emitting areas (EAs) of the display device 100 are arranged in parallel and are configured at a center of one face of the substrate 110, and a non-display area NDA configured at a periphery of the display area DA. Figure 4

[0215] The circuit layer 120 can be configured on the substrate 110.

[0216] ​​The circuit layer 120 can include scan write lines GWL configured in the display area DA and extending in the first direction DR1, and data lines DL configured in the display area DA and extending in the second direction DR2.

[0217] The circuit layer 120 can further include a first power supply line VDSPL configured in the non-display area NDA and transferring the ELVDD of the first power supply (ELVDD), and a second power supply line VSSPL configured in the non-display area NDA and transferring the ELVSS of the second power supply (ELVSS). Figure 5 Figure 8

[0218] The circuit layer 120 can further include circuit bonding pads CBPD mounted in a circuit bonding area CBDA in which the display driving circuit 200 is mounted in the non-display area NDA, circuit connection lines CCNL electrically connected to the circuit bonding pads CBPD, respectively, and substrate bonding pads BBPD arranged in parallel with one side of the circuit bonding pads CBPD adjacent to the edge of the substrate 110 and to which the circuit board 300 is to be bonded.

[0219] When the display driving circuit 200 is mounted, the edge of the circuit bonding area CBDA is parallel to the edge of the display driving circuit 200, and in consideration of this, the reference numerals related to the edge of the circuit bonding area CBDA can also be borrowed as the description related to the edge of the display driving circuit 200 in the following description and the accompanying drawings.

[0220] The circuit bonding pads CBPD can include data output pads DOPD electrically connected to the output terminals of the display driving circuit 200, and data input pads DIPD electrically connected to the input terminals of the display driving circuit 200.

[0221] The circuit connection lines CCNL can include data supply lines DSPL electrically connected to the data output pads DOPD and extending toward the edge of the display area DA, and data pad lines DPDL electrically connected to the data input pads DIPD and extending toward display pads DPD which are a part of the substrate bonding pads BBPD.

[0222] The substrate bonding pads BBPD can include the display pads DPD electrically connected to the display driving circuit 200 through the data pad lines DPDL and the data input pads DIPD, one or more first power supply pads VDPD electrically connected to the first power supply line VDSPL, and one or more second power supply pads VSPD electrically connected to the second power supply line VSSPL.

[0223] Further, as Figure 7 ​​As shown, the substrate bonding pad BBPD can further include touch pads TPD1 and TPD2.

[0224] As shown, according to an embodiment, the display driving circuit 200 can be mounted in the circuit bonding area CBDA by being bonded to the circuit bonding pad CBPD disposed in the circuit bonding area CBDA. Figure 9

[0225] Further, the circuit board 300 can be electrically connected with the display driving circuit 200 and the circuit layer 120 and fixed to the substrate 110 at one side thereof by being bonded to the substrate bonding pad BBPD.

[0226] According to an embodiment, the circuit layer 120 of the display device 100 can further include a lighting circuit TSC disposed in a portion of the circuit bonding area CBDA.

[0227] The lighting circuit TSC can supply various test signals for verifying whether the light emitting elements (LE) of the test element layer 130 are normally driven according to external input before the display driving circuit 200 and the circuit board 300 are bonded. Figure 8

[0228] Figure 10 is a plan view showing the E portion of Figure 9 according to an embodiment. Figure 11 is a sectional view showing the F-F' of Figure 9 Figure 9 is a sectional view showing the G-G' of Figure 8

[0229] As shown, the circuit layer 120 of the display device 100 according to an embodiment can include a first opening portion OP1 overlapping the display driving circuit (200) and penetrating the planarization layer 124. Figure 8 Figure 8 According to an embodiment, the first opening portion OP1 can include a main opening portion MNOP overlapping the display driving circuit (200), and a first sub opening portion SBOP1 extending from a first side SD1 of the main opening portion MNOP opposite the display area (DA) and disposed between the main opening portion MNOP and the display area (DA).

[0230] According to an embodiment, the first opening portion OP1 can include a main opening portion MNOP overlapping the display driving circuit (200), and a first sub opening portion SBOP1 extending from a first side SD1 of the main opening portion MNOP opposite the display area (DA) and disposed between the main opening portion MNOP and the display area (DA). Figure 8 Figure 10 The edge of the main opening portion MNOP can include not only the first side SD1 but also a second side SD2 facing the first side SD1, and a third side SD3 and a fourth side SD4 connected between the first side SD1 and the second side SD2 and facing each other. Figure 8 The edge of the main opening portion MNOP can include not only the first side SD1 but also a second side SD2 facing the first side SD1, and a third side SD3 and a fourth side SD4 connected between the first side SD1 and the second side SD2 and facing each other.

[0231] The edge of the main opening portion MNOP can include not only the first side SD1 but also a second side SD2 facing the first side SD1, and a third side SD3 and a fourth side SD4 connected between the first side SD1 and the second side SD2 and facing each other.​​​​​​

[0232] In this regard, the edge of the main opening MNOP may also include a first vertex ANP1 between the first side SD1 and the third side SD3, a second vertex ANP2 between the first side SD1 and the fourth side SD4, a third vertex ANP3 between the second side SD2 and the third side SD3, and a fourth vertex ANP4 between the second side SD2 and the fourth side SD4.

[0233] According to an embodiment, the first opening OP1 includes a first sub-opening SBOP1 extending from the first side SD1 of the main opening MNOP.

[0234] Therefore, in the second direction DR2 where the first side SD1 and the second side SD2 face each other, the gap G2 between the first side SD1 and the planarization layer 124 can be greater than the gap between the second side SD2 and the planarization layer 124 due to the width of the first sub-opening SBOP1. Figure 8 (G5).

[0235] In other words, with the first opening OP1 penetrating the planarization layer 124, it not only includes the display driving circuit ( Figure 8 The 200) overlapping main opening MNOP, and also includes a first sub-opening SBOP1, which can be larger than the display driving circuit ( Figure 8 200) to the display area ( Figure 8 The DA side extends wider.

[0236] When configured as described above, due to the display driver circuit ( Figure 8 The planarization layer 124 between the display area DA and the display driver circuit (200) can be obtained from the display driver circuit ( Figure 8 The 200) are spaced apart to a width comparable to that of the first sub-opening SBOP1, thus reducing the impact on the display driving circuit ( Figure 8 The installation process of the 200) involves high temperature and high pressure stress, which causes deformation of the organic insulating material of the planarization layer 124. Therefore, the electrical connection to the display driver circuit ( Figure 10 (200) and data wiring for display area DA ( Figure 8 The data supply wiring between the DL and the DSPL has open or short circuit defects.

[0237] As an example, in the second direction DR2, the width G2 of the first sub-opening SBOP1 can be in the range of about 50 μm to 100 μm.

[0238] When the width G2 of the first sub-opening SBOP1 exceeds approximately 100 μm, the inorganic insulating layer of the circuit layer 120, which is not covered by the planarization layer 124 due to the first sub-opening SBOP1, Figure 10The inorganic insulating layers (121, 122, and 123) of the circuit layer 120 can be protected by the first protruding portion PRS1 and the second protruding portion PRS2 of the planarization layer 124. Thus, the warpage defect or the crack defect of the inorganic insulating layers (121, 122, and 123) of the circuit layer 120 can be reduced at the corner portion adjacent to the display area DA and bent in the edge of the display driving circuit (200), i.e., corresponding to the first apex ANP1 and the second apex ANP2.

[0239] On the other hand, in a case where the width G2 of the first sub-opening portion SBOP1 is less than about 50 μm, the deformation of the organic insulating material of the planarization layer 124 caused by the stress of high temperature and high pressure corresponding to the mounting process of the display driving circuit (200) can not be reduced. Figure 8

[0240] According to an embodiment, the planarization layer 124 can include a first protruding portion PRS1 adjacent to a first apex ANP1 between the first side SD1 and the third side SD3 of the main opening portion MNOP, and a second protruding portion PRS2 adjacent to a second apex ANP2 between the first side SD1 and the fourth side SD4 of the main opening portion MNOP.

[0241] That is, the first sub-opening portion SBOP1 can be adjacent to the first protruding portion PRS1 and the second protruding portion PRS2 of the planarization layer 124 in the first direction DR1.

[0242] As described above, with the planarization layer 124 including the first protruding portion PRS1 and the second protruding portion PRS2, the minimum interval G11 between the first apex ANP1 and the planarization layer 124 and the minimum interval G12 between the second apex ANP2 and the planarization layer 124 can be less than the minimum interval G2 between the first side SD1 and the planarization layer 124.

[0243] That is, even though the first opening portion OP1 includes the first sub-opening portion SBOP1, at both ends of the first direction DR1 of the first sub-opening portion SBOP1, the inorganic insulating layers (121, 122, and 123) of the circuit layer 120 can be protected by the first protruding portion PRS1 and the second protruding portion PRS2 of the planarization layer 124. Figure 10 Figure 9 Thus, the warpage defect or the crack defect of the inorganic insulating layers (121, 122, and 123) of the circuit layer 120 can be reduced at the corner portion adjacent to the display area DA and bent in the edge of the display driving circuit (200), i.e., corresponding to the first apex ANP1 and the second apex ANP2. Figure 10

[0244] Thus, the lifespan of the display device 100 can be improved.

[0245] According to an embodiment, as described above, the planarization layer 124 can include the first protruding portion PRS1 adjacent to the first apex ANP1 between the first side SD1 and the third side SD3 of the main opening portion MNOP, and the second protruding portion PRS2 adjacent to the second apex ANP2 between the first side SD1 and the fourth side SD4 of the main opening portion MNOP. Figure 10 ​​​As shown, the planarization layer 124 may further include a third protrusion PRS3 adjacent to the third vertex ANP3 between the second side SD2 and the third side SD3 of the main opening MNOP, and a fourth protrusion PRS4 adjacent to the fourth vertex ANP4 between the second side SD2 and the fourth side SD4 of the main opening MNOP.

[0246] According to one embodiment, the third protrusion PRS3 can be configured to be adjacent to a portion of the third side SD3. That is, the third protrusion PRS3 can be configured parallel to a portion of the third side SD3.

[0247] Furthermore, the fourth protrusion PRS4 can be configured to be adjacent to a portion of the fourth side SD4. That is, the fourth protrusion PRS4 can be configured parallel to a portion of the fourth side SD4.

[0248] According to one embodiment, the first opening OP1 may further include a second sub-opening SBOP2 extending from another part of the third side SD3, excluding the part adjacent to the third protrusion PRS3, and a third sub-opening SBOP3 extending from another part of the fourth side SD4, excluding the part adjacent to the fourth protrusion PRS4.

[0249] Therefore, in the first direction DR1 where the third side SD3 and the fourth side SD4 face each other, the gap G3 between the third side SD3 and the planarization layer 124 can be greater than the gap between the second side SD2 and the planarization layer 124 due to the width of the second sub-opening SBOP2. Figure 8 (G5).

[0250] Furthermore, in the first direction DR1 where the third side SD3 and the fourth side SD4 face each other, the gap G4 between the fourth side SD4 and the planarization layer 124 can be greater than the gap between the second side SD2 and the planarization layer 124 due to the width of the third sub-opening SBOP3. Figure 8 (G5).

[0251] That is, with the first opening OP1 penetrating the planarization layer 124, it not only includes the display driving circuit ( Figure 8 The 200) overlapping main opening MNOP, and also includes a first sub-opening SBOP1, a second sub-opening SBOP2 and a third sub-opening SBOP3, which can be compared with the display driving circuit ( Figure 8 200) in the direction of the display area ( Figure 8 It extends wider in the direction of DA and the second direction DR2.

[0252] When configured as described above, in the display driver circuit ( Figure 8 Between the display area DA and the display area 200, the planarization layer 124 can be drawn from the display driver circuit (Figure 10 The first sub opening portion SBOP1 can be spaced apart from the display driving circuit 200 by a width corresponding to the first sub opening portion SBOP1, and thus deformation of the organic insulating material of the planarization layer 124 caused by stress of high temperature and high pressure corresponding to a mounting process of the display driving circuit 200 can be mitigated. Thus, warping defects or crack defects of the touch interlayer insulating layer 152 and the touch buffer layer 151 disposed on the planarization layer 124 can be reduced. Figure 9 The first sub opening portion SBOP1 can be spaced apart from the display driving circuit 200 by a width corresponding to the first sub opening portion SBOP1, and thus deformation of the organic insulating material of the planarization layer 124 caused by stress of high temperature and high pressure corresponding to a mounting process of the display driving circuit 200 can be mitigated. Thus, warping defects or crack defects of the touch interlayer insulating layer 152 and the touch buffer layer 151 disposed on the planarization layer 124 can be reduced.

[0253] The second sub opening portion SBOP2 can be connected to the first protrusion portion PRS1 and the third protrusion portion PRS3 in the second direction DR2.

[0254] The third sub opening portion SBOP3 can be connected to the second protrusion portion PRS2 and the fourth protrusion portion PRS4 in the second direction DR2.

[0255] That is, according to an embodiment, since the planarization layer 124 includes the first protrusion portion PRS1, the second protrusion portion PRS2, the third protrusion portion PRS3, and the fourth protrusion portion PRS4, a minimum distance between each of the vertices ANP1, ANP2, ANP3, and ANP4, at which two edges extending in different directions from each other in an edge of the main opening portion MNOP are connected, and the planarization layer 124 can be smaller than a minimum distance G2 between the first edge SD1 of the main opening portion MNOP and the planarization layer 124.

[0256] When configured as described above, at a corner portion of an edge of the display driving circuit 200 that is bent, warping defects or crack defects of the inorganic insulating layers 121, 122, and 123 of the circuit layer 120 can be reduced. Thus, the lifespan of the display device 100 can be more improved. Figure 8 As shown in FIG. 1, the display device 100 according to an embodiment can include a circuit layer 120 disposed on a substrate 110, a planarization layer 124 disposed on the circuit layer 120, a touch layer 130 disposed on the planarization layer 124, and a display layer 140 disposed on the touch layer 130.

[0257] As shown in FIG. 1, the display device 100 according to an embodiment can include a circuit layer 120 disposed on a substrate 110, a planarization layer 124 disposed on the circuit layer 120, a touch layer 130 disposed on the planarization layer 124, and a display layer 140 disposed on the touch layer 130. Figure 1 As shown in FIG. 1, the display device 100 according to an embodiment can include a circuit layer 120 disposed on a substrate 110, a planarization layer 124 disposed on the circuit layer 120, a touch layer 130 disposed on the planarization layer 124, and a display layer 140 disposed on the touch layer 130. Figure 8 As shown in FIG. 1, the display device 100 according to an embodiment can include a circuit layer 120 disposed on a substrate 110, a planarization layer 124 disposed on the circuit layer 120, a touch layer 130 disposed on the planarization layer 124, and a display layer 140 disposed on the touch layer 130. Figure 10 As shown in FIG. 1, the display device 100 according to an embodiment can include a circuit layer 120 disposed on a substrate 110, a planarization layer 124 disposed on the circuit layer 120, a touch layer 130 disposed on the planarization layer 124, and a display layer 140 disposed on the touch layer 130. Figure 8 As shown in FIG. 1, the display device 100 according to an embodiment can include a circuit layer 120 disposed on a substrate 110, a planarization layer 124 disposed on the circuit layer 120, a touch layer 130 disposed on the planarization layer 124, and a display layer 140 disposed on the touch layer 130.

[0258] The circuit bonding pad CBPD can include a data output pad DOPD disposed adjacent to a first edge SD1 of the main opening portion MNOP facing the display area DA, and a data input pad DIPD disposed adjacent to a second edge SD2 of the main opening portion MNOP facing the first edge SD1.

[0259] As an example, the data output pads DOPD can be arranged into two or more adjacent pad columns on the second direction DR2.

[0260] Each of two or more pad columns may include a data output pad (DOPD) arranged parallel to each other in the first direction DR1.

[0261] Data output pads (DOPDs) configured in adjacent pad rows can be adjacent in a diagonal direction, rather than parallel in the second direction (DR2). When configured as described above, the configuration of the data supply wiring (DSPL) connected to the data output pads (DOPDs) becomes easier.

[0262] The circuit connection wiring CCNL may include data supply wiring DSPL, which is electrically connected to the data output pad DOPD, and data pad wiring DPDL, which is electrically connected to the data input pad DIPD.

[0263] According to an embodiment, circuit layer 120 may further include a lighting circuit TSC configured between data output pad DOPD and data input pad DIPD.

[0264] Since the lighting circuit TSC is surrounded by the main opening MNOP of the first opening OP1, it can overlap with the display driving circuit 200 and be covered by the planarization layer 124. Thus, even if the lighting circuit TSC overlaps with the display driving circuit 200, it can be electrically and physically protected by the planarization layer 124.

[0265] like Figure 8 As shown, according to an embodiment, the planarization layer 124 of the organic insulating material in the circuit layer 120 may include a first planarization layer 1241 disposed on the interlayer insulating layer 123 and a second planarization layer 1242 covering the first planarization layer 1241.

[0266] The second planarization layer 1242 may include a first step portion ST1 disposed on the first planarization layer 1241 with a first thickness TH1, a bottom extension portion BET facing the first opening portion OP1 and in contact with the interlayer insulating layer 123, and a second step portion ST2 disposed between the first step portion ST1 and the bottom extension portion BET.

[0267] A portion of the second step ST2 adjacent to the first step ST1 can be disposed on the first planarization layer 1241 with a second thickness TH2 that is less than the first thickness TH1.

[0268] According to an embodiment, on a second direction DR2 where the first side SD1 and the second side SD2 face each other, a portion of the second step portion ST2 in the second planarization layer 1242 facing the first side SD1 can be configured with a width W1 larger than the interval G2 between the first side SD1 and the planarization layer 124.

[0269] Furthermore, on the second direction DR2 where the first side SD1 and the second side SD2 face each other, a portion of the bottom surface extension BET in the second planarization layer 1242 facing the first side SD1 can be configured with a width W2 smaller than the interval G2 between the first side SD1 and the planarization layer 124.

[0270] As described above, the second planarization layer 1242 includes a second step portion ST2 with a smaller second thickness TH2, which is configured in the display driving circuit. Figure 9 The amount of organic insulating material around the 200) is reduced, thus reducing the interaction with the display driving circuit ( Figure 10 The high temperature and high pressure stress during the installation process of the 200) affects the planarization layer 124 of the organic insulating material. Therefore, warping or cracking defects of the inorganic insulating layers (i.e., the interlayer insulation layer 152 and the touch buffer layer 151) disposed on the planarization layer 124 can be reduced.

[0271] like Figure 10 As shown, according to an embodiment, the circuit layer 120 may further include a second opening OP2 located between the data output pad DOPD and the lighting circuit TSC on a second direction DR2 where the first side SD1 and the second side SD2 face each other, and a third opening OP3 located between the data input pad DIPD and the lighting circuit TSC.

[0272] The second opening OP2 can extend parallel to the first side SD1.

[0273] The third opening OP3 can extend parallel to the second side SD2.

[0274] like Figure 11 As shown, each of the second opening OP2 and the third opening OP3 can penetrate at least the touch layer insulating layer 152 in the touch buffer layer 151 and the touch layer insulating layer 152. As an example, each of the second opening OP2 and the third opening OP3 can penetrate the touch buffer layer 151 and the touch layer insulating layer 152.

[0275] During the installation of the display driver circuit 200, the second opening OP2 can block the transmission of cracks generated in the touch buffer layer 151 and the inter-touch layer insulation layer 152 on the planarization layer 124 covering the lighting circuit TSC to the data output pad DOPD and the data supply wiring DSPL.

[0276] Likewise, during the mounting process of the display driving circuit 200, a crack generated in the touch buffer layer 151 and the touch interlayer insulating layer 152 on the planarization layer 124 covering the lighting circuit TSC can be blocked from being transmitted to the data input pad DIPD and the data pad wire DPDL through the third opening portion OP3.

[0277] As shown in Figure 9 and Figure 10 , each of the circuit bonding pads (CBPD of the display driving circuit 200; DOPD and DIPD of the display driving circuit 200) can include a first pad layer PDL1, a second pad layer PDL2, and a third pad layer PDL3. Figure 10 Figure 9

[0278] The first pad layer PDL1 can be disposed in the first gate conductive layer on the first gate insulating layer 1221 or the second gate conductive layer on the second gate insulating layer 1222.

[0279] The second pad layer PDL2 can be disposed in the first source / drain conductive layer on the interlayer insulating layer 123 and electrically connected with the first pad layer PDL1 through a connection hole penetrating the gate insulating layer 122 and the interlayer insulating layer 123.

[0280] The third pad layer PDL3 can be disposed in the second touch conductive layer on the touch interlayer insulating layer 152 and electrically connected with the second pad layer PDL2 through a connection hole penetrating the touch buffer layer 151 and the touch interlayer insulating layer 152.

[0281] As shown in Figure 10 , each of the circuit connection wires (CCNL of the display driving circuit 200; DSPL and DPDL of the display driving circuit 200) can be disposed in the first gate conductive layer on the first gate insulating layer 1221 or the second gate conductive layer on the second gate insulating layer 1222. As an example, each of the circuit connection wires (CCNL of the display driving circuit 200; DSPL and DPDL of the display driving circuit 200) can be connected with the first pad layer PDL1 of each of the circuit bonding pads (CBPD of the display driving circuit 200; DOPD and DIPD of the display driving circuit 200). Figure 9 Figure 10 Figure 9 Figure 10 Figure 11 Figure 9

[0282] The lighting circuit TSC can include a wire or an electrode disposed in the first gate conductive layer on the first gate insulating layer 1221 or the second gate conductive layer on the second gate insulating layer 1222.

[0283] The display driving circuit 200 can be mounted in the non-display area NDA of the substrate 110 through the conductive bonding member 220. ​​​​​​​​

[0284] As an example, the display driving circuit 200 can include a bump 210 facing the CBPD of the circuit bonding pad (121, 122, and 123) of the circuit layer 120. Figure 10 Figure 11 Figure 9 The DOPD and the DIPD of the display driving circuit 200.

[0285] The conductive bonding member 220 can include a resin member 222 in which conductive balls 221 are dispersed and which has a bonding property.

[0286] By sandwiching the conductive balls 221 of the conductive bonding member 220 between the bump 210 and the CBPD of the circuit bonding pad (121, 122, and 123) of the circuit layer 120, and the bump 210 of the display driving circuit 200 can be electrically connected to the CBPD of the circuit bonding pad (121, 122, and 123). Figure 12 Figure 13 Figure 8 The DOPD and the DIPD of the display driving circuit 200. Figure 14

[0287] Figure 13 FIG. 10 is a plan view showing the E portion of the display device 100 according to an embodiment. Figure 15 FIG. 11 is a cross-sectional view showing the F-F' of the display device 100 according to an embodiment. Figure 8 FIG. 12 is a plan view showing the E portion of the display device 100 according to an embodiment. Figure 12 FIG. 13 is a cross-sectional view showing the F-F' of the display device 100 according to an embodiment. Figure 9 to Figure 11 FIG. 14 is a plan view showing the E portion of the display device 100 according to an embodiment. Figure 10 FIG. 15 is a plan view showing the E portion of the display device 100 according to an embodiment. Figure 8 FIG. 16 is a plan view showing the E portion of the display device 100 according to an embodiment.

[0288] Except for the case in which one side facing the main opening portion MNOP in each of the first protruding portion PRS1, the second protruding portion PRS2, the third protruding portion PRS3, and the fourth protruding portion PRS4 of the planarization layer 124 of the circuit layer 120 is arc-shaped, Figure 13 The display device 100 according to the embodiment shown in FIG. 1 is actually the same as the embodiment shown in FIG. 2, and thus the repeated description will be omitted below. Figure 14 When configured as described above, the corner portion that is bent in the edge of the display driving circuit 200 is protected by the planarization layer 124, and thus not only the warping defect or the crack defect of the inorganic insulating layer (121, 122, and 123) of the circuit layer 120 can be reduced, but also the area of each of the first sub opening portion SBOP1, the second sub opening portion SBOP2, and the third sub opening portion SBOP3 of the first opening portion OP1 can be widened.

[0289] Figure 9 to Figure 12 Thus, since the warping defect or the crack defect of the inorganic insulating layer (121, 122, and 123) of the circuit layer 120 can be reduced,

[0290] Thus, since the warping defect or the crack defect of the inorganic insulating layer (121, 122, and 123) of the circuit layer 120 can be reduced, Figure 14 ​​​​​​The mounting process of the display driving circuit 200 causes deformation of the organic insulating material due to stress of high temperature and high pressure, and thus can reduce a disconnection defect or a short circuit defect of the data supply line DSPL, and can reduce a warpage defect or a crack defect of the touch interlayer insulating layer 152 and the touch buffer layer 151.

[0291] In a case where the circuit layer 120 further includes the auxiliary opening portion AOP, Figure 9 and Figure 9 The display device 100 of an embodiment shown in Figure 15 is practically the same as the embodiment shown in , and thus the repeated explanation will be omitted below.

[0292] The auxiliary opening portion AOP can be located within the first sub opening portion SBOP1 and extend in parallel with the first side SD1.

[0293] Like the second opening portion OP2, the auxiliary opening portion AOP can at least penetrate the touch interlayer insulating layer 152 among the touch buffer layer 151 and the touch interlayer insulating layer 152.

[0294] The crack of the touch buffer layer 151 and the touch interlayer insulating layer 152, which are disposed on the planarization layer 124 around the first sub opening portion SBOP1, can be blocked from being transmitted to the data output pad DOPD by the auxiliary opening portion AOP.

[0295] Figure 9 to Figure 14 As shown in , in the second direction DR2 in which the first side SD1 and the second side SD2 face each other, the interval G6 between the auxiliary opening portion AOP and the planarization layer 124 can be smaller than the interval G7 between the auxiliary opening portion AOP and the first side SD1.

[0296] When configured as described above, the stress of high temperature and high pressure can be prevented from being concentrated in the auxiliary opening portion AOP at the mounting process of the display driving circuit 200.

[0297] Figure 15 In a case where the planarization layer 124 does not include the third protruding portion (PRS3) and the fourth protruding portion (PRS4) of Figure 8 , the display device 100 of an embodiment shown in ​ is practically the same as the embodiment shown in ​ , and thus the repeated explanation will be omitted below.

[0298] According to an embodiment of ​ , the second sub opening portion SBOP2 can extend from the third side SD3 and be in contact with the first protruding portion PRS1.

[0299] Further, the third sub opening portion SBOP3 can extend from the fourth side SD4 and be in contact with the second protruding portion PRS2.

[0300] When configured as described above, around the second side SD2, not only the inorganic insulating layer of the circuit layer 120 is protected by the planarization layer 124, but also the display driving circuit (200) of the entire third side SD3 and fourth side SD4 is spaced apart from the planarization layer 124, so that the warping defect or the crack defect of the inorganic insulating layer of the circuit layer 120 can be further reduced. ​

[0301] Although the embodiments of the present application have been described with reference to the drawings, it should be understood that, for those skilled in the art, other specific forms can be implemented without changing the technical idea or essential technical features of the present application. Therefore, the above-described embodiments should be understood as exemplary rather than limiting in all aspects.​

Claims

1. A display device, characterized by comprising: The display device includes: a substrate including a display region in which light emitting regions are arranged, and a non-display region disposed at a periphery of the display region; a circuit layer disposed on the substrate; a component layer disposed on the circuit layer; a sealing layer disposed on the component layer; a touch sensor layer disposed on the sealing layer; and a display drive circuit mounted in a part of the non-display region of the substrate, the circuit layer includes a gate insulating layer disposed on the substrate, an interlayer insulating layer disposed on the gate insulating layer, a planarization layer disposed on the interlayer insulating layer, and a first opening portion overlapping the display drive circuit and penetrating the planarization layer, the first opening portion includes a main opening portion overlapping the display drive circuit, and a first sub opening portion extending from a first side of edges of the main opening portion opposite the display region, a minimum interval between each of vertices at which two sides of the edges of the main opening portion extending in different directions from each other and the planarization layer is smaller than a minimum interval between the first side of the main opening portion and the planarization layer, the edges of the main opening portion further include a second side facing the first side, and a third side and a fourth side connected between the first side and the second side and facing each other, the planarization layer includes a first protruding portion adjacent to a first vertex between the first side and the third side, and a second protruding portion adjacent to a second vertex between the first side and the fourth side.

2. The display device according to claim 1, wherein the planarization layer further includes: a third protruding portion disposed adjacent to a third vertex between the second side and the third side and a part of the third side; and a fourth protruding portion disposed adjacent to a fourth vertex between the second side and the fourth side and a part of the fourth side.

3. The display device according to claim 2, wherein the first opening portion further includes: a second sub opening portion extending from another part of the third side and meeting the first protruding portion and the third protruding portion; and a third sub opening portion extending from another part of the fourth side and meeting the second protruding portion and the fourth protruding portion.

4. The display device according to claim 2, wherein the first protruding portion, the second protruding portion, the third protruding portion, and the fourth protruding portion each have an arc shape in a side facing the main opening portion.

5. The display device according to claim 1, wherein the first opening portion further includes: a second sub opening portion extending from the third side and meeting the first protruding portion; and a third sub opening portion extending from the fourth side and meeting the second protruding portion.

6. The display device according to claim 1, further comprising a circuit board disposed adjacent to the display drive circuit and joined at an edge of the substrate, the circuit layer further includes: a circuit joining pad arranged within the main opening portion and for the display drive circuit to be joined to, ​ ​ circuit connection wirings electrically connected to the circuit connection pads, respectively; and a substrate bonding pad arranged in parallel to one side of the edges of the substrate adjacent to the circuit bonding pads and to which the circuit board is to be bonded; the circuit bonding pads include: a data output pad disposed adjacent to the first side, and a data input pad disposed adjacent to the second side; the circuit connection wirings include: a data supply wiring electrically connected to the data output pad and overlapping the first sub opening portion and extending to the edge of the display region, and a data pad wiring electrically connected to the data input pad and extending to a part of the substrate bonding pads; in a direction in which the first side and the second side face each other, a space between the first side and the planarization layer is larger than a space between the second side and the planarization layer due to a width of the first sub opening portion.

7. The display device according to claim 6, wherein the planarization layer includes: a first planarization layer disposed on the interlayer insulating layer, and a second planarization layer covering the first planarization layer; the second planarization layer includes a first step portion disposed on the first planarization layer at a first thickness, a bottom surface extension portion facing the first side and abutting the interlayer insulating layer, and a second step portion disposed between the first step portion and the bottom surface extension portion, a part of the second step portion adjacent to the first step portion is disposed on the first planarization layer at a second thickness smaller than the first thickness, in a direction in which the first side and the second side face each other, a part of the second step portion of the second planarization layer facing the first side is disposed at a width larger than the space between the first side and the planarization layer, the touch sensor layer includes a touch buffer layer disposed on the sealing layer, a touch interlayer insulating layer disposed on the touch buffer layer, and a touch planarization layer disposed on the touch interlayer insulating layer, the touch planarization layer overlaps the first step portion.

8. The display device according to claim 6, wherein the touch sensor layer includes a touch buffer layer disposed on the sealing layer, and a touch interlayer insulating layer disposed on the touch buffer layer, the circuit layer further includes a lighting circuit overlapping the display drive circuit and surrounded by the main opening portion, and disposed between the data output pad and the data input pad and covered by the planarization layer, the lighting circuit is electrically connected to at least a part of the data output pad, the touch buffer layer overlaps the lighting circuit and abuts the interlayer insulating layer in the first opening portion.

9. The display device according to claim 8, wherein the circuit layer further includes: a second opening portion which is located between the data output pad and the lighting circuit in a direction in which the first edge and the second edge face each other, extends in parallel with the first edge, and penetrates at least the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer; and a third opening portion which is located between the data input pad and the lighting circuit in a direction in which the first edge and the second edge face each other, extends in parallel with the second edge, and penetrates at least the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer. 10.The display device according to claim 8, wherein the circuit layer further includes an auxiliary opening portion which is located within the first sub opening portion, extends in parallel with the first edge, and penetrates at least the touch interlayer insulating layer among the touch buffer layer and the touch interlayer insulating layer, in a direction in which the first edge and the second edge face each other, a gap between the auxiliary opening portion and the planarization layer is smaller than a gap between the auxiliary opening portion and the first edge.

Images