Layout structure of shift register

Abstract

The utility model provides a layout structure of a shift register. The layout structure comprises a middle area and a peripheral area surrounding the middle area, the peripheral area is provided with a plurality of input port layout areas, a plurality of parallel output port layout areas, a serial output port layout area, a power port layout area and a grounding port layout area; the middle area is provided with a shift trigger layout area, a register trigger layout area, at least one clock module layout area and at least one output module layout area; and the plurality of shaping and filtering layout areas are connected with the plurality of input port layout areas in a one-to-one correspondence manner and are used for processing input signals from the corresponding input port layout areas and transmitting the processed signals to the shift trigger layout area, the register trigger layout area or the clock module layout area. The shift register adopting the layout structure can effectively suppress input noise; on the basis, due to the fact that the layout structure is reasonably arranged, the layout area is reduced, and the chip area is effectively utilized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular to a layout structure of a shift register. BACKGROUND

[0002] From the basic display driving circuit to the complex communication device; from the industrial level automation control device to the consumer level electronic equipment, the shift register is almost everywhere. It can store data in the internal register through the way of serial input, and output the data to the corresponding position through the way of parallel output and then pass it to the next stage circuit, playing a key role in data transmission, processing and storage, and its characteristics deeply affect the development context of the electronic field.

[0003] With the rapid development of the digital and information age, the data transmission rate requirement is getting higher and higher, and the device sensitivity is getting stronger. In the process of signal transmission, it is easy to be disturbed by the noise of the system environment, resulting in misjudgment.

[0004] In addition, the layout structure of the existing shift register has the problem of wasting chip area, which hinders the miniaturization and integration of the product. CONTENT OF THE INVENTION

[0005] In order to solve or improve the above-mentioned problems in the prior art, the present application provides a layout structure of a shift register, which comprises a middle region and a peripheral region surrounding the middle region.

[0006] The peripheral region is provided with a plurality of input port layout areas, a plurality of parallel output port layout areas, a serial output port layout area, a power port layout area and a ground port layout area.

[0007] The middle region is provided with a plurality of shaping filter layout areas, a shift flip-flop layout area, a register flip-flop layout area, at least one clock module layout area and at least one output module layout area.

[0008] Among them, the plurality of shaping filter layout areas are connected with the plurality of input port layout areas one by one, for processing the input signals from the corresponding input port layout areas, and delivering the processed signals to the shift flip-flop layout area, the register flip-flop layout area or the clock module layout area.

[0009] In the foregoing technical solution, since the shaping filter layout area is added, the input signals of various types can be respectively subjected to shaping filter processing, the ability of the shift register to resist noise signals is improved, and the overall reliability is improved. On the other hand, the layout layout of the peripheral region and the middle region is nested, the port layout area is arranged around the chip, and the logic module layout area is concentrated in the middle of the chip. This design effectively utilizes the limited space on the chip, helps to reduce the size of the chip, and improves the integration of the device.

[0010] Optionally, the shaping filter layout area includes a Schmitt layout area and an inverter layout area, wherein: the Schmitt layout area is equipped with a Schmitt filter module, which can suppress noise in the input signal based on a preset threshold; the inverter layout area is equipped with an inverter shaping module, which can shape the signal processed by the Schmitt filter module.

[0011] The Schmitt filter module has two voltage thresholds. By setting the upper and lower threshold levels, it can effectively suppress noise in the input signal, improving the signal-to-noise ratio and system reliability. The inverter shaping module can shape a slowly changing signal waveform into a steeply edged rectangular wave, and it can also improve the circuit's anti-interference capability, ensuring signal stability. After the input signal is noise-suppressed by the Schmitt filter module, it is sent to the inverter shaping module for shaping, ultimately outputting a complete and clean full-volt signal.

[0012] Optionally, the Schmitt trigger pattern is located between the corresponding input port pattern and the inverter pattern. This way, the input signal from the input port pattern is first processed by the Schmitt trigger pattern to suppress noise, and then shaped by the inverter pattern, which better aligns with signal processing logic.

[0013] Optionally, the peripheral area includes a first side and a third side opposite to each other along a first direction, and a second side and a fourth side opposite to each other along a second direction; the first direction is perpendicular to the second direction; a plurality of input port layout areas are disposed on the first side; a ground port layout area is disposed on the second side; at least a portion of a plurality of parallel output circuit layout areas are disposed on the third side; and a power supply port layout area is disposed on the fourth side.

[0014] Placing the input port layout area and most of the output port layout area at opposite ends of the chip, and placing the power and ground port layout areas at both ends of the overall middle section, facilitates pin bonding during the packaging process, conforms to current chip pin layout rules, and improves the chip's versatility.

[0015] Optionally, in the multiple parallel output port layout areas, the first parallel output port layout area is located at the junction of the first and fourth sides; the remaining parallel output port layout areas are located on the third side and arranged along the second direction; the serial output port layout area is located at the junction of the first and second sides.

[0016] Optionally, the central region includes a first row to a fourth row arranged sequentially from the first side to the third side along a first direction; multiple shaping filter layout areas are set in the first row; shift trigger layout areas are set in the second row; register trigger layout areas are set in the third row; and multiple output module layout areas are set in the first row, the third row, and the fourth row, respectively.

[0017] The aforementioned arrangement places modules with similar heights within the same row of the layout area, preventing uneven layout structures caused by modules of different shapes and avoiding additional area loss. Space is reserved between each row of layout areas for wiring channels, ensuring smooth signal transmission.

[0018] Optionally, multiple output module layout areas include: a serial output module layout area, located at one end of the first row near the serial output port layout area; a first-position parallel output module layout area, located at one end of the third row near the first-position parallel output port layout area; and a remaining-position parallel output module layout area, located in the fourth row.

[0019] Optionally, at least one clock module layout area is provided, including a shift clock module layout area and a register clock module layout area; the shift clock module layout area is located in the second row; the register clock module layout area is located in the third row and is adjacent to the register flip-flop layout area.

[0020] Optionally, in the central region, the layout areas located in the same row have the same height along the first direction. This makes the overall layout more regular, allows sufficient space between layout areas in adjacent rows for metal wiring, and ensures that the metal wiring is relatively straight.

[0021] Optionally, the multiple input port layout areas include: a serial input port layout area and a clear signal port layout area, which are electrically connected to the shift flip-flop layout area via corresponding shaping filter layout areas; an enable signal port layout area, which is electrically connected to the register flip-flop layout area via corresponding shaping filter layout areas; a shift clock signal port layout area, which is electrically connected to the shift clock module layout area via corresponding shaping filter layout areas; and a register clock signal port layout area, which is electrically connected to the register clock module layout area via corresponding shaping filter layout areas.

[0022] The aforementioned technical solution and its optional solutions provide a layout structure that enables shift register chip products using this layout structure to effectively suppress noise in the input signal, achieve accurate data transmission processing, and improve system reliability. In particular, by optimizing the layout structure with added shaping and filtering areas, the arrangement of each layout can be made more compact and reasonable, which is conducive to the miniaturization of shift registers. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.

[0024] Figure 1 This is a schematic diagram illustrating the division of the central and peripheral regions of the layout structure in an embodiment of this application;

[0025] Figure 2This is a detailed division diagram of each area of ​​the layout structure provided in the embodiments of this application;

[0026] Figure 3 This is a schematic diagram of the signals / levels input / output to each port layout area in the layout structure provided in the embodiments of this application;

[0027] Figure 4 This is a schematic diagram of two sub-layout areas included in the shaping and filtering layout area in the layout structure provided in the embodiments of this application.

[0028] The image is labeled as follows:

[0029] 100: Outer area; 200: Central area;

[0030] 110: Multiple input port layout area, 120: Multiple parallel output port layout area, 130: Serial output port layout area, 140: Power supply port layout area, 150: Ground port layout area;

[0031] 210: Multiple shaping filter layout areas; 220: Shift flip-flop layout area; 230: Register flip-flop layout area;

[0032] 111: Serial input port layout area, 112: Enable signal port layout area, 113: Register clock signal port layout area, 114: Shift clock signal port layout area, 115: Clear signal port layout area;

[0033] 121: The layout area of ​​the first parallel output port; 122, 123, 124, 125, 126, 127, and 128 are the layout areas of the second to eighth parallel output ports, respectively.

[0034] 211, 212, 213, 214, and 215 represent the first to fifth shaping filter layout areas, respectively.

[0035] 241: Serial output module layout area; 242: First bit parallel output module layout area; 243: Remainder bit parallel output module layout area.

[0036] 251: Shift clock module layout area; 252: Register clock module layout area;

[0037] 201: Schmidt layout area, 202: Inverter layout area. Detailed Implementation

[0038] This application will now be described more fully below with reference to the accompanying drawings. However, this application can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided herein to make this application more detailed and complete. The same reference numerals denote the same objects throughout the drawings.

[0039] In the specification of the present application, when a component / module / unit is referred to as being "connected to" other components / module / units, such as other components / module / units, the one component / module / unit can be directly connected to or directly coupled to the other components / module / units, or there can also be an intermediate third component / module / unit; in addition, in the embodiments of the present application, "connection" mainly refers to electrical connection, and "adjacent" and "neighboring" mean that two layout areas are joined to each other, or two layout areas are directly close to each other (without including a third layout area between them) and are spaced apart by a preset distance.

[0040] Aiming at the problem in the prior art that a shift register is vulnerable to signal noise interference, the present application provides a layout structure of a shift register. Compared with the prior art, a shaping and filtering layout area is added to effectively suppress input noise, and the layout structure is reasonably arranged to reduce the layout area.

[0041] In the embodiments of the present application, the technical solution of the present application is described by taking an 8-bit shift register as an example, but the present application is not limited thereto. The layout structure provided by the present application can also be applied to shift registers such as 4-bit, 16-bit, 32-bit, and 64-bit, and the specific selection depends on application requirements.

[0042] For the convenience of description and understanding, the embodiments of the present application define "the first direction" and "the second direction" as reference directions, and at the same time define "the first side" to "the fourth side" as the reference areas of the layout. The above definitions are for more accurately disclosing the technical solution of the present application and do not constitute a limitation to the present application.

[0043] As Figure 1 shown, the layout structure provided by the embodiment can be generally divided into a middle area 200 and a peripheral area 100, where the peripheral area 100 surrounds the middle area 200. In a typical embodiment, the middle area 200 is rectangular, and the peripheral area 100 is a hollow rectangle, that is, a "hui" character shape, to surround the four sides of the middle area 200.

[0044] Among them, the peripheral area 100 is used to set up various port layout areas. These port layout areas are provided with, for example, pads (PADs), which can be electrically connected to structures such as pins and leads to input / output signals or access levels. The middle area 200 can be provided with multiple layout areas for implementing logic functions. Obviously, circuits / modules / units for implementing the required logic functions are provided in these layout areas. In the embodiment, the specific structures of the circuits / modules / units not described in detail are all understandable by those skilled in the art and can be selected as appropriate according to the prior art.

[0045] As Figure 2As shown, the peripheral area 100 includes multiple input port layout areas 110, multiple parallel output port layout areas 120, a serial output port layout area 130, a power supply port layout area 140, and a ground port layout area 150. The central area 200 includes multiple shaping filter layout areas 210, shift trigger layout areas 220, register trigger layout areas 230, at least one clock module layout area, and at least one output module layout area.

[0046] Multiple shaping and filtering layout areas 210 are connected one-to-one with multiple input port layout areas 110 to process input signals from the corresponding input port layout areas and send the processed signals to shift trigger layout area 220, register trigger layout area 230, or clock module layout area. Power port layout area 140 and ground port layout area 150 are used to supply power to the entire chip.

[0047] like Figure 4 As shown, the shaping filter layout area further includes the following two sub-layout areas:

[0048] Schmidt layout area 201 is equipped with a Schmidt filter module, which can suppress noise in the input signal based on a preset threshold. Specifically, the Schmidt filter module has two voltage thresholds. By setting the upper and lower threshold levels, it can effectively suppress noise in the input signal, improve the signal-to-noise ratio, and enhance the reliability of the system.

[0049] Inverter layout area 202 is equipped with an inverter shaping module, which can shape the signal processed by the Schmitt filter module. The aforementioned inverter shaping module can shape a signal waveform with slowly changing edges into a rectangular wave with steep edges, and can also improve the circuit's anti-interference capability and ensure signal stability.

[0050] In the aforementioned embodiment, the input signals from multiple input port layout areas 110 are respectively processed by the Schmitt filter module in the corresponding shaping filter layout area for noise suppression, and then transmitted to the inverter shaping module for shaping processing, finally outputting a complete and clean full-volt signal.

[0051] In the corresponding input port layout area and shaping filter layout area, the Schmitt layout area 201 is relatively closer to the input port layout area, that is, the Schmitt layout area is located between the corresponding input port layout area and the inverter layout area, in order to facilitate signal transmission and metal wiring.

[0052] In this embodiment, since each of the multiple input port layout areas 110 is independently connected to a shaping and filtering layout area, various input signals can be processed separately, such as serial input signals, clock signals, clear signals, or enable signals. This allows for comprehensive optimization of the input signals, resulting in better overall reliability of the shift register.

[0053] In a preferred embodiment, such as Figure 2 As shown, the peripheral region 100 includes a first side and a third side opposite each other along a first direction (vertical direction in the figure), and a second side and a fourth side opposite each other along a second direction (horizontal direction in the figure); the first direction is perpendicular to the second direction.

[0054] In another formulation, the peripheral region 100 can be defined as including a first side, a second side, a third side, and a fourth side arranged sequentially in a clockwise or counterclockwise direction. This embodiment uses the example of the peripheral region 100 including the first to fourth sides arranged sequentially in a clockwise direction for illustration.

[0055] Furthermore, multiple input port layout areas 110 are disposed on the first side and arranged sequentially along the second direction, ground port layout area 150 is disposed on the second side, and a portion of the multiple parallel output circuit layout areas 120 (e.g.) Figure 2 The second to eighth parallel output circuit layout areas 122 to 128 shown are located on the third side, and the power port layout area 140 is located on the fourth side.

[0056] In one embodiment, the power port layout area 140 and the ground port layout area 150 are respectively located at the middle position of the fourth side and the second side.

[0057] In this embodiment, the plurality of parallel output port layout areas 120 specifically includes a multi-bit parallel output port layout area. Taking the 8-bit shift register in this embodiment as an example, it includes eight parallel output port layout areas corresponding to eight bits, i.e. Figure 2 The first parallel output port layout area 121 is shown in the figure, and the second to eighth parallel output port layout areas are shown in figures 122 to 128.

[0058] In a preferred embodiment, such as Figure 2 As shown, the first parallel output port layout area 121 of the multiple parallel output port layout areas 120 is located at the junction of the first side and the fourth side, and the serial output port layout area 130 is located at the junction of the first side and the second side.

[0059] In another alternative layout, the first parallel output port layout area 121 is located at the junction of the first and second sides, and the serial output port layout area 130 is located at the junction of the first and fourth sides.

[0060] In other words, the first parallel output port layout area 121 and the serial output port layout area 130 are respectively located in... Figure 2 The top left and top right corners of the map layout can be swapped.

[0061] In the aforementioned preferred embodiment, the remaining output port layout areas 122 to 128 (i.e., the remaining parallel output port layout areas) are arranged sequentially along the second direction on the third side.

[0062] like Figure 2 As shown, in a preferred embodiment, the central region 200 includes a first row to a fourth row arranged sequentially along a first direction, from the side closest to the first side to the side closest to the third side; in other words, it includes a central region 200 along a first direction. Figure 2 The first to fourth rows are arranged sequentially from top to bottom.

[0063] Among them, multiple shaping filter layout areas 210 are set in the first row; shift trigger layout areas 220 (first to eighth bits) are set in the second row; register trigger layout areas 230 (first to eighth bits) are set in the third row; and at least some output module layout areas (e.g., second to eighth bits) are set in the fourth row.

[0064] In a typical embodiment, at least one output module layout area specifically includes: a serial output module layout area 241, which is located at one end of the first row near the serial output port layout area 130. In other words, the serial output module layout area 241 is located in the corner of the central region 200 closest to the serial output port layout area 130.

[0065] The first (first) parallel output module layout area 242 is located in the third row near the first parallel output port layout area 121; the remaining (second to eighth) parallel output module layout areas 243 are located in the fourth row, that is, near the second to eighth parallel output port layout areas.

[0066] In a typical embodiment, such as Figure 2 As shown, at least one clock module layout area includes a shift clock module layout area 251 and a register clock module layout area 252; the shift clock module layout area 251 is located in the second row and is adjacent to the shift flip-flop layout area 220; the register clock module layout area 252 is located in the third row and is adjacent to the register flip-flop layout area 230.

[0067] In the aforementioned embodiments, preferably, within the central region 200, modules located in the same row are arranged at the same height. This avoids uneven layout structures caused by modules of different shapes, which would result in additional area loss. Furthermore, regular spaces are reserved between each layout area as wiring channels to ensure smooth signal transmission.

[0068] In embodiments of this application, the plurality of input port layout areas 110 may specifically include one or more of the following port layout areas, each used to receive different signals, such as... Figure 2 As shown, it includes: serial input port layout area 111, enable signal port layout area 112, register clock signal port layout area 113, shift clock signal port layout area 114, and clear signal port layout area 115.

[0069] In a typical embodiment, such as Figure 2 As shown, the serial input port layout area 111 and the clear signal port layout area 115 are electrically connected to the shift trigger layout area 220 via corresponding shaping filter layout areas. The serial input port layout area 111 receives externally input data to be shifted and transmitted, while the clear signal port layout area 115 controls whether the data is cleared. The enable signal port layout area 112 is electrically connected to the register trigger layout area 230 via a corresponding shaping filter layout area. The enable signal port layout area 112 controls whether the parallel output is in a high-impedance state.

[0070] The shift clock signal port layout area 114 is electrically connected to the shift clock module layout area 251 via a corresponding shaping and filtering layout area; the register clock signal port layout area 113 is electrically connected to the register clock module layout area 252 via a corresponding shaping and filtering layout area. The shift clock signal port layout area 114 is used to control data shifting operations by receiving a clock signal, while the register clock signal port layout area 113 is used to control data latching and output.

[0071] In a typical embodiment, such as Figure 2 The multiple shaping and filtering layout areas 210 specifically include a first shaping and filtering layout area 211, a second shaping and filtering layout area 212, a third shaping and filtering layout area 213, a fourth shaping and filtering layout area 214, and a fifth shaping and filtering layout area 215 arranged from left to right. They are all close to the multiple input port layout areas and are respectively connected to the serial input port layout area 111, the enable signal port layout area 112, the register clock signal port layout area 113, the shift clock signal port layout area 114, and the clear signal port layout area 115, respectively, to shape and filter the signals input to the aforementioned five port layout areas.

[0072] To provide a more detailed explanation of how the shift register works in the embodiments Figure 3 The diagram shows the signals / levels input / output to each port area.

[0073] Please refer to Figure 2 and Figure 3The shift clock control signal SCLK is input through the shift clock signal port layout area 114 and then transmitted to the corresponding fourth shaping and filtering module layout area 214. After noise suppression and shaping, it is transmitted to the shift clock module layout area 251. The clock module in this layout area generates the shift clock control signal and then transmits it to the shift trigger layout area 220.

[0074] The externally input signal SER that needs to be shifted is transmitted to the corresponding first shaping and filtering module layout area 211 after passing through the serial input port layout area 111. After noise suppression and shaping, it is transmitted to the shift trigger layout area 220. In this embodiment, an 8-bit shift trigger module is provided in this layout area. The aforementioned shaped SER signal is first used as the input signal of the first shift trigger module.

[0075] Whenever the SCLK signal flips from low to high, the first to eighth shift trigger modules perform a signal shift transmission. The shaped SER signal is transmitted from the first shift trigger module to the second bit, and the input signal of the second shift trigger module is then transmitted to the third bit, and so on. The input signal of the eighth shift trigger module is used as the shift (serial) output signal QHS after shift transmission, and is led out to the outside through the serial output port layout area 130.

[0076] Meanwhile, the outputs of each bit of the shift trigger module from the first to the eighth bit are respectively transmitted to the first to the eighth bit register triggers set in the register trigger layout area 230, and are used as input signals of the first to the eighth bit register triggers according to the bit number.

[0077] The register clock control signal RCLK is input through the register clock signal port layout area 113 and then transmitted to the corresponding third shaping and filtering module layout area 213. After noise suppression and shaping, it is transmitted to the register clock module layout area 252. Based on the register clock module in this layout area, a register clock control signal is generated and then transmitted to the first to eighth register flip-flop modules in the register flip-flop layout area 230.

[0078] Whenever the signal RCLK flips from low to high, the first to eighth register flip-flops perform a signal transmission. The first register flip-flop transmits the input signal (i.e., the output signal of the first shift flip-flop) to the first parallel output module layout area 242, and then leads it out to the outside through the first parallel output port layout area 121. The second to eighth register flip-flops transmit their respective input signals (i.e., the output signals of the second to eighth shift flip-flops) to the remaining parallel output module layout area 243, and then lead them out to the outside through the multiple remaining parallel output port layout areas 122 to 128 respectively.

[0079] After the shift clear control signal SCLR enters through the clear signal port layout area 115, it is transmitted to the corresponding fifth shaping and filtering module layout area 215. After noise suppression and shaping, the shift clear control signal is generated and then transmitted to the first to eighth shift trigger modules in the shift trigger layout area 220.

[0080] When the SCLR signal is low, all shift triggers from the first to the eighth position are forced to output a low level. When the SCLR signal is high, the shift triggers from the first to the eighth position perform data shifting and transmission processing under the control of the shift clock signal SCLK.

[0081] The enable signal (register flip-flop output status control signal) OE enters through the enable signal port layout area 112 and is transmitted to the corresponding second shaping and filtering module layout area 212. After noise suppression and shaping, the enable signal is generated and then transmitted to the first to eighth register flip-flop modules in the register flip-flop layout area 230.

[0082] When the OE signal is high, all register flip-flops from the first to the eighth bit are forced to output a high-impedance state. When the OE signal is low, the first to the eighth register flip-flops perform data storage and export processing under the control of the register clock signal.

[0083] The following provides the corresponding connection relationship between each package pin and each port layout area of ​​the 8-bit shift register in the embodiment.

[0084] Table 1. Pin List of 8-bit Shift Register

[0085]

[0086]

[0087] In summary, in the aforementioned embodiments, the addition of a shaping and filtering layout area enables the processing of various input signals separately, improving the shift register's ability to resist noise signals and thus enhancing overall reliability.

[0088] On the other hand, by adopting a nested layout of peripheral and central areas, the port layout area is placed around the chip, while the logic module layout area is concentrated in the middle of the chip. This design effectively utilizes the limited space on the chip and helps to reduce the chip size.

[0089] The above description is only a partial embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A layout structure for a shift register, characterized in that, It includes a central region (200) and a peripheral region (100) surrounding the central region (200). The peripheral area (100) is provided with multiple input port layout areas (110), multiple parallel output port layout areas (120), serial output port layout area (130), power supply port layout area (140) and ground port layout area (150). The central region (200) is provided with: multiple shaping filter layout areas (210), shift trigger layout areas (220), register trigger layout areas (230), at least one clock module layout area and at least one output module layout area; The plurality of shaping filter layout areas (210) are connected one-to-one with the plurality of input port layout areas (110) to process the input signals from the corresponding input port layout areas and to send the processed signals to the shift trigger layout area (220), the register trigger layout area (230) or the clock module layout area.

2. The layout structure according to claim 1, characterized in that, The shaping filter layout area includes: The Schmitt pattern area (201) is equipped with a Schmitt filter module, which can suppress noise in the input signal based on a preset threshold. The inverter layout area (202) is equipped with an inverter shaping module, which can shape the signal processed by the Schmitt filter module.

3. The layout structure according to claim 2, characterized in that, The Schmitt layout area (201) is located between the corresponding input port layout area and the inverter layout area (202).

4. The layout structure according to any one of claims 1 to 3, characterized in that, The peripheral region (100) includes a first side and a third side opposite to each other along a first direction, and a second side and a fourth side opposite to each other along a second direction; the first direction is perpendicular to the second direction; The plurality of input port layout areas (110) are disposed on the first side; The grounding port layout area (150) is located on the second side; At least a portion of the plurality of parallel output port layout areas (120) are disposed on the third side; The power port layout area (140) is located on the fourth side.

5. The layout structure according to claim 4, characterized in that, In the plurality of parallel output port layout areas (120), the first parallel output port layout area (121) is located at the junction of the first side and the fourth side; the remaining parallel output port layout areas are located on the third side and are arranged along the second direction. The serial output port layout area (130) is located at the junction of the first side and the second side.

6. The layout structure according to claim 4, characterized in that, The central region (200) includes a first row to a fourth row arranged sequentially along the first direction from the side closest to the first side to the side closest to the third side; The plurality of shaping filter layout areas (210) are set in the first row; The shift trigger layout area (220) is located in the second row; The register trigger layout area (230) is located in the third row; The layout areas of the multiple output modules are respectively set in the first row, the third row, and the fourth row.

7. The layout structure according to claim 6, characterized in that, Multiple output module layout areas, including: The serial output module layout area (241) is located at one end of the first row near the serial output port layout area (130); The first parallel output module layout area (242) is located at one end of the third row near the first parallel output port layout area (121); The remaining parallel output module layout area (243) is located in the fourth row.

8. The layout structure according to claim 6, characterized in that, The at least one clock module layout area includes a shift clock module layout area (251) and a register clock module layout area (252). The shift clock module layout area (251) is located in the second row; The register clock module layout area (252) is located in the third row and is adjacent to the register trigger layout area (230).

9. The layout structure according to claim 6, characterized in that, In the central region (200), the map areas located in the same row have the same height along the first direction.

10. The layout structure according to claim 8, characterized in that, The plurality of input port layout areas (110) include: The serial input port layout area (111) and the clear signal port layout area (115) are electrically connected to the shift trigger layout area (220) via the corresponding shaping filter layout area; The enable signal port layout area (112) is electrically connected to the register trigger layout area (230) via the corresponding shaping filter layout area; The shift clock signal port layout area (114) is electrically connected to the shift clock module layout area (251) via the corresponding shaping filter layout area; The clock signal port layout area (113) is electrically connected to the clock module layout area (252) via the corresponding shaping and filtering layout area.

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