Fast charging chip and fast charging device

Abstract

The utility model discloses a fast charging chip and a fast charging device, and relates to the technical field of electronic circuits, the fast charging chip comprises a USB signal pin and at least two independent bare chips, a Flash memory is arranged on the second bare chip, on the first bare chip, the USB signal pin is connected with a processor, and on the second bare chip, the Flash memory is connected with the processor; and establishing communication connection between the processor and the Flash memory, so that the processor can read a program instruction in the Flash memory to control the chip. According to the fast charging chip provided by the invention, the Flash memory for storing the program and the data is arranged on the independent bare wafer, so that the realization of the memory unit is not limited by a high-voltage BCD process platform designed by a traditional fast charging chip, and can be realized by adopting other process platforms with more advantages in cost and performance; and the requirements that the requirement of a fast charging chip for the storage capacity of a program is larger and larger and the requirement for the reliability of data storage is higher and higher can be met.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a fast charging chip and a fast charging device. Background Technology

[0002] In recent years, USB fast charging technology has developed rapidly, especially in terms of charging speed, safety, and intelligent management. With the high integration of fast charging technology, the control complexity and design difficulty of fast charging systems have also increased accordingly. To improve the ease of system debugging and the flexibility of function upgrades, the core of a fast charging system—the fast charging chip—usually integrates a microcontroller unit (MCU), using software programming to implement system control. This way, design modifications and changes can be easily completed simply by updating the program in the chip's internal memory.

[0003] Fast charging technology typically achieves this by transmitting higher voltages and greater currents. Therefore, fast charging chips must be able to withstand high voltages, which usually means designing on a high-voltage BCD process platform. However, integrating embedded memory IPs such as eFlash and MTP on a high-voltage BCD process not only requires additional mask layers but also results in lower capacity density and less than ideal data retention capabilities. As the integration and complexity of fast charging chips increase, the demand for program memory capacity grows, and the requirements for data storage reliability become increasingly stringent. Clearly, the current method of integrating embedded memory IPs on a high-voltage BCD process is increasingly unable to meet the application requirements of fast charging technology. Utility Model Content

[0004] The purpose of this application is to provide a fast charging chip and a fast charging device that can meet the requirements of fast charging chips for program storage capacity and data storage reliability.

[0005] To achieve the above objectives, this application provides the following solution:

[0006] In a first aspect, this application provides a fast charging chip for establishing communication between a power supply device and a charging device to negotiate charging voltage and charging current. The fast charging chip includes: a USB signal pin, a first bare die, and a second bare die. The USB signal pin is used for fast charging communication between the fast charging chip and the power supply device or the charging device. The first bare die is provided with a fast charging interface circuit, a Flash controller, an SPI interface circuit, and a processor. The second bare die is provided with a Flash memory for storing program instructions and / or data. The processor is used to control the various components of the fast charging chip according to the program instructions stored in the Flash memory.

[0007] Optionally, the first and second bare wafers are interconnected via package leads.

[0008] Optionally, the first bare wafer is implemented using a high-voltage BCD process platform, and the second bare wafer is implemented using an eFlash process platform.

[0009] Optionally, the fast charging interface circuit is connected to the USB signal pin at one end and to the processor at the other end; the processor communicates with the Flash memory through the Flash controller and the SPI interface circuit.

[0010] Optionally, the fast charging interface circuit includes: a Type-C circuit, a DPDM communication circuit, and a PD communication circuit; the Type-C circuit, the DPDM communication circuit, and the PD communication circuit are mounted on the APB bus and connected to the AHB bus through a conversion bridge, and connected to the processor through the AHB bus.

[0011] Optionally, the first bare die also includes: a voltage and current regulation circuit and a path management circuit; the voltage and current regulation circuit and the path management circuit are mounted on the APB bus and connected to the AHB bus through a conversion bridge, and connected to the processor through the AHB bus; the voltage and current regulation circuit is used to adjust and control the fast charging output voltage and fast charging output current according to the communication information of fast charging communication; the path management circuit is used to control the USB port path transistor and detect and respond to abnormalities.

[0012] Secondly, this application provides a fast charging chip for establishing communication between a power supply device and a charging device to negotiate charging voltage and charging current. The fast charging chip includes: a USB signal pin, a first bare die, and a second bare die; the USB signal pin is used for fast charging communication between the fast charging chip and the power supply device and / or the charging device; the first bare die is implemented using a high-voltage BCD process platform and has a fast charging interface circuit, a Flash controller, an SPI interface circuit, and a processor; the second bare die is implemented using an eFlash process platform and has a Flash memory on it, which is used to store program instructions and / or data; the fast charging interface circuit is connected to the USB signal pin at one end and to the processor at the other end; the processor is communicatively connected to the Flash memory through the Flash controller and the SPI interface circuit, and is used to control the various components of the fast charging chip according to the program instructions stored in the Flash memory. The fast charging chip also includes: a third bare die and a fourth bare die; the third bare die has a first power MOSFET, and the fourth bare die has a second power MOSFET; the first power MOSFET and the second power MOSFET are respectively connected to the first bare die through package leads.

[0013] Optionally, the fast charging interface circuit includes: a Type-C circuit, a PD communication circuit, an A-port DPDM communication circuit, a B-port DPDM communication circuit, and a C-port DPDM communication circuit; the Type-C circuit, PD communication circuit, A-port DPDM communication circuit, B-port DPDM communication circuit, and C-port DPDM communication circuit are mounted on the APB bus and connected to the AHB bus through a conversion bridge, and connected to the processor through the AHB bus.

[0014] Optionally, the first bare die also includes: a charge / discharge management circuit, a voltage and current regulation circuit, a path management circuit, and an analog-to-digital conversion circuit; the charge / discharge management circuit, the voltage and current regulation circuit, the path management circuit, and the analog-to-digital conversion circuit are mounted on the APB bus and connected to the AHB bus via a conversion bridge, and connected to the processor via the AHB bus; the charge / discharge management circuit is used to realize bidirectional power conversion management for charging and discharging; the voltage and current regulation circuit is used to adjust and control the fast charging output voltage and fast charging output current according to the communication information of fast charging communication; the path management circuit is used to realize the control of the USB port path transistor and the detection and handling of abnormalities; the analog-to-digital conversion circuit is used to sample the voltage signal, current signal, and temperature signal of the fast charging chip and quantize them into digital signals for the processor's control reference.

[0015] Thirdly, this application provides a fast charging device, which is a charging device, a power supply device, or a bidirectional fast charging device; the fast charging device has one or more fast charging chips as described above built in.

[0016] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0017] This application provides a fast charging chip and a fast charging device. The fast charging chip includes a USB signal pin and at least two independent bare dies. A Flash memory is located on the second bare die, used to store program instructions and / or data. On the first bare die, a fast charging interface circuit establishes a connection between the USB signal pin and a processor, enabling fast charging communication between the fast charging chip and a power supply or charging device. A Flash controller and an SPI interface circuit further establish a communication connection between the processor and the Flash memory, allowing the processor to read the program instructions stored in the Flash memory and control the chip. The fast charging chip proposed in this application integrates two or more interconnected bare dies, with the Flash memory for storing program instructions and / or data located on a separate bare die. This allows the implementation of the storage unit to be implemented without being limited to the high-voltage BCD process platform of traditional fast charging chip designs, and can be implemented using other cost-effective and performance-advantageous process platforms. This meets the increasing demands of fast charging chips for program storage capacity and data storage reliability. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a fast charging chip circuit module provided in one embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the specific structure of a fast charging chip provided in an embodiment of this application.

[0021] Figure 3 This is a schematic diagram of a circuit system for a fast charging chip applied to a single-port fast charging adapter, as provided in one embodiment of this application.

[0022] Figure 4 This is a schematic diagram of the specific structure of a fast charging chip provided in another embodiment of this application.

[0023] Figure 5 This is a schematic diagram of a circuit system for a fast charging chip applied to a multi-port fast charging power bank, as provided in another embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Fast charging chips, due to their high voltage tolerance requirements, are generally designed using a high-voltage BCD process platform. However, integrating embedded storage IPs such as eFlash and MTP on a high-voltage BCD platform requires numerous photomask layers, resulting in lower capacity density and poorer data retention. With increasing integration and complexity, fast charging chips demand ever-larger program storage capacity and higher data storage reliability. Current implementations of integrating embedded storage IPs on high-voltage BCD platforms are increasingly unable to meet the application requirements of fast charging.

[0026] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] In one exemplary embodiment, a fast charging chip is provided for establishing communication between a power supply device and a charging device to negotiate charging voltage and charging current, such as... Figure 1 As shown, the fast charging chip includes: a USB signal pin, a first bare die, and a second bare die; the USB signal pin is used for fast charging communication between the fast charging chip and a power supply device or a charging device; a fast charging interface circuit, a Flash controller, an SPI interface circuit, and a processor are provided on the first bare die; a Flash memory is provided on the second bare die, which is used to store program instructions and / or data; the processor is used to control the various components of the fast charging chip according to the program instructions stored in the Flash memory. In this embodiment, one end of the fast charging interface circuit is connected to the USB signal pin, and the other end is connected to the processor; the processor is communicatively connected to the Flash memory through the Flash controller and the SPI interface circuit.

[0028] In this embodiment, the first bare die is implemented using a high-voltage BCD process platform, and the second bare die is implemented using an eFlash process platform. The design described above places the Flash memory used to store program instructions and / or data on a separate bare die. This allows the implementation of the storage unit to be independent of the high-voltage BCD process platform of traditional fast-charging chip designs, and can be implemented using other process platforms with more cost and performance advantages. This meets the increasing demands of fast-charging chips for program storage capacity and increasingly higher requirements for data storage reliability.

[0029] The first and second bare dies are interconnected via package leads, such as... Figure 2 As shown, the package leads include: a clock lead (SCK), a master output / slave input lead (MOSI), a master input / slave output lead (MISO), and a slave select lead (SS) for communication between the SPI interface circuit and the Flash memory; the package leads also include: a power supply lead (VCC) and a ground lead (GND) for the Flash memory. These package leads can be either traditional bonding leads or advanced redistribution layer (RDL) leads.

[0030] The processor on the first bare die controls the power supply of the VCC pin interconnected with the second bare die through the Flash controller, thereby controlling the power-on and power-off of the Flash memory on the second bare die. The first bare die acts as the master of SPI communication and initiates communication with the Flash memory on the second bare die.

[0031] In this embodiment, the USB signal pins include the DP signal pin, DM signal pin, CC1 signal pin, and CC2 signal pin. The DP signal pin, DM signal pin, CC1 signal pin, and CC2 signal pin all employ a high-voltage withstand design, ensuring that these pins will not be damaged when subjected to a voltage attack from VBUS due to an abnormal short circuit with the VBUS pin.

[0032] Specifically, such as Figure 2 As shown, the fast charging interface circuit includes: a Type-C circuit, a DPDM communication circuit, and a PD communication circuit. These circuits are mounted on the APB bus and connected to the AHB bus via a conversion bridge, connecting to the processor through the AHB bus. The Type-C circuit is used for connection detection, connection direction determination, and signal path configuration of the Type-C interface. The DPDM communication circuit is used to implement fast charging protocol communication using the DP signal pin and / or DM signal pin as the communication channel. These protocols include Qualcomm's QC, Huawei's FCP and SCP, Samsung's AFC, OPPO's VOOC, vivo's VFCP, Transsion's TFCP, and domestic UFCS converged fast charging, etc. The PD communication circuit is used to implement USB Power Delivery fast charging protocol communication using the CC1 signal pin or CC2 signal pin as the communication channel.

[0033] In an exemplary embodiment, a voltage and current regulation circuit and a path management circuit are further provided on the first bare die. The voltage and current regulation circuit and the path management circuit are mounted on the APB bus and connected to the AHB bus via a conversion bridge, and connected to the processor through the AHB bus. The voltage and current regulation circuit is used to regulate and control the fast charging output voltage and fast charging output current according to the communication information of the fast charging communication; the path management circuit is used to control the USB port path transistor and detect and respond to anomalies. The voltage and current regulation circuit regulates and controls the fast charging output voltage and fast charging output current to meet the power supply requirements of the charging device.

[0034] In this embodiment, the processor is an ARM Cortex-M0 processor, a 32-bit RISC processor, which is connected to the Flash controller via the AHB bus. The Flash controller communicates with the Flash memory located on the second die via an SPI interface circuit, reads the program instructions from the Flash memory, and uploads them to the ARM Cortex-M0 processor via the AHB bus. The ARM Cortex-M0 processor executes the acquired program instructions sequentially to control the circuit system of the fast charging adapter.

[0035] When the fast charging chip provided in the above embodiments is applied in a single-port fast charging adapter, its circuit system schematic diagram is as follows. Figure 3 As shown, Figure 3 In the diagram, T1 is the AC / DC transformer, D1 is the secondary rectifier diode, and C1 is the AC / DC output voltage regulator capacitor.

[0036] Figure 3 In this circuit, M1 is the pass transistor for the USB port, and diode D2 is the optocoupler emitter. Resistors R1 and R2 are used to set the bias operating point of the optocoupler drive circuit. Resistor R3 is connected in series with the power ground trace and is connected to the CSP and CSN pins of the fast charging chip to detect the current of the USB port. Capacitor C2 and resistor R4 form a voltage loop compensation network, connected to the VFB and OPTO pins of the fast charging chip; capacitor C3 and resistor R5 form a current loop compensation network, connected to the IFB and OPTO pins of the fast charging chip.

[0037] The VIN pin of the fast charging chip supplies power to the chip and is also used to detect the AC / DC output voltage; the VBUS pin is used to detect the USB port output voltage and to discharge the USB port when the pass transistor M1 is turned off.

[0038] The DP, DM, CC1, and CC2 signal pins in the fast charging chip are connected to the charging device via a USB Type-C connector and a USB cable. Based on the Type-C connection detection method, the CC1 and CC2 signal pins control the power path transistor M1 to conduct when a charging device is detected; conversely, they control the power path transistor M1 to close when the charging device is detected to be removed.

[0039] The charging device selects a communication channel from the DP, DM, CC1, and CC2 USB signal pins for fast charging based on its own charging needs. The fast charging chip, based on the communication with the charging device, adjusts the light intensity of the optocoupler emitter D2 via the OPTO pin to control the voltage and current loops.

[0040] When a voltage boost is needed, the voltage and current regulation circuit in the fast charging chip raises the target voltage of the voltage loop; when a voltage buck is needed, the voltage and current regulation circuit in the fast charging chip lowers the target voltage of the voltage loop. When an increase in output current is needed, the voltage and current regulation circuit in the fast charging chip raises the target current of the current loop; when a decrease in output current is needed, the voltage and current regulation circuit in the fast charging chip lowers the target current of the current loop.

[0041] The processor in the fast charging chip reads the program instructions inside the Flash memory and executes the program instructions in sequence to control the circuit system of the single-port fast charging adapter.

[0042] In another exemplary embodiment of this application, a fast charging chip is also provided, such as... Figure 4 As shown, in addition to the USB signal pins, the first bare die and the second bare die, the fast charging chip also includes a third bare die and a fourth bare die; the third bare die is provided with a first power MOSFET, and the fourth bare die is provided with a second power MOSFET; the first power MOSFET and the second power MOSFET are respectively connected to the first bare die through package leads, and together with the two external power transistors, they serve as the four power transistors of the BUCK-BOOST DCDC.

[0043] In this embodiment, the first bare die and the second bare die are interconnected via package leads, such as... Figure 4 As shown, the package leads include: a clock lead (SCK), a master output / slave input lead (MOSI), a master input / slave output lead (MISO), and a slave select lead (SS) for communication between the SPI interface circuit and the Flash memory; the package leads also include: a power supply lead (VCC) and a ground lead (GND) for the Flash memory. The package leads also include: leads for connecting the first power MOSFET and leads for connecting the second power MOSFET. These package leads can be either traditional bonding leads or advanced redistribution layer (RDL) leads.

[0044] Specifically, the USB signal pins include DPA, DMA, DPB, DMB, DPC, DMC, CC1, and CC2 signal pins. The fast charging interface circuit of the first bare chip includes three sets of DPDM circuits: an A-port DPDM communication circuit bonded to the DPA and DMA signal pins; a B-port DPDM communication circuit bonded to the DPB and DMB signal pins; and a C-port DPDM communication circuit bonded to the DPC and DMC signal pins. These circuits are used to implement fast charging protocol communication using the DP and / or DM signal pins as communication channels. These protocols include Qualcomm's QC, Huawei's FCP and SCP, Samsung's AFC, OPPO's VOOC, vivo's VFCP, Transsion's TFCP, and the domestic UFCS converged fast charging, among others.

[0045] The fast charging interface circuit also includes a Type-C circuit and a PD communication circuit. The Type-C circuit is used to detect the connection of the Type-C interface, determine the connection direction, and configure the signal path. The PD communication circuit is used to implement fast charging communication using the USB Power Delivery fast charging protocol with the CC1 or CC2 signal pin as the communication channel. The Type-C circuit, PD communication circuit, A-port DPDM communication circuit, B-port DPDM communication circuit, and C-port DPDM communication circuit are mounted on the APB bus and connected to the AHB bus through a conversion bridge, and then connected to the processor through the AHB bus.

[0046] The DPA, DMA, DPB, DMB, DPC, DMC, CC1, and CC2 signal pins in this fast charging chip are used to transmit fast charging communication signals, enabling the chip to communicate with mobile phones, tablets, and adapters for fast charging. These USB signal pins are designed with high voltage resistance, ensuring they will not be damaged when subjected to voltage attacks from VBUS due to abnormal short circuits with the VBUS pin.

[0047] As an exemplary embodiment, the first bare die also includes: a charge / discharge management circuit, a voltage and current regulation circuit, a path management circuit, and an analog-to-digital conversion circuit. These circuits are mounted on the APB bus and connected to the AHB bus via a conversion bridge, and then connected to the processor via the AHB bus. The charge / discharge management circuit is used to implement bidirectional power conversion management for charging and discharging. This includes adjusting the voltage and current of the battery in the power bank to the voltage and current required for fast charging output to power the charging device during fast charging; and adjusting the voltage and current provided by the external device to the voltage and current capable of directly charging the battery inside the power bank during fast charging input. The charge / discharge management circuit connects LG1 and HG1 of the first bare die to the gates of MOS1 on the third bare die and MOS2 on the fourth bare die via bonding wires, controlling the MOS transistors to periodically turn on and off to achieve power conversion.

[0048] The voltage and current regulating circuit is used to adjust and control the fast charging output voltage and current based on the communication information of fast charging communication. This includes adjusting and controlling the fast charging output voltage and current during output fast charging to meet the power supply requirements of external charging devices; and adjusting and controlling the input charging voltage and current during input fast charging to meet the charging requirements of the internal battery of the power bank.

[0049] The path management circuit is used to control the USB port path transistors and detect and handle anomalies, including device access and removal detection, identification of charging or power supply devices, and control and management of the conduction and shutdown of each USB port path transistor. The conduction and shutdown of each USB port path transistor are controlled via the GATEA, GATEB, and GATEC pins.

[0050] The analog-to-digital converter circuit is used to sample the voltage, current and temperature signals of the fast charging chip and quantize them into digital signals for the processor to reference during control.

[0051] When the fast charging chip provided in the above embodiments is applied in a multi-port fast charging power bank, its circuit system schematic diagram is as follows. Figure 5 As shown in the diagram, the control core is this fast charging chip, which integrates a BUCK-BOOST DC-DC converter as a charge and discharge management circuit. Figure 5 Power transistors Q5 and Q6, along with the first and second MOS power transistors MOS1 and MOS2 packaged within the fast charging chip, serve as the four power transistors of the BUCK-BOOST DC-DC converter, all connected to inductor L1. Resistor R1 is the current sensing resistor for the VBUS terminal, and resistor R2 is the current sensing resistor for the BAT terminal. Capacitor C1 is the Zener capacitor for the VBUS terminal, and capacitors C2 and C3 are the bootstrap capacitors for the two half-bridges of the BUCK-BOOST DC-DC converter, respectively. Transistor Q1 is the Type-A port access transistor, transistor Q2 is the Type-B port access transistor, and back-to-back transistors Q3 and Q4 are the Type-C port access transistors.

[0052] The DPA and DMA signal pins in the chip are connected to the Type-A port, the DPB and DMB signal pins are connected to the Type-B port, and the CC1, CC2, DPC, and DMC signal pins are connected to the Type-C port. These USB signal pins serve as channels for fast charging communication.

[0053] The charge / discharge management circuit in the fast charging chip is connected to the gates of MOS1 on the third bare die and MOS2 on the fourth bare die via bonding leads, controlling the MOS transistors to periodically turn on and off to achieve power conversion. Specifically, the fast charging chip controls the power transistors Q5 and Q6 to periodically turn on and off via the HG2 and LG2 pins, respectively, to achieve power conversion. The BST2 and SW2 pins are used to implement the bootstrap drive of power transistor Q5; the BST1 and SW1 pins are used to implement the bootstrap drive of MOS2 on the fourth bare die inside the fast charging chip. The VBUSP pin, as the power path, is connected to the drain of MOS2 on the fourth bare die inside the fast charging chip.

[0054] The path management circuit in the fast charging chip is used to detect the access and removal of devices at the Type-A, Type-B, and Type-C ports, identify whether the accessed device is a charging device or a power supply device, and control the conduction and shutdown of the path transistors of each USB port through the GATEA, GATEB, and GATEC pins.

[0055] Specifically, the Type-A port is an output port, usually connected to charging devices; the Type-B port is an input port, usually connected to power supply devices; and the Type-C port is a bidirectional port, which can be connected to both charging and power supply devices.

[0056] When only one USB port has a charging device connected, the circuit of that USB port is turned on, and fast charging is enabled; when both Type-A and Type-C ports have charging devices connected, the circuits of both Type-A and Type-C ports are turned on, fast charging output is disabled, and normal 5V output is enabled.

[0057] When only one USB port has a power supply device connected, the pass transistor of that USB port is turned on, and fast charging input is enabled; when both Type-B and Type-C ports have power supply devices connected, the pass transistor of the Type-C port is turned on and the pass transistor of the Type-B port is turned off, and the Type-C port is selected for fast charging input.

[0058] When both charging and power supply devices are connected to different USB ports, the USB port with the connected device is turned on, fast charging input and fast charging output are disabled, and the device enters a normal 5V charging and discharging state.

[0059] The voltage and current regulation circuit in the fast charging chip controls the output voltage and current of the BUCK-BOOST DC-CDC according to the fast charging communication information to meet the power supply requirements of the external charging device; it also controls the input charging voltage and current of the BUCK-BOOST DC-CDC according to the fast charging communication information to meet the charging requirements of the internal battery of the power bank.

[0060] The analog-to-digital converter circuit in the fast charging chip collects physical information such as VBUS voltage, battery voltage, current flowing through current sensing resistors R1 and R2, chip temperature, and battery temperature, which are then used by the processor to set control strategies, measure battery power, and protect the system from abnormalities.

[0061] Based on the same concept, this application also provides a fast charging device, which can be a charging device, a power supply device, or a bidirectional fast charging device; the fast charging device has one or more built-in fast charging chips as described above. Specifically, the fast charging device can be a power supply device such as an adapter, car charger, and power strip; a charging device such as a mobile terminal, small household appliance, and portable power tool; or a device that can both supply power and charge, such as a power bank and outdoor energy storage power source.

[0062] The innovative fast-charging chip proposed in this invention integrates two or more independent bare dies, which are interconnected via package leads. The Flash memory for storing program instructions and / or data is independently mounted on a single bare die. This design frees the memory implementation from the limitations of the BCD process platform relied upon by traditional fast-charging chip designs. Instead, it can utilize other cost-effective and performance-advantageous process platforms to implement the memory, thereby meeting the increasing demand for program storage capacity and higher requirements for data storage reliability in fast-charging chips. This effectively solves the limitation problem of traditional fast-charging chips using high-voltage BCD process platforms analyzed in the background art.

[0063] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A fast charging chip for establishing communication between a power supply device and a charging device to negotiate charging voltage and charging current, characterized in that, The fast charging chip includes: a USB signal pin, a first bare die, and a second bare die; the USB signal pin is used for fast charging communication between the fast charging chip and a power supply device or a charging device; the first bare die is provided with a fast charging interface circuit, a Flash controller, an SPI interface circuit, and a processor; the second bare die is provided with a Flash memory, which is used to store program instructions and / or data; the processor is used to control the various components of the fast charging chip according to the program instructions stored in the Flash memory.

2. The fast charging chip according to claim 1, characterized in that, The first bare die and the second bare die are interconnected through package leads.

3. The fast charging chip according to claim 2, characterized in that, The first bare wafer is implemented using a high-voltage BCD process platform, and the second bare wafer is implemented using an eFlash process platform.

4. The fast charging chip according to claim 3, characterized in that, The fast charging interface circuit is connected to the USB signal pin at one end and to the processor at the other end; the processor is connected to the Flash memory through the Flash controller and the SPI interface circuit.

5. The fast charging chip according to claim 4, characterized in that, The fast charging interface circuit includes a Type-C circuit, a DPDM communication circuit, and a PD communication circuit. The Type-C circuit, the DPDM communication circuit, and the PD communication circuit are mounted on the APB bus and connected to the AHB bus via a conversion bridge, and are connected to the processor through the AHB bus.

6. The fast charging chip according to claim 5, characterized in that, The first bare die also includes a voltage and current regulation circuit and a path management circuit; the voltage and current regulation circuit and the path management circuit are mounted on the APB bus and connected to the AHB bus through a conversion bridge, and connected to the processor through the AHB bus. The voltage and current regulating circuit is used to adjust and control the fast charging output voltage and fast charging output current according to the communication information of fast charging communication; the path management circuit is used to control the USB port path transistor and detect and respond to abnormalities.

7. The fast charging chip according to claim 3, characterized in that, The fast charging chip further includes: a third bare die and a fourth bare die; the third bare die is provided with a first power MOSFET, and the fourth bare die is provided with a second power MOSFET; the first power MOSFET and the second power MOSFET are respectively connected to the first bare die through package leads.

8. The fast charging chip according to claim 7, characterized in that, The fast charging interface circuit includes: a Type-C circuit, a PD communication circuit, an A-port DPDM communication circuit, a B-port DPDM communication circuit, and a C-port DPDM communication circuit; the Type-C circuit, the PD communication circuit, the A-port DPDM communication circuit, the B-port DPDM communication circuit, and the C-port DPDM communication circuit are mounted on the APB bus and connected to the AHB bus through a conversion bridge, and connected to the processor through the AHB bus.

9. The fast charging chip according to claim 8, characterized in that, The first bare die also includes: a charge / discharge management circuit, a voltage and current regulation circuit, a path management circuit, and an analog-to-digital conversion circuit; the charge / discharge management circuit, the voltage and current regulation circuit, the path management circuit, and the analog-to-digital conversion circuit are mounted on the APB bus and connected to the AHB bus via a conversion bridge, and connected to the processor via the AHB bus; The charging and discharging management circuit is used to realize bidirectional power conversion management for charging and discharging; the voltage and current regulation circuit is used to adjust and control the fast charging output voltage and fast charging output current according to the communication information of fast charging communication; the path management circuit is used to control the USB port path transistor and detect and respond to abnormalities. The analog-to-digital conversion circuit is used to sample the voltage, current, and temperature signals of the fast charging chip and quantize them into digital signals for reference by the processor for control.

10. A fast charging device, wherein the fast charging device is a charging device, a power supply device, or a bidirectional fast charging device; characterized in that, The fast charging device has one or more fast charging chips as described in any one of claims 1-9 built in.

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