Transistor structure and semiconductor device

Abstract

The embodiment of the utility model provides a transistor structure and a semiconductor device, and the transistor structure comprises a gate electrode, a p-type oxide semiconductor channel layer, and a gate dielectric layer between the gate electrode and the p-type oxide semiconductor channel layer. Wherein the main crystal phase of the lattice structure of the p-type oxide semiconductor channel layer is composed of a (110) crystal phase. The oxide semiconductor channel layer has a specific lattice structure to achieve greater charge carrier mobility therein and to prevent or reduce the likelihood of oxygen and / or hydrogen contamination from the gate dielectric layer and other layers around the transistor structure.

Description

Technical Field

[0001] Embodiments of this utility model relate to a transistor structure and a semiconductor device, and more particularly to a back-end transistor structure and a semiconductor device including the back-end transistor structure. Background Technology

[0002] In some cases, transistors can be formed in the interconnect layer of a semiconductor device. The interconnect layer is sometimes referred to as the back end of line (BEOL) region of the semiconductor device. Utility Model Content

[0003] An embodiment of the present invention provides a transistor structure including a gate electrode, a p-type oxide semiconductor channel layer, and a gate dielectric layer between the gate electrode and the p-type oxide semiconductor channel layer, wherein the main crystal phase of the crystal structure of the p-type oxide semiconductor channel layer is composed of (110) crystal phase.

[0004] An embodiment of the present invention provides a semiconductor device including an interconnect layer and a back-end transistor structure on a substrate of the semiconductor device. The interconnect layer includes a plurality of dielectric layers and a plurality of conductive structures in the plurality of dielectric layers. The back-end transistor structure is located in the dielectric layers of the plurality of dielectric layers of the interconnect layer. The back-end transistor structure includes a gate electrode, a p-type oxide semiconductor channel layer, a gate dielectric layer between the gate electrode and the p-type oxide semiconductor channel layer, a first interface layer between the gate dielectric layer and the p-type oxide semiconductor channel layer, and a second interface layer between the dielectric layer of the interconnect layer and the p-type oxide semiconductor channel layer. At least a portion of the lattice structure of the p-type oxide semiconductor channel layer is composed of a (110) crystal phase.

[0005] Based on the above, embodiments of the present invention form a transistor structure in the interconnect layer of a semiconductor device. The transistor structure is formed such that an interface layer is included between the gate dielectric layer and the oxide semiconductor channel layer of the transistor structure. The interface layer provides a substrate on which the oxide semiconductor channel layer can be formed to have a specific lattice structure to achieve a greater charge carrier mobility in the oxide semiconductor channel layer than without the interface layer. Additionally and / or alternatively, the interface layer can prevent or reduce the possibility of oxygen and / or hydrogen contamination from the gate dielectric layer and other layers surrounding the transistor structure.

[0006] To make the above features and advantages of the embodiments of this utility model more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1This is a diagram of an exemplary semiconductor device described herein.

[0008] Figures 2A to 2C This is a diagram of an exemplary embodiment of the transistor structure described herein.

[0009] Figures 3A to 3F This is a diagram of an exemplary embodiment of forming a semiconductor device as described herein.

[0010] Figures 4A to 4I This is a diagram of an exemplary embodiment of the transistor structure described herein.

[0011] Figure 5 This is a diagram of an exemplary embodiment of the transistor structure described herein.

[0012] Figure 6A and Figure 6B This is a diagram of an exemplary embodiment of the transistor structure described herein.

[0013] Figure 7 This is a flowchart of an exemplary process related to forming the transistor structure described herein.

[0014] Explanation of reference numerals in the attached figures

[0015] 100, 108: Semiconductor device; 102: Device layer; 104: Interconnect layer; 106: Substrate; 110: Dielectric layer; 112: Interlayer dielectric (ILD) layer; 114: Etch stop layer (ESL); 116: Conductive structure; 118: Connection structure; 120: Transistor structure; 200, 300, 400, 500, 600, 602: Exemplary embodiments; 202: Gate electrode; 204: Gate dielectric layer; 206, 206a, 206b: Interface Surface layer; 208: p-type oxide semiconductor channel layer; 210, 212: source / drain; 214, 218: lattice structure; 216, 220: adjacent crystal layers; 222: effective mass; 224: charge carrier mobility; 226: gate contact; 402, 404: recess; 700: process; 710, 720: cube; AA: line; D1, D2, D3, D4, D5, D6, D7, D8, D9, D10: size; x, y, z: direction. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, in the following description, the first feature being formed "on" or "on" a second feature may include embodiments where the first and second features are formed in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features are not in direct contact. Furthermore, component numbers and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplification and clarity of description of this disclosure, and is not intended to limit the relationship between various embodiments and / or configurations.

[0017] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. In addition to the orientations depicted in the figures, these spatially relative terms also cover different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used therein can be interpreted in the same manner.

[0018] Forming transistors in the interconnect layer of a semiconductor device typically involves using materials and / or structures different from those used in transistors formed in the device layer (e.g., the front end of line (FEOL) region) of the semiconductor device. While transistors in the device layer can be formed in the semiconductor substrate of the semiconductor device, transistors formed in the interconnect layer are typically formed in the dielectric layer of the semiconductor device. Therefore, oxide semiconductor materials are often used for the channel layer of transistors in the interconnect layer because they integrate better with the dielectric material used in the interconnect layer compared to the semiconductor material used in the channel layer of transistors in the device layer. Specifically, oxide semiconductor materials can be processed at lower temperatures, achieve greater nucleation uniformity on the dielectric material, and / or achieve higher crystallinity on the dielectric material than semiconductor materials such as silicon (Si).

[0019] However, when used in transistors within the interconnect layers of semiconductor devices, some types of oxide semiconductor materials may still face similar challenges as the aforementioned semiconductor materials. For example, p-type oxide semiconductor materials such as tin oxide (SnO) can be used in the channel layer of p-type transistors, and when deposited on, for example, silicon oxide (SiO2),... xWhen applied to dielectric materials, p-type oxide semiconductor materials may suffer from low crystallinity. This can lead to low charge carrier mobility in the channel layer, which reduces the performance of p-type transistors (e.g., reduced switching speed and / or reduced channel control).

[0020] Additionally and / or alternatively, tin oxide may be susceptible to oxygen (O2) and / or hydrogen (H2) contamination from other layers and / or structures within the interconnect layer, leading to performance degradation and / or malfunction of p-type transistors. For example, oxygen contamination can lead to the formation of tin dioxide (SnO2), an n-type material. This can cause threshold voltage shift and / or current leakage in p-type transistors. As another example, hydrogen contamination can lead to the formation of oxygen vacancies in the channel layer of the p-type transistor, which can increase the density of charge carrier donor states in the channel layer, resulting in increased current leakage in the channel layer.

[0021] In some embodiments described herein, the transistor structure may be formed in the interconnect layer (e.g., the back-end region) of the semiconductor device. The transistor structure is formed such that an interface layer is included between the gate dielectric layer and the oxide semiconductor channel layer of the transistor structure. The interface layer provides a substrate on which the oxide semiconductor channel layer may be formed to have a specific lattice structure to achieve a greater charge carrier mobility in the oxide semiconductor channel layer than would be without the interface layer. Additionally and / or alternatively, the interface layer may prevent or reduce the possibility of oxygen (O2) and / or hydrogen (H2) contamination from the gate dielectric layer and other layers surrounding the transistor structure.

[0022] The higher charge carrier mobility in the channel layer enables transistor structures to achieve faster switching speeds and / or provide better channel control. Furthermore, the protection of the oxide semiconductor channel layer from oxygen (O2) contamination provided by the interface layer allows for the maintenance of specific properties of the oxide semiconductor channel layer. For example, the interface layer prevents the oxide semiconductor from transitioning from p-type to n-type materials, which could otherwise occur due to oxygen contamination. Additionally, the protection of the oxide semiconductor channel layer from hydrogen (H2) contamination provided by the interface layer allows for the creation of low oxygen vacancies within the oxide semiconductor channel layer. This enables transistor structures to achieve low current leakage.

[0023] Figure 1This is a diagram of an exemplary semiconductor device 100 described herein. Semiconductor device 100 may include a system-on-a-chip (SoC) device, a logic device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU), a memory device (e.g., a high bandwidth memory (HBM) device), and / or other types of semiconductor devices.

[0024] like Figure 1 As shown, the semiconductor device 100 may include a device layer 102 and an interconnect layer 104 above the device layer 102 in the z-direction of the semiconductor device 100. The device layer 102 may also be referred to as the front-end region or FEOL region of the semiconductor device 100. The interconnect layer 104 may also be referred to as the back-end region or BEOL region of the semiconductor device 100.

[0025] Device layer 102 includes substrate 106. Substrate 106 may correspond to a portion of a semiconductor wafer on which semiconductor device 100 is formed. Substrate 106 may include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates. Substrate 106 may extend in semiconductor device 100 along the x-direction and / or y-direction.

[0026] Semiconductor device 108 may be included in and / or on substrate 106 within device layer 102 of semiconductor device 100. Semiconductor device 108 includes front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (finFET) structures, front-end gate all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, sensors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices. Front-end semiconductor devices refer to semiconductor devices formed in (e.g., within and / or on) device layer 102 of semiconductor device 100.

[0027] A dielectric layer 110 is included on the substrate 106. The dielectric layer 110 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 110 includes one or more dielectric materials that allow various portions of the substrate 106 and / or the semiconductor device 108 to be selectively etched or protected from etching and / or electrically isolated from the semiconductor device 108 in the device layer 102. The dielectric layer 110 includes silicon nitride (Si). x N y ), oxides (e.g., silicon dioxide (SiO2) x (and / or other oxide materials) and / or other types of dielectric materials. The dielectric layer 110 may extend in the x and / or y directions in the semiconductor device 100.

[0028] An interconnect layer 104 of the semiconductor device 100 is included over a substrate 106 and over a semiconductor device 108 in the z-direction of the semiconductor device 100. The interconnect layer 104 includes a plurality of dielectric layers (e.g., back-end dielectric layers) disposed in a direction substantially perpendicular to the substrate 106 (e.g., the z-direction). The dielectric layers may include a plurality of ILD layers 112 and a plurality of ESL layers 114 disposed alternately in the z-direction. The ILD layers 112 and ESL layers 114 may extend in the x-direction and / or y-direction of the semiconductor device 100.

[0029] Each of the ILD layers 112 may comprise an oxide (e.g., silicon oxide (SiO2)). x The dielectric material can be an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogensilsesquioxane (HSQ), or other suitable dielectric materials. In some embodiments, the ILD layer 112 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x ), amorphous fluorinated carbon (aC) xFy), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon carbide (SiOC) polymers, porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silica (SiO2). x )wait.

[0030] ESL 114 may each include silicon nitride (Si) x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, ILD layers 112 and ESL 114 comprise different dielectric materials to provide etching selectivity, thereby enabling the formation of various structures in interconnect layer 104.

[0031] Interconnect layer 104 includes a plurality of conductive structures 116. One or more of the conductive structures 116 are electrically coupled and / or physically coupled to one or more of the semiconductor devices 108 in device layer 102. The conductive structures 116 provide electrical wiring that enables the supply of signals and / or power to and / or from the semiconductor devices 108. The conductive structures 116 may include vias, trenches, contacts, plugs, interconnects, metallization layers, conductive traces, and / or combinations of other types of conductive structures. The conductive structures 116 may be one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of electrically conductive materials. In some embodiments, one or more substrates are included between the conductive structures 116 and ILD layer 112 and / or between the conductive structures 116 and ESL 114. One or more liner layers may include barrier liner layers, adhesive liner layers, and / or other types of liner layers. Exemplary materials for one or more liner layers include tantalum nitride (TaN) and / or titanium nitride (TiN), etc.

[0032] In some embodiments, the conductive structures 116 of the interconnect layer 104 may be arranged vertically (e.g., in the z-direction). In other words, a plurality of stacked conductive structures 116 extend between the device layer 102 and the connection structures 118 above the interconnect layer 104 to facilitate the routing of electrical signals and / or power between the device layer 102 and the connection structures 118. The plurality of stacked conductive structures 116 may be referred to as M layers. For example, a metal 0 (M0) layer may be located at the bottom of the interconnect layer 104 and may be directly coupled to the device layer 102 (e.g., to a contact or via of a semiconductor device 108 in the device layer 102), a metal 1 (M1) layer may be located above the M0 layer in the interconnect layer 104, a metal 2 (M2) layer may be located above the M1 layer, and so on. Additionally, via layers may be included between the vertically arranged M layers. For example, a via 1 (V1) layer may be included between layers M1 and M2 to interconnect layers M1 and M2, a via 2 (V2) layer may be included between layers M2 and M3 to interconnect layers M2 and M3, and so on.

[0033] Connection structure 118 includes solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, and / or other types of connection structures. Connection structure 118 enables semiconductor device 100 to be attached to semiconductor device package substrates (e.g., interposers, redistribution layer (RDL) structures, printed circuit boards (PCBs)) and / or other semiconductor devices.

[0034] The interconnect layer 104 of the semiconductor device 100 also includes one or more semiconductor devices. For example, a transistor structure 120 is included in the ILD layer 112 of the interconnect layer 104. The transistor structure 120 may be referred to as a back-end transistor structure or a BEOL transistor structure because the transistor structure 120 is included in the interconnect layer 104 of the semiconductor device 100 (e.g., a back-end region or a BEOL region), which is opposite to the device layer 102 of the semiconductor device 100 (e.g., a front-end region or a FEOL region). The transistor structure 120 is electrically coupled and / or physically coupled to one or more conductive structures 116 in the interconnect layer 104.

[0035] As mentioned above, Figure 1 This is provided as an example. Other examples are available. Figure 1 The differences described in [the text].

[0036] Figures 2A to 2C This is a diagram of an exemplary embodiment 200 of the transistor structure 120 described herein. (As in conjunction with...) Figure 1 The transistor structure 120, as described, may be referred to as a back-end transistor structure or a BEOL transistor structure, wherein the transistor structure 120 is included in the ILD layer 112 within the interconnect layer 104 of the semiconductor device 100. The transistor structure 120 may also be referred to as a thin-film transistor (TFT) because one or more layers (e.g., a gate dielectric layer, a channel layer) of the transistor structure 120 are formed as a thin film using thin-film deposition techniques. The transistor structure 120 includes an oxide semiconductor channel layer, which allows the fabrication process of the transistor structure 120 to be integrated into the fabrication process of the interconnect layer 104.

[0037] Figure 2A A cross-sectional view of transistor structure 120 is shown. Transistor structure 120 may include a gate electrode 202. Since the gate electrode 202 is located at the bottom of transistor structure 120, it may be referred to as a bottom gate electrode or a buried gate electrode. The gate electrode 202 may be electrically coupled to a gate contact, such as... Figure 2C As shown. The gate electrode 202 may comprise one or more electrically conductive metallic materials having a relatively low coefficient of thermal expansion (CTE). Examples of such electrically conductive metallic materials include platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), iron (Fe), nickel (Ni), cobalt (Co), chromium (Cr), beryllium (Be), antimony (Sb), iridium (Ir), molybdenum (Mo), osmium (Os), thorium (Th), vanadium (V), palladium (Pd), and / or alloys thereof. In some embodiments, the z-direction thickness of the gate electrode 202 (in Figure 2A The value (denoted as D1) is in the range of about 5 nanometers to about 1000 nanometers. However, other values ​​and / or ranges of the z-direction thickness of the gate electrode 202 are also within the scope of this disclosure.

[0038] Transistor structure 120 includes a gate dielectric layer 204. The gate dielectric layer 204 may be included on and / or on the gate electrode 202. The gate dielectric layer 204 may be a high-k gate dielectric layer because it may include one or more high-k dielectric materials with a dielectric constant greater than that of silicon dioxide (SiO2) (approximately 3.9). Examples of such high-k dielectric materials include hafnium oxide (HfO).x For example, HfO2), aluminum oxide (Al) x O y For example, Al2O3) and / or zirconium oxide (ZrO2) x For example, ZrO2, etc. Additionally and / or alternatively, the gate dielectric layer 204 may include silicon oxide (SiO2). x (e.g., SiO2) and / or a low-k dielectric layer. The gate dielectric layer 204 may include a thickness (in the z-direction) of [missing information - likely a thickness in the z-direction]. Figure 2A The thin film layer is denoted as size D2, which includes a range of about 3 nanometers to about 100 nanometers. However, other values ​​and / or ranges of the z-direction thickness of the gate dielectric layer 204 are also within the scope of this disclosure.

[0039] Transistor structure 120 includes an interface layer 206 on and / or on a gate dielectric layer 204 and a p-type oxide semiconductor channel layer 208 on and / or on the interface layer 206. The p-type oxide semiconductor channel layer 208 comprises a p-type oxide semiconductor material, such as tin oxide (SnO). The conductivity of the p-type oxide semiconductor channel layer 208 can be selectively controlled by a gate electrode 202 to selectively allow current to flow between the source and drain (210 and 212) of the transistor structure 120. When a voltage is applied to the gate electrode 202, the p-type oxide semiconductor channel layer 208 can become electrically conductive, thereby allowing current to flow between the source and drain (210 and 212). Conversely, when a voltage is removed from the gate electrode 202, the p-type oxide semiconductor channel layer 208 can become electrically non-conductive, thereby preventing current from flowing between the source and drain (210 and 212).

[0040] An interface layer 206 is included between the bottom surface of the p-type oxide semiconductor channel layer 208 and the top surface of the gate dielectric layer 204 to provide a substrate on which a specific lattice structure of the p-type oxide semiconductor channel layer 208 is formed. The interface layer 206 is composed of a material having a lattice structure 214, wherein when the p-type oxide semiconductor channel layer 208 is formed on the interface layer 206, the lattice constant between adjacent crystal layers 216 (in...) Figure 2A The lattice constant (size D3) in the p-type oxide semiconductor channel layer 208 promotes the formation of a specific lattice structure 218. In particular, the lattice constant (size D3) between adjacent crystal layers 216 in the lattice structure 214 of the interface layer 206 promotes the formation of the (110) crystal phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208.

[0041] Interface layer 206 promotes the growth of the (110) crystal phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208 because when the p-type oxide semiconductor channel layer 208 is formed on interface layer 206, the lattice structure 218 of the p-type oxide semiconductor channel layer 208 approximately conforms to the lattice structure 214 of interface layer 206. This results in a lattice constant between horizontally adjacent crystal layers 220 in the lattice structure 218 of the p-type oxide semiconductor channel layer 208 (in Figure 2A The lattice constant (denoted as size D4) between horizontally adjacent crystal layers 220 in lattice structure 218 can be larger than the vertical distance between molecules in lattice structure 218 (in the case of p-type oxide semiconductor channel layer 208 formed directly on gate dielectric layer 204). Figure 2A The value is represented as D5.

[0042] The formation of a p-type oxide semiconductor channel layer 208 on the interface layer 206 results in a larger lattice constant (size D4) between horizontally adjacent crystal layers 220 in the lattice structure 218, which promotes the formation of the (110) phase in the lattice structure 218. This is because the (110) phase forms with a larger grain size than other phases (e.g., the (001) phase). The larger lattice constant (size D4) between the horizontally adjacent crystal layers 220 and the lattice structure 218 allows for the growth of larger grain sizes in the lattice structure 218, thereby favoring the formation of the (110) phase and inhibiting the growth of other phases (e.g., the (001) phase).

[0043] Therefore, at least a portion of the lattice structure 218 of the p-type oxide semiconductor channel layer 208 is composed of the (110) crystal phase. The (110) crystal phase in the material of the p-type oxide semiconductor channel layer 208 has a greater charge carrier mobility (e.g., a greater hole mobility) compared to other crystal phases (e.g., the (001) crystal phase). For example, the (110) crystal phase may have a charge carrier mobility (e.g., a greater electromobility) that is about 10 times greater than that of the (001) crystal phase. Therefore, compared to the p-type oxide semiconductor channel layer 208 being formed directly on the gate dielectric layer 204 (which could lead to the formation of an amorphous structure in the p-type oxide semiconductor channel layer 208), forming the p-type oxide semiconductor channel layer 208 on the interface layer 206 to promote the growth of the (110) crystal phase in the p-type oxide semiconductor channel layer 208 enables a greater charge carrier mobility to be achieved in the p-type oxide semiconductor channel layer 208. In some embodiments, the lattice structure 218 of the p-type oxide semiconductor channel layer 208 is composed of a majority (110) crystal phase (e.g., at least 50% of the lattice structure 218 is the (110) crystal phase) to enable the p-type oxide semiconductor channel layer 208 to achieve a sufficiently high charge carrier mobility. In some embodiments, the lattice structure 218 of the p-type oxide semiconductor channel layer 208 is composed of about 70% or more of the (110) crystal phase. In some embodiments, the lattice structure 218 of the p-type oxide semiconductor channel layer 208 is composed of about 95% or more of the (110) crystal phase. In some embodiments, the (110) crystal phase is the dominant crystal phase in the lattice structure 218 because the (110) crystal phase constitutes the largest portion of the lattice structure 218 compared to any other crystal phase. The greater the percentage of the lattice structure 218 composed of the (110) crystal phase, the greater the charge carrier mobility achievable in the p-type oxide semiconductor channel layer 208. In some implementations, the charge carrier mobility achievable in the p-type oxide semiconductor channel layer 208 is linearly related to the percentage of the lattice structure 218 composed of the (110) crystal phase.

[0044] Furthermore, compared to forming the p-type oxide semiconductor channel layer 208 directly on the gate dielectric layer 204, forming the p-type oxide semiconductor channel layer 208 on the interface layer 206 to promote the growth of the (110) crystal phase in the p-type oxide semiconductor channel layer 208 results in a larger bandgap in the p-type oxide semiconductor channel layer 208, which enables the transistor structure 120 to achieve a lower off-current (Ioff). The lower the off-current, the less current leakage through the p-type oxide semiconductor channel layer 208.

[0045] In some embodiments, the material of interface layer 206 has a lattice constant (size D3) that is greater than or approximately equal to the lattice constant (size D4) of the (110) phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208. This increases the likelihood of forming the (110) phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208 and / or increases the composition of the (110) phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208. As an example, if the p-type oxide semiconductor channel layer 208 comprises tin oxide (SnO), the lattice constant (size D4) of the (110) phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208 may be approximately 4.89 angstroms. Therefore, in this example, the material of interface layer 206 has a lattice constant (size D3) greater than or approximately equal to 4.89 angstroms. Examples of such materials include strontium oxide (SrO), barium oxide (BaO), and / or calcium oxide (CaO) doped with high concentrations of strontium (Sr) (e.g., about 40% to about 50% by weight of strontium).

[0046] In some embodiments, the material of interface layer 206 has a lattice constant (size D3) greater than the lattice constant (size D4) of the (001) phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208, which also promotes the formation of the (110) phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208. As an example, if the p-type oxide semiconductor channel layer 208 comprises tin oxide (SnO), the lattice constant (size D4) of the (001) phase in the lattice structure 218 of the p-type oxide semiconductor channel layer 208 may be approximately 3.81 angstroms. Therefore, in this example, the material of interface layer 206 has a lattice constant (size D3) greater than 3.81 angstroms. Examples of such materials include magnesium oxide (MgO), calcium oxide (CaO), and / or calcium oxide (CaO) doped with greater than 0% to about 50% by weight of strontium.

[0047] Other examples of materials for interface layer 206 include metal oxide materials, such as yttrium oxide (Y). x O y For example, Y2O3), lithium oxide (Li x O, such as Li₂O) and / or lanthanum oxide (La₂O) x O y For example, La2O3. In some embodiments, the interface layer 206 comprises oxides of two or more metals, such as calcium (Ca), magnesium (Mg), yttrium (Y), lithium (Li), lanthanum (La), strontium (Sr), and / or barium (Ba).

[0048] The metal oxide material of interface layer 206 may also have a sufficiently high band gap (e.g., greater than about 4 electron volts (eV)) such that interface layer 206 does not affect (or minimally affects) gate leakage in transistor structure 120. In some embodiments, the metal oxide material of interface layer 206 has a band gap that is approximately equal to or greater than the band gap of gate dielectric layer 204.

[0049] In addition to promoting the growth of the (110) crystal phase in the p-type oxide semiconductor channel layer 208, the interface layer 206 also blocks, inhibits, and / or resists the diffusion of oxygen (O2) and / or hydrogen (H2) from the layers and / or structures beneath the p-type oxide semiconductor channel layer 208 into the p-type oxide semiconductor channel layer 208. For example, the interface layer 206 also blocks, inhibits, and / or resists the diffusion of oxygen (O2) and / or hydrogen (H2) from the gate electrode 202, the gate dielectric layer 204, and / or the ILD layer 112 beneath the p-type oxide semiconductor channel layer 208 into the p-type oxide semiconductor channel layer 208. The Gibbs free energy change (ΔG) of the metal oxide material of the interface layer 206 can be greater than the Gibbs free energy change of one or more materials of the gate dielectric layer 204 (e.g., high dielectric constant dielectric material, low dielectric constant dielectric material). The significant variation in the Gibbs free energy of the metal oxide material in interface layer 206 enables it to resist intermixing with gate dielectric layer 204 and / or other layers and / or structures (e.g., gate electrode 202 and ILD layer 112). This reduces the likelihood of oxygen (O2) and / or hydrogen (H2) diffusing from these layers and / or structures through interface layer 206 into p-type oxide semiconductor channel layer 208.

[0050] Interface layer 206 may have a z-direction thickness ranging from about 3 nanometers to about 30 nanometers. Figure 2AThe interface layer 206 is a thin film layer (denoted as D6). If the z-direction thickness of the interface layer 206 is less than about 3 nanometers, the interface layer 206 may be insufficient to control the formation of the lattice structure 218 in the p-type oxide semiconductor channel layer 208 and / or the interface layer 206 may be insufficient to prevent oxygen (O2) and / or hydrogen (H2) from diffusing into the p-type oxide semiconductor channel layer 208. If the z-direction thickness of the interface layer 206 is greater than about 30 nanometers, the total oxide thickness between the gate electrode 202 and the p-type oxide semiconductor channel layer 208 (which may correspond to the thickness of the gate dielectric layer 204 and the thickness of the interface layer 206) may result in insufficient control over the conductivity in the p-type oxide semiconductor channel layer 208. If the z-direction thickness of the interface layer 206 is within the range of approximately 3 nm to approximately 30 nm, sufficient control over the formation of the lattice structure 218 in the p-type oxide semiconductor channel layer 208 can be achieved, as can sufficient blocking of the diffusion of oxygen (O2) and / or hydrogen (H2), while simultaneously achieving sufficient control over the conductivity in the p-type oxide semiconductor channel layer 208. However, other values ​​for the z-direction thickness of the interface layer 206, and ranges other than approximately 3 nm to approximately 30 nm, are also within the scope of this disclosure. Furthermore, for embodiments where the transistor structure 120 uses a higher gate voltage, such as a medium-voltage transistor or a high-voltage transistor embodiment, the thickness of the interface layer 206 can be greater.

[0051] The p-type oxide semiconductor channel layer 208 may have a z-direction thickness ranging from about 0.5 nanometers to about 30 nanometers. Figure 2A The thin film layer is denoted as D7. However, other values ​​and / or ranges of the z-direction thickness of the p-type oxide semiconductor channel layer 208 are also within the scope of this disclosure.

[0052] The source / drain electrodes (210 and 212) are located on and / or on the p-type oxide semiconductor channel layer 208. The source / drain electrodes (210 and 212) may be in direct physical contact with the p-type oxide semiconductor channel layer 208, or one or more layers (e.g., pads, barrier layers, adhesive layers) may be included between the p-type oxide semiconductor channel layer 208 and the source / drain electrodes (210 and 212). The term "source / drain" may refer individually or collectively to the source region or the drain region, depending on the context. Each source / drain electrode (210 and 212) may comprise one or more electrically conductive materials, such as one or more metals and / or one or more metal-containing materials. Examples of such materials include aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), gold (Au), platinum (Pt), nickel (Ni), titanium nitride (TiN), and / or indium tin oxide (ITO). In some implementations, the z-direction thickness of each of the source / drain electrodes (210 and 212) is greater than about 5 nanometers. However, other values ​​and / or ranges of the z-direction thickness of each of the source / drain electrodes (210 and 212) are also within the scope of this disclosure.

[0053] The source / drain (210 and 212) can each be electrically coupled to a conductive structure 116 in the interconnect layer 104 of the semiconductor device 100. This allows an electrical input (e.g., voltage, current) to be applied to the source / drain (210 and / or 212) and / or allows the source / drain (210 and / or 212) to be electrically grounded.

[0054] Figure 2B The relationship between the lattice constant (size D4) of the lattice structure 218 of the p-type oxide semiconductor channel layer 208 and the effective mass 222 and charge carrier mobility 224 in the p-type oxide semiconductor channel layer 208 is shown. Figure 2B As shown, as the lattice constant (size D4) of the lattice structure 218 increases, the effective mass 222 in the p-type oxide semiconductor channel layer 208 decreases. Therefore, the charge carrier mobility 224 in the p-type oxide semiconductor channel layer 208 decreases, resulting in reduced current leakage in the p-type oxide semiconductor channel layer 208 and improved switching speed.

[0055] Figure 2C A top view of transistor structure 120 and along its length are shown. Figure 2A The position of the cross section of line AA in the diagram. For example... Figure 2CAs shown, the source / drain electrodes (210 and 212) can extend laterally outward in the y-direction of the semiconductor device 100 through multiple sides of the p-type oxide semiconductor channel layer 208. Similarly, the gate electrode 202 can extend laterally outward in the y-direction of the semiconductor device 100 through multiple sides of the p-type oxide semiconductor channel layer 208, and laterally outward through the source / drain electrodes (210 and 212). This allows the gate contact 226 to be formed on the gate electrode 202.

[0056] like Figure 2C As further shown, transistor structure 120 may have one or more additional sizes, such as size D8, size D9, and / or size D10, etc. Size D8 corresponds to the y-direction width of p-type oxide semiconductor channel layer 208. In some embodiments, size D8 includes a range from about 5 nanometers to about 1000 nanometers. However, other values ​​and / or ranges of size D8 are also within the scope of this disclosure. Size D9 corresponds to the x-direction distance between the source / drain (210 and 212). Size D9 may also be referred to as the gate length (Lg) of transistor structure 120. In some embodiments, size D9 includes a range from about 5 nanometers to about 1000 nanometers. However, other values ​​and / or ranges of size D9 are also within the scope of this disclosure. Size D10 corresponds to the x-direction width of the source / drain (210 and / or 212). In some embodiments, size D10 includes a range from about 5 nanometers to about 1000 nanometers. However, other values ​​and / or ranges of size D10 are also within the scope of this disclosure.

[0057] As mentioned above, providing Figures 2A to 2C As an example. Other examples can be related to... Figures 2A to 2C The differences mentioned above.

[0058] Figures 3A to 3F This is a diagram of an exemplary embodiment 300 of the semiconductor device 100 described herein. In some embodiments, combined with Figures 3A to 3F One or more of the semiconductor processing operations may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or other types of semiconductor processing tools.

[0059] Instead of referring to Figure 3A A substrate 106 is provided. The substrate 106 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor workpieces.

[0060] like Figure 3BAs shown, a semiconductor device 108 (e.g., a front-end semiconductor device) may be formed in and / or on a substrate 106 within a device layer 102 of the semiconductor device 100. One or more semiconductor processing tools may be used to form one or more portions of the semiconductor device 108. For example, deposition tools may be used to perform various deposition operations to deposit layers and / or structures of the semiconductor device 108 and / or to deposit photoresist layers for etching the substrate 106 and / or portions of the deposited layers. As another example, exposure tools may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, development tools may be used to develop the pattern in the photoresist layer. As another example, etching tools may be used to etch the substrate 106 and / or portions of the deposited layers to form the semiconductor device 108. As another example, planarization tools may be used to planarize portions of the semiconductor device 108. As another example, electroplating tools may be used to deposit metal structures and / or layers of the semiconductor device 108.

[0061] like Figure 3C As shown, a deposition tool is used to deposit a dielectric layer 110 on and / or on a substrate 106 and on and / or on a semiconductor device 108. The deposition tool can be used to deposit the dielectric layer 110 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. In some embodiments, after depositing the dielectric layer 110, a planarization tool can be used to planarize the dielectric layer 110.

[0062] like Figure 3D As shown, a first portion of the interconnect layer 104 of the semiconductor device 100 is formed on the dielectric layer 110. One or more deposition tools are used to deposit alternating layers of ILD layers 112 and ESL layers 114 in the first portion of the interconnect layer 104 of the semiconductor device 100. In this manner, the ILD layers 112 and ESL layers 114 can be arranged in the z-direction of the semiconductor device 100. One or more deposition tools can be used to deposit each of the ILD layers 112 and ESL layers 114 using PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, after depositing the ILD layers 112 and / or ESL layers 114, planarization tools can be used to planarize the ILD layers 112 and / or ESL layers 114.

[0063] like Figure 3DAs further shown, various operations are performed using deposition tools, exposure tools, development tools, etching tools, planarization tools, and / or electroplating tools to form a conductive structure 116 in a first portion of the interconnect layer 104. The conductive structure 116 may be included in the ILD layer 112 and / or ESL 114 and may be electrically coupled to the semiconductor device 108 in the device layer 102. In some embodiments, the ILD layer 112, ESL 114, and conductive structure 116 may be constructed in the z-direction of a metallization layer. For example, a first ESL 114 and a first ILD layer 112 may be formed, a recess may be formed in the first ESL 114 and / or the first ILD layer 112, and the first conductive structure 116 (e.g., a MO metallization layer) may be formed in the recess. A second ESL 114 and a second ILD layer 112 may be formed over the first ESL 114 and the first ILD layer 112. Recesses may be formed in the second ESL 114 and / or the second ILD layer 112, and a second conductive structure 116 (e.g., an M1 metallization layer) may be formed in the recesses. The remaining metallization layers of the first portion of the interconnect layer 104 may be formed in a similar manner. Additionally, via layers may be formed to interconnect the metallization layers in the interconnect layer 104. The via layers may include conductive structures 116 corresponding to vias or interconnect lines that interconnect two or more metallization layers in the interconnect layer 104.

[0064] like Figure 3E As shown, a second portion of the interconnect layer 104 of the semiconductor device 100 is formed on and / or on the first portion of the interconnect layer 104. (Executable and compatible) Figure 3D A similar technique is used to form the second portion of the interconnect layer 104. Additionally, a transistor structure 120 (e.g., a back-end transistor structure or a BEOL transistor structure) is formed in the ILD layer 112 within the second portion of the interconnect layer 104. A conductive structure 116 may be formed on the transistor structure 120 to electrically connect it to the transistor structure 120 within the interconnect layer 104. Figures 4A to 4I An exemplary embodiment forming the transistor structure 120 is shown and described.

[0065] like Figure 3F As shown, a third portion of the interconnect layer 104 may be formed over the second portion of the interconnect layer 104, which includes the transistor structure 120. The third portion of the interconnect layer 104 can be used in conjunction with... Figure 3D and Figure 3E The techniques described are formed by similar combinations.

[0066] like Figure 3FAs further shown, the connection structure 118 is formed on the interconnect layer 104, such that the connection structure 118 is electrically coupled and / or physically coupled to one or more conductive structures 116 in the interconnect layer 104. Deposition tools can be used employing CVD, PVD, ALD, electroplating, and / or combinations thereof. Figure 1 Other deposition techniques besides those described above are used to deposit the interconnect structure 118. In some embodiments, semiconductor packaging tools attach the interconnect structure 118 to the semiconductor device 100.

[0067] As mentioned above, providing Figures 3A to 3F As an example. Other examples can be related to... Figures 3A to 3F The differences mentioned above.

[0068] Figures 4A to 4I This is a diagram of an exemplary embodiment 400 of the transistor structure 120 described herein. In some embodiments, combined with Figures 4A to 4I One or more of the semiconductor processing operations described herein may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, developing tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools. See also Figure 4A The operations described in exemplary embodiment 400 can be performed in conjunction with the ILD layer 112 of the interconnect layer 104 of the semiconductor device 100. The operations described in exemplary embodiment 400 can be performed in conjunction with the formation of the semiconductor device 100, such as in conjunction with... Figures 3A to 3F As described above. For example, the operations described in exemplary embodiment 400 may be performed in conjunction with forming interconnect layer 104, such as in conjunction with... Figure 3E As mentioned above.

[0069] like Figure 4B As shown, the gate electrode 202 can be formed on the ILD layer 112. The deposition tools can utilize CVD, PVD, ALD, electroplating, and / or a combination thereof. Figure 1 Other deposition techniques besides those described are used to deposit the gate electrode 202. In some embodiments, after depositing the gate electrode 202, a planarization tool can be used to perform a chemical mechanical planarization (CMP) operation to planarize the gate electrode 202.

[0070] like Figure 4CAs shown, a gate dielectric layer 204 may be formed on and / or on the gate electrode 202. Deposition tools may be used to deposit the gate dielectric layer 204 using CVD, PVD, ALD, oxidation, and / or other suitable deposition techniques. In some embodiments, after depositing the gate dielectric layer 204, a planarization tool may be used to perform a CMP operation to planarize the gate dielectric layer 204.

[0071] like Figure 4D As shown, interface layer 206 may be formed on and / or on gate dielectric layer 204. Deposition tools may be used to deposit interface layer 206 using ALD, CVD, PVD, and / or other suitable deposition techniques. In some embodiments, after depositing interface layer 206, a CMP operation is performed using a planarization tool to planarize interface layer 206.

[0072] Interface layer 206 may include a material (e.g., a metal oxide material) having a lattice structure 214 having a lattice constant (size D3) that satisfies a lattice constant threshold. For example, interface layer 206 may include a material (e.g., a metal oxide material) having a lattice structure 214 having a lattice constant (size D3) that is approximately equal to or greater than the lattice constant of a particular crystalline phase to be realized in the p-type oxide semiconductor channel layer 208 formed on interface layer 206. Specifically, interface layer 206 may include a material (e.g., a metal oxide material) having a lattice structure 214 having a lattice constant (size D3) that is approximately equal to or greater than the lattice constant of the (110) crystalline phase to be realized in the p-type oxide semiconductor channel layer 208 formed on interface layer 206.

[0073] like Figure 4E As shown, a p-type oxide semiconductor channel layer 208 is formed on and / or on the interface layer 206. Deposition tools can be used to deposit the p-type oxide semiconductor channel layer 208 using ALD, CVD, PVD, and / or other suitable deposition techniques. In some embodiments, after depositing the p-type oxide semiconductor channel layer 208, a CMP operation is performed using a planarization tool to planarize the p-type oxide semiconductor channel layer 208.

[0074] The formation of a p-type oxide semiconductor channel layer 208 on the interface layer 206 results in the lattice constant (size D4) of the p-type oxide semiconductor channel layer 208 conforming to the lattice constant (size D3) of the interface layer 206. The lattice constant (size D4) of the p-type oxide semiconductor channel layer 208 conforming to the lattice constant (size D3) of the interface layer 206 promotes the growth of the (110) crystal phase in the p-type oxide semiconductor channel layer 208 lattice structure 218.

[0075] like Figure 4F As shown, a stack of layers including a gate electrode 202, a gate dielectric layer 204, an interface layer 206, and a p-type oxide semiconductor channel layer 208 can be etched to define a transistor structure 120. In some embodiments, a pattern in a photoresist layer is used to etch the layer stack to define the transistor structure 120. In these embodiments, a photoresist layer can be formed on the p-type oxide semiconductor channel layer 208 using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the gate electrode 202, the gate dielectric layer 204, the interface layer 206, and the p-type oxide semiconductor channel layer 208 to define the transistor structure 120 according to the pattern. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, photoresist removal tools can be used to remove the remainder of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or other techniques). In some embodiments, a hard shielding layer is used as an alternative technique for etching the layer stack according to a pattern.

[0076] like Figure 4G As shown, additional material for the ILD layer 112 may be formed on and / or on the p-type oxide semiconductor channel layer 208. Furthermore, additional material may be formed in the ILD layer 112 such that the transistor structure 120 is encapsulated by the ILD layer 112. Deposition tools may be used to deposit the additional material for the ILD layer 112 using ALD technology, CVD technology, PVD technology, oxidation technology, and / or other suitable deposition techniques. In some embodiments, after depositing the additional material for the ILD layer 112, a planarization tool is used to perform a CMP operation to planarize the ILD layer 112.

[0077] like Figure 4HAs shown, recesses (402 and 404) may be formed in and / or through the ILD layer 112, such that multiple portions of the top surface of the p-type oxide semiconductor channel layer 208 are exposed through the recesses (402 and 404). In some embodiments, a pattern in the photoresist layer is used to etch the ILD layer 112 to form the recesses (402 and 404). In these embodiments, a photoresist layer may be formed on the ILD layer 112 using a deposition tool. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the ILD layer 112 according to the pattern to form the recesses (402 and 404) in the ILD layer 112. In some embodiments, the etching operations include plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using chemical stripping, plasma ashing, and / or other techniques). In some embodiments, a hard shielding layer is used as an alternative technique for etching the ILD layer 112 according to a pattern.

[0078] like Figure 4I As shown, the source / drain electrodes (210 and 212) are formed in the recesses (402 and 404), respectively. The source / drain electrodes (210 and 212) may be located on the portions of the p-type oxide semiconductor channel layer 208 exposed by the recesses (402 and 404), such that the source / drain electrodes (210 and 212) are electrically and / or physically coupled to the p-type oxide semiconductor channel layer 208.

[0079] Deposition tools can be used to deposit source / drain electrodes (210 and 212) using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. In some embodiments, after depositing the source / drain electrodes (210 and 212), a planarization tool can be used to planarize the top surfaces of the source / drain electrodes (210 and 212). The planarization of the source / drain electrodes (210 and 212) results in the top surfaces of the source / drain electrodes (210 and 212) and the top surface of the ILD layer 112 being substantially coplanar.

[0080] As mentioned above, providing Figures 4A to 4I As an example. Other examples may be found related to... Figures 4A to 4I The differences mentioned above.

[0081] Figure 5 This is a diagram of an exemplary embodiment 500 of the transistor structure 120 described herein. Figure 5 As shown, an exemplary embodiment 500 of the transistor structure 120 is similar to the combination of Figures 2A to 2CAn exemplary embodiment 200 of the transistor structure 120 shown and described. However, in Figure 5 In an exemplary embodiment 500 of the transistor structure 120, a p-type oxide semiconductor channel layer 208 of the transistor structure 120 is included between a plurality of interface layers (206a and 206b). In particular, the p-type oxide semiconductor channel layer 208 is included on the interface layer 206a, and the interface layer 206b is included on the p-type oxide semiconductor channel layer 208.

[0082] An interface layer 206a is included between the bottom surface of the p-type oxide semiconductor channel layer 208 and the top surface of the gate dielectric layer 204. Therefore, the interface layer 206a is included between the p-type oxide semiconductor channel layer 208 and the gate electrode 202. The interface layer 206a provides a substrate on which the p-type oxide semiconductor channel layer 208 is formed to have a specific lattice structure. In particular, the interface layer 206a provides a substrate on which the p-type oxide semiconductor channel layer 208 is formed such that at least a portion of the lattice structure 218 of the p-type oxide semiconductor channel layer 208 is composed of the (110) crystal phase. The interface layer 206a also blocks, inhibits, and / or resists the diffusion of oxygen (O2) and / or hydrogen (H2) from layers and / or structures (e.g., gate electrode 202, gate dielectric layer 204) below the p-type oxide semiconductor channel layer 208 into the p-type oxide semiconductor channel layer 208.

[0083] An interface layer 206b is included between the top surface of the p-type oxide semiconductor channel layer 208 and the ILD layer 112. The interface layer 206b blocks, inhibits, and / or resists the diffusion of oxygen (O2) and / or hydrogen (H2) from layers and / or structures above the p-type oxide semiconductor channel layer 208 (e.g., ILD layer 112) into the p-type oxide semiconductor channel layer 208. Therefore, the combination of the interface layers (206a and 206b) protects the p-type oxide semiconductor channel layer 208 from the diffusion of oxygen (O2) and / or hydrogen (H2) from multiple directions and / or locations within the semiconductor device 100. In some embodiments, the interface layer 206a promotes the formation of a (110) crystalline phase at and / or near the bottom of the p-type oxide semiconductor channel layer 208, and the interface layer 206b promotes the formation of a (110) crystalline phase at and / or near the top of the p-type oxide semiconductor channel layer 208. In this manner, both the interface layers (206a and 206b) can further increase the (110) crystal phase composition in the lattice structure 218 of the p-type oxide semiconductor channel layer 208. For example, after the p-type oxide semiconductor channel layer 208 is formed on the interface layer 206a, the (110) crystal phase can constitute about 75% of the lattice structure 218 of the p-type oxide semiconductor channel layer 208, and after the interface layer 206a is formed on the p-type oxide semiconductor channel layer 208, the (110) crystal phase can constitute about 95% of the lattice structure 218 of the p-type oxide semiconductor channel layer 208. However, other values ​​are also within the scope of this disclosure.

[0084] In some embodiments, the interface layers (206a and 206b) comprise the same material and / or the same combination of materials. In some embodiments, the interface layers (206a and 206b) comprise different materials and / or different combinations of materials. In some embodiments, the interface layers (206a and 206b) comprise the same dopant material and / or substantially the same doping concentration. In some embodiments, the interface layers (206a and 206b) comprise different dopant materials and / or different doping concentrations. In some embodiments, the interface layers (206a and 206b) are formed to have substantially the same z-direction thickness. In some embodiments, the interface layers (206a and 206b) are formed to have different z-direction thicknesses.

[0085] During the formation of gate dielectric layer 204 (bonding) Figure 4C After the formation of the p-type oxide semiconductor channel layer 208 (as described above), and in conjunction with the formation of the p-type oxide semiconductor channel layer 208, Figure 4E Prior to the aforementioned step, an interface layer 206a may be formed on the gate dielectric layer 204. The interface layer 206a may be bonded to… Figure 4E Formed in a similar manner as described above. In the formation of the p-type oxide semiconductor channel layer 208 (bonded... Figure 4EFollowing the formation of the ILD layer 112, and in conjunction with the additional material (bonded) Figure 4G Prior to the aforementioned step, an interface layer 206b may be formed on the p-type oxide semiconductor channel layer 208. The interface layer 206b can be bonded to… Figure 4E It is formed in a similar manner as described above.

[0086] Source / drain electrodes (210 and 212) can be formed through the interface layer 206b, so that the source / drain electrodes 210 and 212 fall on and are in physical contact with the p-type oxide semiconductor channel layer 208. Recesses (402 and 404) (bonded) Figure 4H (Description) A p-type oxide semiconductor channel layer 208 can be formed through the interface layer 206b to expose the p-type oxide semiconductor channel layer 208. Therefore, because the source / drain (210 and 212) are formed in the recesses 402 and 404 extending through the interface layer 206b (in combination with...) Figure 4I Therefore, the interface layer 206b can surround the bottom portion of the source / drain (210 and 212) and can be in physical contact with the bottom portion of the source / drain (210 and 212).

[0087] As mentioned above, Figure 5 Provided as an example. Other examples are available. Figure 5 The differences described in [the text].

[0088] Figure 6A and Figure 6B This is an exemplary embodiment of the transistor structure 120 described herein. Figure 6A An exemplary embodiment 600 of the transistor structure 120 is shown, and Figure 6B An exemplary embodiment 602 of the transistor structure 120 is shown.

[0089] like Figure 6A As shown, an exemplary embodiment 600 of the transistor structure 120 is similar to the combination of Figure 2A An exemplary embodiment 200 of the transistor structure 120 shown and described. For example, an exemplary embodiment 600 of the transistor structure 120 includes a p-type oxide semiconductor channel layer 208 on an interface layer 206. However, with Figure 2A In contrast to the bottom gate electrode in exemplary embodiment 200, transistor structure 120 includes Figure 6A The top gate electrode in the exemplary embodiment 600. Therefore, in Figure 6A In the exemplary embodiment 600, the gate dielectric layer 204 and the gate electrode 202 are included on the p-type oxide semiconductor channel layer 208, which is connected to... Figure 5In the exemplary embodiment 500, the opposite is true below the p-type oxide semiconductor channel layer 208. Gate electrode 202 and gate dielectric layer 204 are included between the source / drain electrodes (210 and 212). Gate dielectric layer 204 is included between gate electrode 202 and p-type oxide semiconductor channel layer 208.

[0090] An interface layer 206 is included between the bottom surface of the p-type oxide semiconductor channel layer 208 and the ILD layer 112. The interface layer 206 provides a substrate on which the p-type oxide semiconductor channel layer 208 is formed to have a specific lattice structure. Specifically, the interface layer 206 provides a substrate on which the p-type oxide semiconductor channel layer 208 is formed such that at least a portion of the lattice structure 218 of the p-type oxide semiconductor channel layer 208 is composed of a (110) crystal phase. The interface layer 206 also blocks, inhibits, and / or resists the diffusion of oxygen (O2) and / or hydrogen (H2) from layers and / or structures (e.g., ILD layer 112) below the p-type oxide semiconductor channel layer 208 into the p-type oxide semiconductor channel layer 208. The interface layer 206 may be formed before the gate electrode 202 is formed and before the gate dielectric layer 204 is formed. The interface layer 206 is also formed during the formation of the p-type oxide semiconductor channel layer 208 (in conjunction with...). Figure 4E The interface layer 206 is formed prior to the aforementioned. Except in the exemplary embodiment 600 of the transistor structure 120, where the interface layer 206 is formed on the ILD layer 112 instead of on the gate dielectric layer 204, the interface layer 206 may be combined with... Figure 4D It is formed in a similar manner as described above.

[0091] Except that the gate dielectric layer 204 is formed on the p-type oxide semiconductor channel layer 208 in the exemplary embodiment 600 of the transistor structure 120, rather than on the gate electrode 202, the gate dielectric layer 204 may be combined with Figure 4D Formed in a similar manner. Except that the gate electrode 202 is formed on the gate dielectric layer 204 in the exemplary embodiment 600 of the transistor structure 120, rather than in the recess 402 in the ILD layer 112, the gate electrode 202 is combined with... Figure 4B It is formed in the manner described.

[0092] Source / drain electrodes (210 and 212) can be formed such that the source / drain electrodes (210 and 212) fall on and are in physical contact with the p-type oxide semiconductor channel layer 208. Recesses (402 and 404) and source / drain electrodes (210 and 212) formed in the recesses (402 and 404) can be formed on opposite sides of the gate electrode 202.

[0093] like Figure 6BAs shown, an exemplary embodiment 602 of the transistor structure 120 is similar to the combination of Figure 5 An exemplary embodiment 500 of the transistor structure 120 shown and described. For example, an exemplary embodiment 602 of the transistor structure 120 includes a p-type oxide semiconductor channel layer 208 on an interface layer 206a and an interface layer 206b on the p-type oxide semiconductor channel layer 208.

[0094] However, with Figure 5 In contrast to the bottom gate electrode in the exemplary embodiment 500, the transistor structure 120 is in Figure 6B The exemplary embodiment 602 includes a top gate electrode. Therefore, in Figure 6B In the exemplary embodiment 602, the gate dielectric layer 204 and the gate electrode 202 are included on the p-type oxide semiconductor channel layer 208, which is connected to... Figure 5 In the exemplary embodiment 500, the gate electrode 202 and the gate dielectric layer 204 are included below the p-type oxide semiconductor channel layer 208. The gate dielectric layer 204 is included between the source / drain electrodes (210 and 212). The gate dielectric layer 204 is included between the gate electrode 202 and the interface layer 206b (e.g., the interface layer on top of the p-type oxide semiconductor channel layer 208), rather than between the gate electrode 202 and the interface layer 206a (e.g., the interface layer below the p-type oxide semiconductor channel layer 208).

[0095] An interface layer 206a is included between the bottom surface of the p-type oxide semiconductor channel layer 208 and the ILD layer 112. The interface layer 206a provides a substrate on which the p-type oxide semiconductor channel layer 208 is formed to have a specific lattice structure. Specifically, the interface layer 206a provides a substrate on which the p-type oxide semiconductor channel layer 208 is formed such that at least a portion of the lattice structure 218 of the p-type oxide semiconductor channel layer 208 is composed of the (110) crystal phase. The interface layer 206a also blocks, inhibits, and / or resists the diffusion of oxygen (O2) and / or hydrogen (H2) from layers and / or structures (e.g., ILD layer 112) below the p-type oxide semiconductor channel layer 208 into the p-type oxide semiconductor channel layer 208. An interface layer 206b is included between the top surface of the p-type oxide semiconductor channel layer 208 and the bottom surface of the gate dielectric layer 204. Therefore, the interface layer 206a is included between the p-type oxide semiconductor channel layer 208 and the gate electrode 202. Interface layer 206b blocks, inhibits, and / or resists the diffusion of oxygen (O2) and / or hydrogen (H2) from layers and / or structures (e.g., gate electrode 202, gate dielectric layer 204) above p-type oxide semiconductor channel layer 208 into p-type oxide semiconductor channel layer 208. Therefore, the combination of interface layers (206a and 206b) protects p-type oxide semiconductor channel layer 208 from diffusion of oxygen (O2) and / or hydrogen (H2) from multiple directions and / or locations within semiconductor device 100.

[0096] In forming the p-type oxide semiconductor channel layer 208 (bonded) Figure 4E Following the formation of the ILD layer 112, and in conjunction with the additional material (bonded) Figure 4G Prior to the aforementioned step, interface layer 206b may be formed on p-type oxide semiconductor channel layer 208. Interface layer 206b may be bonded to... Figure 4D It is formed in a similar manner as described above.

[0097] Except that the gate dielectric layer 204 is formed on the interface layer 206b in the exemplary embodiment 600 of the transistor structure 120, rather than on the gate electrode 202, the gate dielectric layer 204 may be combined with Figure 4D Formed in a similar manner. Except that the gate electrode 202 is formed on the gate dielectric layer 204 in the exemplary embodiment 600 of the transistor structure 120, rather than in the recess 402 in the ILD layer 112, the gate electrode 202 is combined with... Figure 4B It is formed in the manner described.

[0098] Source / drain electrodes (210 and 212) can be formed through the interface layer 206b, allowing the source / drain electrodes (210 and 212) to settle on and physically contact the p-type oxide semiconductor channel layer 208. Recesses (402 and 404) (bonded) Figure 4H (Description) A channel layer 208 (p-type oxide semiconductor channel layer 208) can be formed through the interface layer 206b. Therefore, because the source / drain electrodes (210 and 212) are formed in the recesses (402 and 404) extending through the interface layer 206b (in combination) Figure 4I Therefore, the interface layer 206b can surround the bottom portion of the source / drain (210 and 212) and can be in physical contact with the bottom portion of the source / drain (210 and 212). The recesses (402 and 404) and the source / drain (210 and 212) formed in the recesses (402 and 404) can be formed on opposite sides of the gate electrode 202.

[0099] As mentioned above, providing Figure 6A and Figure 6B As an example. Other examples may be found related to... Figure 6A and Figure 6B The differences mentioned.

[0100] Figure 7 This is a flowchart of an exemplary process 700 related to forming the transistor structure described herein. In some embodiments, one or more semiconductor processing tools (e.g., deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or other types of semiconductor processing tools) are used to perform the process. Figure 7 One or more process blocks.

[0101] like Figure 7 As shown, process 700 may include an interface layer (block 710) for forming a back-end transistor structure. For example, one or more semiconductor processing tools may be used to form an interface layer (e.g., interface layer 206, interface layer 206a) for a back-end transistor structure (e.g., transistor structure 120), as described herein.

[0102] like Figure 7As further shown, process 700 may include forming a p-type oxide semiconductor channel layer (block 720) on the interface layer to form a back-end transistor structure. For example, one or more semiconductor processing tools may be used to form the p-type oxide semiconductor channel layer (e.g., p-type oxide semiconductor channel layer 208) on the interface layer to form the back-end transistor structure, as described herein. In some embodiments, forming the p-type oxide semiconductor channel layer on the interface layer results in the lattice constant (size D4) of the p-type oxide semiconductor channel layer (e.g., lattice structure 218) conforming to the lattice constant (size D3) of the interface layer (e.g., lattice structure 214).

[0103] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or any combination of embodiments related to one or more other processes described elsewhere herein.

[0104] In the first embodiment, the lattice constant of the p-type oxide semiconductor channel layer, which conforms to the lattice constant of the interface layer, promotes the growth of the (110) crystal phase in the lattice structure of the p-type oxide semiconductor channel layer.

[0105] In the second embodiment, forming an interface layer, alone or in combination with the first embodiment, includes forming an interface layer on a high-dielectric-constant gate dielectric layer (e.g., gate dielectric layer 204) of the back-end transistor structure.

[0106] In the third embodiment, forming an interface layer, alone or in combination with one or more of the first and second embodiments, includes forming an interface layer on a back dielectric layer (e.g., ILD layer 112) in an interconnect layer (e.g., interconnect layer 104) of a semiconductor device (e.g., semiconductor device 100).

[0107] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, process 700 includes forming another interface layer (e.g., interface layer 206, interface layer 206b) on the p-type oxide semiconductor channel layer.

[0108] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 700 includes forming a high-k dielectric gate dielectric layer (e.g., gate dielectric layer 204) of a back-end transistor structure on another interface layer and forming a gate electrode (e.g., gate electrode 202) of the back-end transistor structure on the high-k dielectric gate dielectric layer.

[0109] Although Figure 7 An example block of process 700 is shown, but in some embodiments, process 700 is... Figure 7The blocks shown may include additional blocks, fewer blocks, different blocks, or blocks arranged differently. Alternatively, two or more of the blocks in process 700 may be executed in parallel.

[0110] In this manner, a transistor structure can be formed in the interconnect layer (e.g., the back-end region) of a semiconductor device. Forming the transistor structure involves including an interface layer between the gate dielectric layer and the oxide semiconductor channel layer of the transistor structure. The interface layer provides a substrate on which the oxide semiconductor channel layer can be formed to have a specific lattice structure to achieve a higher charge carrier mobility in the oxide semiconductor channel layer than would be without the interface layer. Additionally and / or alternatively, the interface layer can prevent or reduce the possibility of oxygen (O2) and / or hydrogen (H2) contamination from the gate dielectric layer and other layers surrounding the transistor structure.

[0111] As described in more detail above, some embodiments described herein provide a transistor structure. The transistor structure includes a gate electrode. The transistor structure includes a p-type oxide semiconductor channel layer, wherein the dominant crystalline phase (majority) of the lattice structure of the p-type oxide semiconductor channel layer is composed of the (110) crystalline phase. The transistor structure includes a gate dielectric layer between the gate electrode and the p-type oxide semiconductor channel layer.

[0112] In some embodiments, the transistor structure further includes an interface layer between the gate dielectric layer and the p-type oxide semiconductor channel layer, wherein the interface layer comprises a metal oxide material. In some embodiments, the metal oxide material of the interface layer has a Gibbs free energy change greater than that of the material of the gate dielectric layer. In some embodiments, the metal oxide material comprises at least one of the following: calcium oxide, yttrium oxide, lithium oxide, lanthanum oxide, strontium oxide, magnesium oxide, or barium oxide. In some embodiments, the metal oxide material comprises strontium-doped calcium oxide. In some embodiments, the gate electrode is below the p-type oxide semiconductor channel layer in the transistor structure, and the p-type oxide semiconductor channel layer is on the top surface of the interface layer. In some embodiments, the gate electrode is above the p-type oxide semiconductor channel layer in the transistor structure, and the interface layer is on the top surface of the p-type oxide semiconductor channel layer.

[0113] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes an interconnect layer on a substrate of the semiconductor device, the interconnect layer including a plurality of dielectric layers and a plurality of conductive structures within the plurality of dielectric layers. The semiconductor device includes a back-end transistor structure within the dielectric layers of the plurality of dielectric layers of the interconnect layer, wherein the back-end transistor structure includes: a gate electrode, a p-type oxide semiconductor channel layer, wherein at least a portion of the lattice structure of the p-type oxide semiconductor channel layer is composed of a (110) crystal phase, a gate dielectric layer between the gate electrode and the p-type oxide semiconductor channel layer, a first interface layer between the gate dielectric layer and the p-type oxide semiconductor channel layer, and a second interface layer between the dielectric layer of the interconnect layer and the p-type oxide semiconductor channel layer.

[0114] In some embodiments, the p-type oxide semiconductor channel layer is on top of the first interface layer, and the second interface layer is on top of the p-type oxide semiconductor channel layer. In some embodiments, the p-type oxide semiconductor channel layer is on top of the second interface layer, and the first interface layer is on top of the p-type oxide semiconductor channel layer. In some embodiments, the back-end transistor structure further includes a plurality of source / drain electrodes physically contacting the top of the p-type oxide semiconductor channel layer, wherein at least one of the first interface layer or the second interface layer is in physical contact with the plurality of source / drain electrodes. In some embodiments, the lattice constant of the crystal structure of the first interface layer is greater than or approximately equal to the lattice constant of the crystal structure of the p-type oxide semiconductor channel layer. In some embodiments, the p-type oxide semiconductor channel layer comprises tin oxide. In some embodiments, the metal oxide material of the first interface layer comprises two or more of the following oxides: calcium, magnesium, yttrium, lithium, lanthanum, strontium, or barium.

[0115] As described in more detail above, some embodiments described herein provide a method. The method includes forming an interface layer for a back-end transistor structure. The method includes forming a p-type oxide semiconductor channel layer of the back-end transistor structure on the interface layer, wherein forming the p-type oxide semiconductor channel layer on the interface layer results in the lattice structure of the p-type oxide semiconductor channel layer conforming to the lattice structure of the interface layer.

[0116] In some embodiments, the lattice constant of the p-type oxide semiconductor channel layer, which conforms to the lattice structure of the interface layer, promotes the growth of the (110) crystal phase in the lattice structure of the p-type oxide semiconductor channel layer. In some embodiments, forming the interface layer includes forming the interface layer on a high-dielectric-constant gate dielectric layer of the back-end transistor structure. In some embodiments, forming the interface layer includes forming the interface layer on a back-end dielectric layer in an interconnect layer of a semiconductor device. In some embodiments, the method further includes forming another interface layer on the p-type oxide semiconductor channel layer. In some embodiments, the method further includes forming a high-dielectric-constant gate dielectric layer of the back-end transistor structure on the interface layer; and forming a gate electrode of the back-end transistor structure on the high-dielectric-constant gate dielectric layer.

[0117] The terms “approximately” and “substantially” can indicate that the value of a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A transistor structure, characterized in that, include: Gate electrode; p-type oxide semiconductor channel layer, wherein the main crystal phase of the crystal structure of the p-type oxide semiconductor channel layer is composed of (110) crystal phase; as well as A gate dielectric layer is located between the gate electrode and the p-type oxide semiconductor channel layer.

2. The transistor structure according to claim 1, characterized in that, Also includes: An interface layer is provided between the gate dielectric layer and the p-type oxide semiconductor channel layer, wherein the interface layer comprises a metal oxide material.

3. The transistor structure according to claim 2, characterized in that, The metal oxide material of the interface layer has a greater Gibbs free energy change than the material of the gate dielectric layer.

4. The transistor structure according to claim 2, characterized in that, The gate electrode is located below the p-type oxide semiconductor channel layer in the transistor structure, and the p-type oxide semiconductor channel layer is located on the top surface of the interface layer.

5. The transistor structure according to claim 2, characterized in that, The gate electrode is located above the p-type oxide semiconductor channel layer in the transistor structure, and the interface layer is located on the top surface of the p-type oxide semiconductor channel layer.

6. A semiconductor device, characterized in that, include: An interconnect layer, situated on the substrate of the semiconductor device, includes: Multiple dielectric layers; and Multiple conductive structures, within the multiple dielectric layers; and The back-end transistor structure, in the dielectric layers of the plurality of dielectric layers of the interconnect layer, wherein the back-end transistor structure includes: Gate electrode; p-type oxide semiconductor channel layer, wherein at least a portion of the lattice structure of the p-type oxide semiconductor channel layer is composed of a (110) crystal phase; A gate dielectric layer is located between the gate electrode and the p-type oxide semiconductor channel layer; A first interface layer is located between the gate dielectric layer and the p-type oxide semiconductor channel layer; and The second interface layer is located between the dielectric layer of the interconnect layer and the p-type oxide semiconductor channel layer.

7. The semiconductor device according to claim 6, characterized in that, The p-type oxide semiconductor channel layer is on top of the first interface layer, and the second interface layer is on top of the p-type oxide semiconductor channel layer.

8. The semiconductor device according to claim 6, characterized in that, The p-type oxide semiconductor channel layer is located on top of the second interface layer, and the first interface layer is located on top of the p-type oxide semiconductor channel layer.

9. The semiconductor device according to claim 8, characterized in that, The back-end transistor structure further includes: Multiple source / drain electrodes are physically in contact with the top of the p-type oxide semiconductor channel layer, wherein at least one of the first interface layer or the second interface layer is physically in contact with the multiple source / drain electrodes.

10. The semiconductor device according to claim 6, characterized in that, The lattice constant of the crystal structure of the first interface layer is greater than or equal to the lattice constant of the crystal structure of the p-type oxide semiconductor channel layer.

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