Test structure and test device for gate-controlled transistor

Abstract

The utility model provides a test structure and a test device for a gate-controlled transistor. The test structure comprises a substrate; the epitaxial layer is located on one side of the substrate, and the doping type of the epitaxial layer is the same as that of the substrate; the first injection region is located in the epitaxial layer, and the doping type of the first injection region is different from that of the epitaxial layer; the gate structure is at least located on the partial surface, away from the substrate, of the first injection region; the second injection region is located in the first injection region, and the doping type of the second injection region is the same as that of the first injection region; the first electrode is at least located on the partial surface, away from the substrate, of the second injection region, and in the preset direction, the first electrode is located on one side of the gate structure and does not make contact with the gate structure; the second electrode is located on the surface, away from the epitaxial layer, of the substrate. The problem that in the prior art, a testing structure for multi-parameter testing of the grid-control transistor occupies a large wafer area is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a test structure and a test device for gate-controlled transistors. Background Technology

[0002] With the rapid development of the semiconductor industry and high-performance computers, TCAD (Technology Computer Aided Design) technology has become an indispensable tool in fields such as semiconductor process analysis, device optimization design, and device reliability analysis, in order to shorten design cycles and reduce experimental costs. In numerical analysis, the physical model of the semiconductor device and its model parameters are the link between device simulation and the actual device. Simulation software must use correct physical models and material parameters to accurately and reliably reflect the real electrical behavior of the actual device.

[0003] Currently, due to the limitations of silicon's physical theoretical limits, silicon-based devices can no longer meet the performance improvement requirements of power electronic devices and systems. Silicon carbide, with its excellent physical and electrical properties, has become an ideal semiconductor material for manufacturing power electronic devices used in extreme environments such as high temperature and high pressure. Due to the high cost and processing difficulty of silicon carbide, device simulation technology is widely used in the optimization design of silicon carbide power electronic devices. However, due to problems such as numerous material defects and poor oxide layer interface characteristics, the physical simulation model of silicon carbide is still imperfect, seriously affecting the simulation accuracy of silicon carbide gate transistors. Therefore, special test structures are needed to extract characteristic parameters and calibrate model parameters. A single test structure can usually only obtain parameters or variables closely related to it, ignoring the relationships and influences between different parameters. To achieve the extraction of multiple parameters, different types and functions of test structures need to be designed, which occupies a large wafer area, and each test structure needs to undergo separate electrical testing.

[0004] Therefore, obtaining the correlation between multiple parameters, reducing the area occupied by the test structure, and improving test efficiency are problems that need to be solved by those skilled in the art. Utility Model Content

[0005] The main objective of this application is to provide a test structure and a test device for gate-controlled transistors, in order to solve the problem that the test structure used for multi-parameter testing of gate-controlled transistors in the prior art occupies a large wafer area.

[0006] To achieve the above objectives, according to one aspect of this application, a test structure for a gate-controlled transistor is provided. The test structure includes: a substrate; an epitaxial layer located on one side of the substrate, the doping type of the epitaxial layer being the same as the doping type of the substrate; a first implantation region located in the epitaxial layer, the surface of the first implantation region away from the substrate being a portion of the surface of the epitaxial layer away from the substrate, the doping type of the first implantation region being different from the doping type of the epitaxial layer; a gate structure located at least on the portion of the surface of the first implantation region away from the substrate; a second implantation region located in the first implantation region, the surface of the second implantation region away from the substrate being a portion of the surface of the first implantation region away from the substrate, the doping type of the second implantation region being the same as the doping type of the first implantation region; a first electrode located at least on the portion of the surface of the second implantation region away from the substrate, wherein the first electrode is located on one side of the gate structure in a predetermined direction and the first electrode is not in contact with the gate structure, the predetermined direction being a direction perpendicular to the thickness of the substrate; and a second electrode located on the surface of the substrate away from the epitaxial layer.

[0007] Optionally, the test structure further includes: a third implantation region located in the first implantation region, situated on one side of the second implantation region in the predetermined direction, in contact with the second implantation region, the surface of the third implantation region away from the substrate being a portion of the surface of the first implantation region away from the substrate, and the doping type of the third implantation region being different from that of the second implantation region; a fourth implantation region located in the first implantation region, situated on the side of the third implantation region away from the second implantation region in the predetermined direction, not in contact with the third implantation region, the surface of the fourth implantation region away from the substrate being a portion of the surface of the first implantation region away from the substrate, and the doping type of the fourth implantation region being the same as that of the third implantation region; the gate structure situated on the portion of the first implantation region away from the substrate, the portion of the second implantation region away from the substrate, and the portion of the fourth implantation region away from the substrate; the first electrode situated on the portion of the second implantation region away from the substrate and the portion of the third implantation region away from the substrate; and a third electrode situated on the portion of the fourth implantation region away from the substrate, situated on the side of the gate structure away from the first electrode in the predetermined direction, and the gate structure not in contact with the third electrode.

[0008] Optionally, in the test structure, there are two of each of the second injection region, the third injection region, the gate structure, and the first electrode. In the predetermined direction, the two third injection regions are located on both sides of the fourth injection region, the two second injection regions are located on both sides of the fourth injection region, the two gate structures are located on both sides of the third electrode, and the two first electrodes are located on both sides of the third electrode. There are multiple test structures, which are arranged in the predetermined direction, and the distance between the third injection region and the fourth injection region in the test structure gradually increases in the predetermined direction.

[0009] Optionally, the gate structure includes: a gate dielectric layer located on a portion of the first implantation region away from the substrate, a portion of the second implantation region away from the substrate, and a portion of the fourth implantation region away from the substrate; and a gate located on the surface of the gate dielectric layer away from the substrate.

[0010] Optionally, the doping concentration of the epitaxial layer is less than the doping concentration of the third implantation region, and the doping concentration of the epitaxial layer is less than the doping concentration of the fourth implantation region.

[0011] Optionally, the doping concentration of the second implantation region is greater than the doping concentration of the first implantation region.

[0012] Optionally, the doping concentration of the epitaxial layer is 1E14cm. -3 ~5E16cm -3 The doping concentration of both the third and fourth implantation regions is 1E19cm. -3 ~1E21cm -3 .

[0013] Optionally, the doping concentration of the first implantation region is 1E17cm. -3 ~5E18cm -3 The doping concentration of the second implantation region is 1E19cm⁻¹. -3 ~1E21cm -3 .

[0014] Optionally, the substrate is made of silicon carbide.

[0015] According to another aspect of this application, a test device for a gate-controlled transistor is provided, comprising any of the test structures for gate-controlled transistors described herein.

[0016] The test structure for a gate-controlled transistor using the technical solution of this application includes a substrate, an epitaxial layer located on one side of the substrate, a first implantation region located in the epitaxial layer, a second implantation region located in the first implantation region, a gate structure, a first electrode, and a second electrode. The gate structure is located on a portion of the surface of the first implantation region that is away from the substrate, the first electrode is located on at least a portion of the surface of the second implantation region that is away from the substrate, and the second electrode is located on a surface of the substrate that is away from the epitaxial layer. The doping type of the epitaxial layer is the same as the doping type of the substrate, the doping type of the first implantation region is different from the doping type of the epitaxial layer, and the doping type of the second implantation region is the same as the doping type of the first implantation region. Compared with the existing technology where the test structure for multi-parameter testing of gate-controlled transistors occupies a large wafer area, the test structure of this application includes a substrate, an epitaxial layer located on one side of the substrate, a first injection region located in the epitaxial layer, a second injection region located in the first injection region, a gate structure, a first electrode, and a second electrode. The gate structure, the first injection region, the first electrode, and the second injection region constitute a lateral MOS (Metal-Oxide-Semiconductor) capacitor structure. This lateral MOS capacitor structure can be used to measure the interface states and fixed charges of the gate-controlled transistor. The first electrode, the second injection region, the epitaxial layer, the substrate, and the second electrode constitute a PiN (P-type-intrinsic-N-type) structure. This PiN structure can be used to extract the composite model parameters of the gate-controlled transistor. The test structure of this application can simultaneously measure multiple parameters, ensuring a small wafer area occupied by the test structure and high testing efficiency for the gate-controlled transistor. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A cross-sectional schematic diagram of a test structure for a gate-controlled transistor provided according to an embodiment of this application is shown;

[0019] Figure 2 An embodiment of this application is shown, which provides a method for... Figure 1 A top-view diagram of the corresponding test structure.

[0020] The above figures include the following reference numerals:

[0021] 10. Substrate; 11. Epitaxial layer; 12. First implantation region; 13. Gate structure; 14. Second implantation region; 15. First electrode; 16. Second electrode; 17. Third implantation region; 18. Fourth implantation region; 19. Third electrode; 131. Gate dielectric layer; 132. Gate. Detailed Implementation

[0022] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0025] As described in the background section, the existing test structures for multi-parameter testing of gate-controlled transistors occupy a large wafer area. To address the above problem, embodiments of this application provide a test structure for gate-controlled transistors and a test device for gate-controlled transistors.

[0026] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0027] This application provides a test structure for gate-controlled transistors, such as... Figure 1 and Figure 2 As shown, the test structure includes:

[0028] Substrate 10;

[0029] Epitaxial layer 11 is located on one side of the substrate 10, and the doping type of the epitaxial layer 11 is the same as that of the substrate 10.

[0030] The first implantation region 12 is located in the epitaxial layer 11. The surface of the first implantation region 12 that is away from the substrate 10 is a portion of the surface of the epitaxial layer 11 that is away from the substrate 10. The doping type of the first implantation region 12 is different from the doping type of the epitaxial layer 11.

[0031] The gate structure 13 is located at least on the surface of the first implantation region 12 that is away from the substrate 10.

[0032] The second implantation region 14 is located in the first implantation region 12. The surface of the second implantation region 14 that is away from the substrate 10 is the part of the surface of the first implantation region 12 that is away from the substrate 10. The doping type of the second implantation region 14 is the same as that of the first implantation region 12.

[0033] The first electrode 15 is located at least on the surface of the second injection region 14 away from the substrate 10. In a predetermined direction, the first electrode 15 is located on one side of the gate structure 13 and does not contact the gate structure 13. The predetermined direction is a direction perpendicular to the thickness of the substrate 10.

[0034] The second electrode 16 is located on the surface of the substrate 10 that is away from the epitaxial layer 11.

[0035] According to the above embodiments, the test structure for the gate-controlled transistor includes a substrate, an epitaxial layer located on one side of the substrate, a first implantation region located in the epitaxial layer, a second implantation region located in the first implantation region, a gate structure, a first electrode, and a second electrode. The gate structure is located on a portion of the surface of the first implantation region that is away from the substrate, the first electrode is located on at least a portion of the surface of the second implantation region that is away from the substrate, and the second electrode is located on a surface of the substrate that is away from the epitaxial layer. The doping type of the epitaxial layer is the same as the doping type of the substrate, the doping type of the first implantation region is different from the doping type of the epitaxial layer, and the doping type of the second implantation region is the same as the doping type of the first implantation region. Compared with the existing technology where the test structure for multi-parameter testing of gate-controlled transistors occupies a large wafer area, the test structure of this application includes a substrate, an epitaxial layer located on one side of the substrate, a first injection region located in the epitaxial layer, a second injection region located in the first injection region, a gate structure, a first electrode, and a second electrode. The gate structure, the first injection region, the first electrode, and the second injection region constitute a lateral MOS capacitor structure, which can be used to measure the interface states and fixed charges of the gate-controlled transistor. The first electrode, the second injection region, the epitaxial layer, the substrate, and the second electrode constitute a PiN structure, which can be used to extract the composite model parameters of the gate-controlled transistor. The test structure of this application can simultaneously measure multiple parameters, ensuring a small wafer area occupied by the test structure and high testing efficiency for the gate-controlled transistor.

[0036] In addition, existing single test structures can usually only obtain parameters or variables that are closely related to them, ignoring the relationships and influences between different parameters. However, the test structure of this application can simultaneously measure interface states, fixed charges, and composite model parameters, that is, it takes into account the relationships and influences between different parameters, ensuring that the test results are more accurate.

[0037] Specifically, the test structure in this application is used to test multiple parameters of the gate-controlled transistor, and the gate-controlled transistor and the test structure of this application are integrated on a single wafer.

[0038] Specifically, in the lateral MOS capacitor structure formed by the test structure of this application, the gate structure and the first injection region serve as one of the plates of the lateral MOS capacitor structure, and the first electrode and the second injection region serve as the other plate of the lateral MOS capacitor structure.

[0039] Specifically, in the PiN structure constituted by the test structure of this application, the first electrode and the second injection region are the P-region (or N-region) of the PiN structure, the epitaxial layer is the i-region of the PiN structure, and the substrate and the second electrode are the N-region (or P-region) of the PiN structure. Specifically, recombination model parameters refer to parameters related to the recombination process of charge carriers (electrons and holes) in a gate-controlled transistor, used to describe the characteristics of the recombination process. Recombination model parameters include, but are not limited to, recombination rate, carrier lifetime, surface recombination rate, and bulk recombination coefficient.

[0040] In one alternative, such as Figure 1 and Figure 2As shown, the above test structure further includes: a third implantation region 17, located within the first implantation region 12, situated on one side of the second implantation region 14 in the predetermined direction, in contact with the second implantation region 14, the surface of the third implantation region 17 away from the substrate 10 being a portion of the surface of the first implantation region 12 away from the substrate 10, and the doping type of the third implantation region 17 being different from the doping type of the second implantation region 14; and a fourth implantation region 18, located within the first implantation region 12, situated on the side of the third implantation region 17 away from the second implantation region 14 in the predetermined direction, not in contact with the third implantation region 17, and the surface of the fourth implantation region 18 away from the substrate 10 being a portion of the surface of the first implantation region 12 away from the substrate 10. The doping type of the fourth implantation region 18 is the same as that of the third implantation region 17 on a portion of the surface away from the substrate 10. The gate structure 13 is located on a portion of the surface away from the substrate 10 of the first implantation region 12, a portion of the surface away from the substrate 10 of the second implantation region 14, and a portion of the surface away from the substrate 10 of the fourth implantation region 18. The first electrode 15 is located on a portion of the surface away from the substrate 10 of the second implantation region 14 and a portion of the surface away from the substrate 10 of the third implantation region 17. The third electrode 19 is located on a portion of the surface away from the substrate 10 of the fourth implantation region 18. In the predetermined direction, the third electrode 19 is located on the side of the gate structure 13 away from the first electrode 15. The gate structure 13 and the third electrode 19 are not in contact. In this embodiment, the test structure further includes a third injection region and a fourth injection region located in the first injection region, and a third electrode located on the surface of the fourth injection region away from the substrate. The gate structure, the first electrode, the second injection region, the third injection region, the third electrode, and the fourth injection region constitute a lateral MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure. The lateral MOSFET structure can be used to measure the channel mobility of the gate-controlled transistor, further ensuring that the test structure can measure multiple parameters simultaneously, further ensuring that the test structure occupies a small wafer area, and further ensuring that the test efficiency of the gate-controlled transistor is high.

[0041] Specifically, in the lateral MOSFET structure formed by the test structure of this application, the gate structure serves as the gate portion of the lateral MOSFET structure, the first electrode, the second injection region, and the third injection region serve as the source portion (or drain region) of the lateral MOSFET structure, and the third electrode and the fourth injection region serve as the drain portion of the lateral MOSFET structure.

[0042] In other embodiments, such as Figure 1 and Figure 2 As shown, in the above test structure, there are two of each of the second injection region 14, the third injection region 17, the gate structure 13, and the first electrode 15. In the predetermined direction, the two third injection regions 17 are located on both sides of the fourth injection region 18, the two second injection regions 14 are located on both sides of the fourth injection region 18, the two gate structures 13 are located on both sides of the third electrode 19, and the two first electrodes 15 are located on both sides of the third electrode 19. There are multiple test structures, and the multiple test structures are arranged in the predetermined direction. In the predetermined direction, the distance between the third injection region 17 and the fourth injection region 18 in the test structure gradually increases (not shown). In this embodiment, the test structure is set as a ring structure, and there are multiple test structures. The multiple test structures are arranged in a predetermined direction. In the predetermined direction, the distance between the third injection region and the fourth injection region in the test structure gradually increases. The multiple test structures form a circular transmission line model. The contact resistivity of the gate-controlled transistor can be extracted using the circular transmission line model. This further ensures that the test structure can measure multiple parameters at the same time, further ensures that the wafer area occupied by the test structure is small, and further ensures that the test efficiency of the gate-controlled transistor is high.

[0043] Specifically, multiple test structures arranged in a predetermined direction form a test structure group, and the spacing between the third injection region and the fourth injection region in each test structure is different.

[0044] It should be noted that in the circular transmission line model composed of multiple test structures in this application, the first electrode, second injection region, third injection region, second electrode and fourth injection region in each test structure constitute the circular transmission line model.

[0045] Specifically, such as Figure 1 As shown, d represents the distance between the third injection region 17 and the fourth injection region 18 in the predetermined direction.

[0046] According to some exemplary embodiments of this application, such as Figure 1 and Figure 2As shown, the gate structure 13 includes: a gate dielectric layer 131 located on the portion of the first injection region 12 away from the substrate 10, the portion of the second injection region 14 away from the substrate 10, and the portion of the fourth injection region 18 away from the substrate 10; and a gate 132 located on the surface of the gate dielectric layer 131 away from the substrate 10. In this embodiment, the gate dielectric layer serves as an electrical isolation layer, ensuring good insulation between the gate and the injection region below, preventing current from flowing directly from the gate to the injection region, thereby ensuring the normal operation of the gate-controlled transistor. Furthermore, this gate structure design allows for the testing of multiple parameters of the gate-controlled transistor (such as interface states, fixed charge, channel mobility, etc.), further improving the efficiency and accuracy of the testing.

[0047] In some alternative embodiments of this application, the doping concentration of the epitaxial layer is lower than the doping concentration of the third injection region, and the doping concentration of the epitaxial layer is lower than the doping concentration of the fourth injection region. In this embodiment, by controlling the doping concentration of the epitaxial layer to be lower than that of the fourth injection region compared to the third injection region, the injection and collection efficiency of charge carriers can be optimized, thereby further improving the performance of the gate-controlled transistor.

[0048] In some alternative embodiments of this application, the doping concentration of the second implantation region is greater than that of the first implantation region. In this embodiment, by increasing the doping concentration of the second implantation region, the doping uniformity of the entire implantation region can be improved, which helps to reduce device performance fluctuations caused by doping inhomogeneity.

[0049] In some alternative embodiments of this application, the doping concentration of the epitaxial layer is 1E14cm. -3 ~5E16cm -3 The doping concentration of both the third and fourth implantation regions is 1E19cm. -3 ~1E21cm -3 .

[0050] In other embodiments, the doping concentration of the first implantation region is 1E17cm. -3 ~5E18cm -3 The doping concentration of the second implantation region is 1E19cm. -3 ~1E21cm -3 .

[0051] In other embodiments, the substrate is made of silicon carbide.

[0052] This application also provides a test device for gate-controlled transistors, including any of the above-described test structures for gate-controlled transistors.

[0053] In the above embodiments, the test device includes a test structure, wherein the test structure includes a substrate, an epitaxial layer located on one side of the substrate, a first implantation region located in the epitaxial layer, a second implantation region located in the first implantation region, a gate structure, a first electrode, and a second electrode, wherein the gate structure is located on a portion of the first implantation region away from the substrate, the first electrode is located at least on a portion of the second implantation region away from the substrate, and the second electrode is located on a surface of the substrate away from the epitaxial layer. The doping type of the epitaxial layer is the same as the doping type of the substrate, the doping type of the first implantation region is different from the doping type of the epitaxial layer, and the doping type of the second implantation region is the same as the doping type of the first implantation region. Compared with the existing technology where the test structure for multi-parameter testing of gate-controlled transistors occupies a large wafer area, the test structure of this application includes a substrate, an epitaxial layer located on one side of the substrate, a first injection region located in the epitaxial layer, a second injection region located in the first injection region, a gate structure, a first electrode, and a second electrode. The gate structure, the first injection region, the first electrode, and the second injection region constitute a lateral MOS capacitor structure, which can be used to measure the interface states and fixed charges of the gate-controlled transistor. The first electrode, the second injection region, the epitaxial layer, the substrate, and the second electrode constitute a PiN structure, which can be used to extract the composite model parameters of the gate-controlled transistor. The test structure of this application can simultaneously measure multiple parameters, ensuring a small wafer area occupied by the test structure and high testing efficiency for the gate-controlled transistor.

[0054] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0055] The test structure for gate-controlled transistors in this application includes a substrate, an epitaxial layer located on one side of the substrate, a first implantation region located in the epitaxial layer, a second implantation region located in the first implantation region, a gate structure, a first electrode, and a second electrode. The gate structure is located on a portion of the surface of the first implantation region that is away from the substrate, the first electrode is located on at least a portion of the surface of the second implantation region that is away from the substrate, and the second electrode is located on a surface of the substrate that is away from the epitaxial layer. The doping type of the epitaxial layer is the same as the doping type of the substrate, the doping type of the first implantation region is different from the doping type of the epitaxial layer, and the doping type of the second implantation region is the same as the doping type of the first implantation region. Compared with the existing technology where the test structure for multi-parameter testing of gate-controlled transistors occupies a large wafer area, the test structure of this application includes a substrate, an epitaxial layer located on one side of the substrate, a first injection region located in the epitaxial layer, a second injection region located in the first injection region, a gate structure, a first electrode, and a second electrode. The gate structure, the first injection region, the first electrode, and the second injection region constitute a lateral MOS capacitor structure, which can be used to measure the interface states and fixed charges of the gate-controlled transistor. The first electrode, the second injection region, the epitaxial layer, the substrate, and the second electrode constitute a PiN structure, which can be used to extract the composite model parameters of the gate-controlled transistor. The test structure of this application can simultaneously measure multiple parameters, ensuring a small wafer area occupied by the test structure and high testing efficiency for the gate-controlled transistor.

[0056] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A test structure for gate-controlled transistors, characterized in that, The test structure includes: Substrate; An epitaxial layer is located on one side of the substrate, and the doping type of the epitaxial layer is the same as that of the substrate; A first implantation region is located in the epitaxial layer. The surface of the first implantation region away from the substrate is a portion of the surface of the epitaxial layer away from the substrate. The doping type of the first implantation region is different from the doping type of the epitaxial layer. A gate structure is located at least on the surface of the first implantation region away from the substrate; The second implantation region is located within the first implantation region. The surface of the second implantation region that is away from the substrate is a portion of the surface of the first implantation region that is away from the substrate. The doping type of the second implantation region is the same as that of the first implantation region. A first electrode is located at least on the surface of the second injection region away from the substrate. In a predetermined direction, the first electrode is located on one side of the gate structure and does not contact the gate structure. The predetermined direction is a direction perpendicular to the thickness of the substrate. The second electrode is located on the surface of the substrate away from the epitaxial layer.

2. The test structure for gate-controlled transistors according to claim 1, characterized in that, The test structure also includes: A third implantation region is located within the first implantation region. In the predetermined direction, the third implantation region is located on one side of the second implantation region. The third implantation region is in contact with the second implantation region. The surface of the third implantation region away from the substrate is a portion of the surface of the first implantation region away from the substrate. The doping type of the third implantation region is different from that of the second implantation region. A fourth implantation region is located within the first implantation region. In the predetermined direction, the fourth implantation region is located on the side of the third implantation region away from the second implantation region. The fourth implantation region is not in contact with the third implantation region. The surface of the fourth implantation region away from the substrate is a portion of the surface of the first implantation region away from the substrate. The doping type of the fourth implantation region is the same as that of the third implantation region. The gate structure is located on the portion of the first implantation region away from the substrate, the portion of the second implantation region away from the substrate, and the portion of the fourth implantation region away from the substrate. The first electrode is located on the portion of the second implantation region away from the substrate and the portion of the third implantation region away from the substrate. The third electrode is located on a portion of the surface of the fourth injection region away from the substrate. In the predetermined direction, the third electrode is located on the side of the gate structure away from the first electrode, and the gate structure is not in contact with the third electrode.

3. The test structure for gate-controlled transistors according to claim 2, characterized in that, In the test structure, there are two of each of the second injection region, the third injection region, the gate structure, and the first electrode. In the predetermined direction, the two third injection regions are located on both sides of the fourth injection region, the two second injection regions are located on both sides of the fourth injection region, the two gate structures are located on both sides of the third electrode, and the two first electrodes are located on both sides of the third electrode. There are multiple test structures, which are arranged in a predetermined direction, and the distance between the third injection region and the fourth injection region in the test structure gradually increases in the predetermined direction.

4. The test structure for gate-controlled transistors according to claim 2, characterized in that, The gate structure includes: A gate dielectric layer is located on the portion of the first implantation region that is away from the substrate, the portion of the second implantation region that is away from the substrate, and the portion of the fourth implantation region that is away from the substrate; The gate is located on the surface of the gate dielectric layer away from the substrate.

5. The test structure for gate-controlled transistors according to claim 2, characterized in that, The doping concentration of the epitaxial layer is less than that of the third implantation region, and the doping concentration of the epitaxial layer is less than that of the fourth implantation region.

6. The test structure for gate-controlled transistors according to claim 1, characterized in that, The doping concentration of the second implantation region is greater than that of the first implantation region.

7. The test structure for gate-controlled transistors according to claim 5, characterized in that, The doping concentration of the epitaxial layer is 1E14cm. -3 ~5E16cm -3 The doping concentration of both the third and fourth implantation regions is 1E19cm. -3 ~1E21cm -3 .

8. The test structure for gate-controlled transistors according to claim 6, characterized in that, The doping concentration of the first implantation region is 1E17cm. -3 ~5E18cm -3 The doping concentration of the second implantation region is 1E19cm⁻¹. -3 ~1E21cm -3 .

9. The test structure for gate-controlled transistors according to claim 1, characterized in that, The substrate is made of silicon carbide.

10. A test device for gate-controlled transistors, characterized in that, The test structure for gate-controlled transistors includes any one of claims 1 to 9.

Images