Semiconductor device

Abstract

Various embodiments of the present disclosure relate to a semiconductor device including a device substrate having a front side surface opposite a back side surface. An upper dielectric layer is disposed over the backside surface. A through substrate via (TSV) extends through the device substrate from the upper dielectric layer. The dummy vias are laterally offset from the TSVs. A top surface of the dummy via and a top surface of the TSV are coplanar, and a bottom surface of the dummy via is separated from the front side surface through the device substrate.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of through-hole structure of multilayer stacked wafer. BACKGROUND

[0002] Many modern electronic devices (e.g., smartphones, digital cameras, biomedical imaging devices, automotive imaging devices, etc.) include semiconductor devices having multiple layers of stacked wafers. Wafers bonded to each other improve the functionality and performance of semiconductor devices (e.g., image sensors, memories, microprocessors, etc.). Multiple layers of stacked wafers enable three-dimensional integration of devices, resulting in compact device footprints. SUMMARY

[0003] According to an embodiment of the utility model, a semiconductor device includes a device substrate, an upper dielectric layer, a through substrate via (TSV), and a dummy via. The device substrate has a front side surface opposite a back side surface. The upper dielectric layer is above the back side surface. The TSV extends from the upper dielectric layer through the device substrate. The dummy via is laterally offset from the TSV, where a top surface of the dummy via and a top surface of the TSV are substantially coplanar, and a bottom surface of the dummy via is separated from the front side surface by the device substrate.

[0004] According to another embodiment of the utility model, a semiconductor device includes an imaging wafer, a logic wafer, and a device substrate. The device substrate is disposed between the logic wafer and the imaging wafer, and the device substrate has a front side surface opposite a back side surface, where the device substrate has a peripheral region laterally separated from a device region. The semiconductor device also includes an upper dielectric layer above the back side surface, a wire disposed below the front side surface and within the peripheral region, a through substrate via (TSV) disposed within the device substrate, the TSV extending from the upper dielectric to the wire, a dummy via disposed within the device region and extending from a bottom surface of the upper dielectric layer toward the device substrate. The dummy via is separated from the front side surface of the device substrate. BRIEF DESCRIPTION OF DRAWINGS

[0005] The present disclosure can best be understood when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity. Included in the description are drawings of certain embodiments and depicting representative shapes and relative spatial relationships.

[0006] Figure 1 Cross-sectional views of some embodiments of a semiconductor device including an active through substrate via (TSV) and a dummy via are shown.

[0007] Figure 2Cross-sectional views of some embodiments of a stacked image sensor with an imaging chip, a device chip, and a logic chip are shown.

[0008] Figure 3 Top views of some embodiments of a stacked image sensor are shown. Figure 2 Figure 2 Cross-sectional views of some embodiments of a stacked image sensor are shown.

[0009] Figure 4 , Figure 5 and Figure 6 Cross-sectional views of some embodiments of a device chip including active TSVs and dummy vias are shown.

[0010] Figure 7 Cross-sectional views of some embodiments of a stacked image sensor with active TSVs and dummy vias are shown.

[0011] Figure 8 Cross-sectional views of some embodiments of a stacked image sensor corresponding to some other embodiments of a stacked image sensor are shown. Figure 2 and Figure 7 Cross-sectional views of some embodiments of a stacked image sensor corresponding to some other embodiments of a stacked image sensor are shown.

[0012] Figures 9-18 Various views of some embodiments of a method of forming a stacked image sensor including dummy vias in a device region and active TSVs in a peripheral region are shown.

[0013] Figures 19-22 Various cross-sectional views of some other embodiments of a method of forming a stacked image sensor with active TSVs and dummy vias are shown.

[0014] Figure 23 Flowcharts according to some embodiments of a method for forming a stacked image sensor including active TSVs within a peripheral region of a device chip and dummy vias within a device region are shown. DETAILED DESCRIPTION

[0015] ​The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the present application. Specific examples of components and configurations are described herein to facilitate discussion of the present application. The components and configurations are simply examples and are not intended to be limiting. For example, in the following description, the formation of a first component over or on a second component can include embodiments in which the first component is formed directly on the second component, and can also include embodiments in which additional components can be formed between the first component and the second component such that the first component is not formed directly on the second component. Additionally, the present disclosure can repeat certain elements or / and use certain terms in various examples. This repetition and / or these terms are not to be construed as a limitation on the specific embodiments or / and examples, but are intended to be common to the various embodiments and / or examples described herein.

[0016] The semiconductor devices can be multi-stacked chips in which a single semiconductor die (or chip) is singulated from a wafer. The dies of the semiconductor devices can include integrated circuits (ICs) that provide various functions and capabilities for the semiconductor devices. After the dies are fabricated and singulated, they can be bonded to each other and vertically stacked / interconnected through through substrate vias (TSVs) or through silicon vias. The multi-stacked chips provide compact and high performance semiconductor devices that incorporate the functions of multiple dies. Semiconductor devices that can benefit from multi-stacked chips include memory devices, image sensors, microprocessors, field programmable gate arrays, radio frequency devices, power elements, light emitting diode devices, etc.

[0017] For example, a stacked image sensor can include vertically stacked imaging dies, device dies, and logic dies, where the device dies are bonded to the imaging dies and the logic dies are bonded to the device dies. The imaging dies can include a plurality of pixel sensors having photodetectors. The device dies can include pixel devices having reset transistors, source follower transistors, selection transistors, etc., that are configured to perform readout of accumulated charge from the photodetectors. The logic dies can include a plurality of logic elements that can include transistors, logic gates, or other elements configured as application specific integrated circuits (ASICs) that can facilitate downstream signal processing of the charge accumulated by the photodetectors read out by the device dies.

[0018] The stacked image sensor can have a device region (e.g., a middle region of the image sensor) aligned with the plurality of pixel sensors and photodetectors, and a peripheral region surrounding the image sensor at a periphery of the plurality of pixel sensors. TSVs are disposed within the peripheral region and are configured to electrically couple the logic dies to the device dies. For example, a bonding structure having bond pads can connect the device dies to the logic dies, and the TSVs can provide electrical connections from the device dies to the logic dies through the bond pads.

[0019] Due to stress at the center of the wafer, devices with multi-layer stacked wafers can experience delamination between wafers. For example, while TSVs can provide structural support in the peripheral region of an image sensor, the logic wafer and device wafer can experience deformation or delamination in the device region, where either the substrate layer of the device wafer deforms due to stress or the dielectric film between the logic wafer and the device wafer delaminates.

[0020] Various aspects of the present disclosure relate to a via structure for a multi-layer stacked wafer including dummy vias. The dummy vias are disposed within a device region of a semiconductor device to provide structural support to avoid inter-wafer or inter-layer deformation or delamination. For example, a device wafer can include a device substrate and an upper dielectric layer disposed above the device substrate. The device substrate has a front side surface opposite a backside surface. Active TSVs in a peripheral region are disposed within the device substrate, extending from the upper dielectric layer and through the device substrate. Dummy vias within the device region are laterally offset from the active TSVs and extend from the upper dielectric layer toward the device substrate, where the dummy vias are separated from the front side surface of the device substrate. Top surfaces of the active TSVs and the dummy vias are substantially co-planar, and the active TSVs have a first height that is greater than a second height of the dummy vias. Further, the active TSVs are connected to active elements (e.g., transistors), and the dummy vias are electrically isolated from the active elements.

[0021] By adding one or more dummy vias within the device region of the device wafer, structural support between the logic wafer and the device wafer is achieved without adding vias within the device region of the device substrate. Thus, crosstalk within the device substrate is minimized by avoiding excess vias within the device substrate, space for active elements is maintained within the device region by avoiding TSVs within the device region, and a rigid / stress absorption point is achieved within the device region. The one or more dummy vias can reduce or eliminate the risk of inter-wafer or inter-layer delamination or deformation caused by stress within the multi-layer stacked wafer, which is caused by mechanical stress including thermal expansion of the multi-layer stacked wafer.

[0022] As discussed herein, various methods of forming active TSVs and dummy vias are presented. For example, the active TSVs and dummy vias can be formed with a single photoresist mask and two etches. This process has the advantage of forming the active TSVs and dummy vias at low cost. In another example, the active TSVs and dummy vias are formed from two photoresist masks and three etches. This process has the advantage of independent and high-fidelity control of the critical dimensions of the active TSVs and dummy vias through independent etch processes.

[0023] Figure 1A cross-sectional view 100 of some embodiments of a semiconductor device including active substrate through-silicon vias (TSVs) and dummy vias is shown.

[0024] The cross-sectional view 100 shows a device wafer 134 having a device substrate 102. In some embodiments, the device wafer 134 is any wafer having interconnect structures electrically coupled to another wafer. The device substrate 102 has a front side surface 102f opposite a back side surface 102b. The device substrate 102 can be or include a semiconductor body (e.g., single crystal silicon, CMOS body, silicon-germanium, etc.) and have a first doping type (e.g., p-type). A plurality of dielectric layers 132 are disposed on the front side surface 102f of the device substrate 102. The plurality of dielectric layers 132 can include a first dielectric layer 110 disposed on the front side surface 102f, a second dielectric layer 112 disposed on the first dielectric layer 110, and a third dielectric layer 114 disposed on the second dielectric layer. In some embodiments, the first dielectric layer 110 is a barrier layer or a photoresist protective oxide, which can be or include a dielectric, a low-k dielectric, or an oxide (e.g., silicon dioxide). In some embodiments, the second dielectric layer 112 is a contact etch stop layer and can be or include a dielectric, a low-k dielectric, or a nitride (e.g., silicon nitride). In some embodiments, the third dielectric layer 114 is a dielectric fill layer and can be or include an oxide or other dielectric material.

[0025] An interlayer dielectric (ILD) layer 116 is disposed on the plurality of dielectric layers 132. In some embodiments, the ILD layer 116 can be or include a nitride, a carbide, an oxide, a low-k dielectric, etc. A metal layer 118 is disposed on the ILD layer 116. The metal layer 118 can be or include copper, tungsten, aluminum, etc. In some embodiments, the metal layer 118 includes wires or other interconnect devices disposed within a dielectric (not shown).

[0026] A dielectric film 120 is disposed on the back surface 102b of the device substrate 102. The dielectric film 120 can be or include an oxide such as silicon dioxide, a low-k dielectric material, etc. A lower dielectric layer 122 is disposed on the dielectric film 120, and an upper dielectric layer 124 is disposed above the lower dielectric layer 122. The upper dielectric layer 124 includes a plurality of wires 130. The lower dielectric layer 122 and the upper dielectric layer 124 can be or include a nitride, a carbide, an oxide, a low-k dielectric, etc.

[0027] The device wafer 134 has a peripheral region 136 laterally separated from a device region 138, where the peripheral region 136 is at a periphery of the device wafer 134 and the device region 138 is laterally surrounded by the peripheral region 136. A plurality of shallow trench isolation (STI) structures 108a, 108b are disposed within the device substrate 102 extending from the front side surface 102f in the peripheral region 136 and the device region 138. The plurality of STI structures 108a, 108b can be or include silicon dioxide, silicon nitride, silicon carbide, or the like.

[0028] The active TSV 104 is disposed within the peripheral region 136 and extends from the upper dielectric layer 124 through the lower dielectric layer 122, the dielectric film 120, the device substrate 102, the STI structure 108a of the STI structures 108a, 108b, the plurality of dielectric layers 132, and the ILD layer 116 to contact the metal layer 118. The active TSV 104 has a first height hi from a bottom surface of the upper dielectric layer 124 to a top surface of the metal layer 118. Further, one of the plurality of conductive lines 130 is disposed along a top surface of the active TSV 104. In some embodiments, the active TSV 104 can be or include one or more of copper, tungsten, aluminum, or another suitable metal.

[0029] The liner structure 140 is disposed along a top surface of the lower dielectric layer 122, separating the upper dielectric layer 124 from the lower dielectric layer 122. The liner structure 140 extends along an outer sidewall of the active TSV 104, separating the active TSV 104 from the lower dielectric layer 122, the dielectric film 120, the device substrate 102, the STI structure 108a, and the plurality of dielectric layers 132. The liner structure 140 has a top surface disposed along a bottom surface of the upper dielectric layer 124 and a bottom surface disposed along a top surface of the ILD layer 116. As such, the liner structure 140 is not disposed along a bottom portion 142 of the active TSV 104 within the ILD layer 116. Accordingly, an outer sidewall of the bottom portion 142 of the active TSV 104 disposed within the ILD layer 116 will be in contact with the ILD layer 116. In some embodiments, the liner structure 140 provides electrical isolation and a diffusion barrier between the active TSV 104 and one or more of the lower dielectric layer 122, the dielectric film 120, or the device substrate 102.

[0030] In some embodiments, the spacer structure 140 includes a first dielectric spacer 128 and a second dielectric spacer 106. In some embodiments, the first dielectric spacer 128 and the second dielectric spacer 106 include the same material. In other embodiments, the first dielectric spacer 128 and the second dielectric spacer 106 include different materials, where the first dielectric spacer 128 can be or include a nitride such as silicon nitride, a high-k dielectric including a nitride, or other nitride, and the second dielectric spacer 106 can be or include an oxide such as silicon dioxide, a high-k dielectric including an oxide, or other oxide. In some embodiments, the first dielectric spacer 128 and the second dielectric spacer 106 include different materials having different etch rates, for example, where the material of the first dielectric spacer 128 has a faster etch rate than the material of the second dielectric spacer 106. The first dielectric spacer 128 is disposed along a top surface of the lower dielectric layer 122, and the second dielectric spacer 106 is disposed on a top surface of the first dielectric spacer 128 and separates the first dielectric spacer 128 from the upper dielectric layer 124. The second dielectric spacer 106 extends from the upper dielectric layer 124 along an outer sidewall of the active TSV 104 to a top surface of the ILD layer 116 and has a second height h2 that is less than the first height hi of the active TSV 104. Further, the second dielectric spacer 106 separates the active TSV 104 from the first dielectric spacer 128.

[0031] The first dielectric spacer 128 extends from a lower surface of the second dielectric spacer 106 above the lower dielectric layer 122 to a top surface of the ILD layer 116 and has a third height h3 that is less than the first height hi of the active TSV 104 and less than the second height h2 of the second dielectric spacer 106. Further, the first dielectric spacer 128 separates the second dielectric spacer 106 from the device substrate 102.

[0032] Dummy via 126 is laterally offset from active TSV 104, where dummy via 126 is disposed within device region 138. Dummy via 126 is disposed within lower dielectric layer 122, where dummy via 126 extends from a bottom surface of upper dielectric layer 124. As such, a top surface of dummy via 126 is substantially co-planar with a top surface of active TSV 104. That is, active TSV 104 and dummy via 126 extend from a common surface defined by a bottom surface of upper dielectric layer 124. A bottom surface sl of dummy via 126 is separated from a front side surface of device substrate 102. In some embodiments, the bottom surface sl of dummy via is in contact with dielectric film 120, where the bottom surface sl of dummy via 126 is in full contact with dielectric film 120. That is, dielectric film 120 is in contact with bottom surface sl of dummy via 126 across an entire bottom surface sl of dummy via 126. In the present embodiment, bottom surface sl of dummy via 126 is disposed above backside surface 102b of device substrate 102. In some embodiments, dummy via 126 can be or include one or more of copper, tungsten, aluminum, or another suitable metal. In the present embodiment, bottom surface sl is in full contact with a dielectric, such as dielectric film 120. In other embodiments, bottom surface sl is in full contact with lower dielectric layer 122 or device substrate 102 (not shown). In some embodiments, dummy via 126 is aligned over STI structure 108b. In some embodiments, a top surface of dummy via 126 is in full contact with upper dielectric layer 124.

[0033] Dummy via 126 has a fourth height h4 from a bottom surface of upper dielectric layer 124 to bottom surface sl within dielectric film 120. Fourth height h4 is less than first height hi of active TSV 104. In some embodiments, first height hi of active TSV 104 ranges from one to two, two to three, or more than three times fourth height h4 of dummy via 126. Further, in some embodiments, a width of active TSV 104 ranges from one to two, two to three, or more than three times a width of dummy via 126.

[0034] The spacer structure 140 is disposed along the outer sidewall of the dummy via 126, separating the dummy via 126 from the lower dielectric layer 122 and separating the outer sidewall of the dummy via 126 from the dielectric film 120. The first dielectric spacer 128 is disposed between the outer sidewall of the dummy via 126 and the lower device dielectric, and separates the outer sidewall of the dummy via 126 from the dielectric film 120. The second dielectric spacer 106 is disposed along the sidewall of the dummy via 126, where the second dielectric spacer 106 is disposed along the inner sidewall of the first dielectric spacer 128 and separates the dummy via 126 from the first dielectric spacer 128. The second dielectric spacer 106 extends from the top surface of the dummy via 126 to the bottom surface s1 of the dummy via 126, and has a vertical height that is the same as the fourth height h4 of the dummy via 126. The first dielectric spacer 128 extends from the bottom surface of the second dielectric spacer 106 disposed above the lower dielectric layer 122 to the bottom surface s1 of the dummy via 126, and has a vertical height that is less than the vertical height of the second dielectric spacer 106. The spacer structure 140 provides electrical isolation and diffusion barrier between the dummy via 126 and the lower dielectric layer 122 and the dielectric film 120.

[0035] In some embodiments, a device dielectric layer 139 is disposed between the front side surface 102f of the device substrate 102 and the ILD layer 116, where the device dielectric layer 139 is vertically aligned with the plurality of dielectric layers 132. A plurality of active elements 144 is disposed on the front side surface 102f of the device substrate 102 below the dummy via 126, where a gate electrode of the plurality of active elements 144 is disposed within the device dielectric layer 139. The plurality of active elements 144 can be separated from each other by STI structures, such as the STI structure 108b. The device dielectric layer 139 can be or include nitride, carbide, oxide, low-k dielectric, etc. In some embodiments, the plurality of active elements 144 can provide configuration functions for a semiconductor device, such as a reset transistor for an image sensor.

[0036] In some embodiments, the active TSV 104 is coupled to an active element, such as one of the plurality of active elements 144 and / or an active element of another wafer (not shown). Since the dummy via 126 is electrically isolated from other active elements, such as the plurality of active elements 144 or other active elements, the bottom surface s1 of the dummy via 126 is disconnected from conductive interconnects or metal structures, such as wires, vias.

[0037] By providing dummy vias 126 within the lower dielectric layer 122, the dummy vias 126 provide structural support and rigidity to the device wafer 134 to reduce or eliminate the risk of delamination or distortion between wafers or layers within the device region 138 of the multi-layer stacked wafer caused by mechanical stresses including thermal expansion. In addition, the active TSVs 104 provide structural support at the peripheral region 136 of the device wafer 134.

[0038] Figure 2 A cross-sectional view 200 of some embodiments of a stacked image sensor having an imaging wafer 204, a device wafer 134, and a logic wafer 202 is shown.

[0039] Some embodiments of the imaging wafer 204 bonded to the bottom side of the device wafer 134 are shown. Some embodiments of the logic wafer 202 bonded to the top side of the device wafer 134 are shown. The imaging wafer 204 includes a dielectric interconnect structure 208 disposed below the device wafer 134 and an imaging substrate 210 disposed on a bottom surface of the dielectric interconnect structure 208.

[0040] The device region 138 of the imaging wafer 204 includes a plurality of transfer transistors 212 disposed within the dielectric interconnect structure 208 on a front side surface 226f of the imaging substrate 210. The imaging substrate 210 can be or include a semiconductor body (e.g., single crystal silicon, CMOS body, silicon-germanium, etc.) and have a first doping type (e.g., p-type). A plurality of floating diffusion nodes 228 are disposed within the imaging substrate 210 and on the front side surface 226f of the imaging substrate 210 and are coupled to the plurality of transfer transistors 212. A plurality of photodetectors 214 are disposed below the plurality of floating diffusion nodes 228 within the imaging substrate 210, with the plurality of photodetectors 214 separated from each other by an isolation structure 216. The isolation structure 216 is disposed along a back side surface 226b of the imaging substrate 210 and extends through the imaging substrate 210 between the plurality of photodetectors 214 forming a grid structure. A lower dielectric layer 230 is disposed on a bottom surface of the isolation structure 216. A grid structure 218 is disposed within the isolation structure 216 and aligned between the plurality of photodetectors 214. A plurality of optical filters 220 are disposed on the lower dielectric layer 230. A plurality of microlenses 222 are disposed on the optical filters 220.

[0041] As such, the device region 138 of the imaging die 204 includes imaging devices aligned under the dummy vias 126. The plurality of microlenses 222 are configured to direct incident light toward the plurality of photodetectors 214. The plurality of optical filters 220 each include a material configured to pass a first range of wavelengths while blocking a second range of wavelengths from reaching each of the photodetectors 214. The grid structure 218 and the isolation structure 216 provide isolation of photons and electrons between the plurality of photodetectors 214. The photodetectors 214 are configured to absorb incident light (e.g., photons) received through the microlenses 222 and generate respective electrical signals corresponding to the incident light. For example, the plurality of photodetectors 214 can generate electron-hole pairs from the incident light. The plurality of transfer transistors 212 can selectively form conductive channels in the imaging substrate 210 between the plurality of floating diffusion nodes 228 and the plurality of photodetectors 214 to transfer accumulated charge in the plurality of photodetectors 214 to the plurality of floating diffusion nodes 228. The plurality of transfer transistors 212 are configured to conduct and transfer accumulated charge from the plurality of floating diffusion nodes 228.

[0042] The peripheral region 136 of the imaging die 204 includes bond pads 206 laterally offset from the plurality of photodetectors 214. The bond pads 206 extend through the lower dielectric layer 230, through the isolation structure 216, through the imaging substrate 210, and into the dielectric interconnect structure 208. The bond pads 206 are configured to provide electrical connections to devices (e.g., the plurality of transfer transistors 212, the plurality of active elements 144, or active elements disposed within the logic die 202) of the stacked image sensor and / or another IC device. The isolation structure 224 is disposed within the imaging substrate 210 and can be configured as an STI structure and can be, for example, or include silicon dioxide, silicon nitride, silicon carbide, etc. The isolation structure 224 is disposed on a front side surface 226f of the imaging substrate 210 and extends along sidewalls of the bond pads 206 and is configured to increase electrical isolation between the bond pads 206 and other devices (e.g., the plurality of photodetectors 214). Further, the bond pads are aligned under the active TSVs 104.

[0043] The logic die 202 includes a logic dielectric layer 236 disposed over the upper dielectric layer 124 of the device die 134. The logic die 202 also includes a logic substrate 238 disposed on the logic dielectric layer 236. The logic dielectric layer 236 can be, or include, nitride, carbide, oxide, low-k dielectric, etc. The logic substrate 238 can be, or include, a semiconductor body (e.g., single crystalline silicon, CMOS body, silicon-germanium, etc.) and have a first doping type (e.g., p-type).

[0044] Multiple logic elements 232 are disposed within a logic substrate 238 in device region 138 and aligned above dummy vias 126. In some embodiments, the multiple logic elements 232 may include transistors, logic gates, or other elements configured as application-specific integrated circuits (ASICs) to facilitate downstream signal processing of charges accumulated by multiple photodetectors 214 read from device wafer 134. The multiple logic elements 232 are separated from each other by multiple STI structures 234. In some embodiments, the multiple STI structures 234 are disposed within the logic substrate 238 and aligned above active TSVs 104.

[0045] Figure 2 The active TSV 104 and the dummy via 126 can provide structural support for the device chip 134, which prevents delamination or deformation of the layers of the device chip 134 or the bonding interface between the device chip 134 and the logic chip 202.

[0046] Figure 3 It shows along Figure 2 The line A-A' intercepts Figure 2 A top view 300 of some embodiments of a stacked image sensor. It should be understood that, for ease of illustration, [the following is a description of the top view 300 of some embodiments of a stacked image sensor]. Figure 2 The lower dielectric layer is omitted in the top view 300. Figure 2 (122).

[0047] like Figure 3 As shown, a dummy via 126 is disposed within device region 138, and an active TSV 104 is disposed within peripheral region 136, wherein the dummy via 126 and the active TSV 104 are circular in shape. The dummy via 126 and the active TSV 104 are surrounded by a pad structure 140. The pad structure 140 may include a second dielectric pad 106 disposed along the outer edge of the dummy via 126 and the active TSV 104. The pad structure 140 may also include a first dielectric pad 128 disposed along the outer edge of the second dielectric pad 106.

[0048] Device region 138 includes a plurality of dummy vias 304, including dummy vias 126. Peripheral region 136 includes a plurality of active TSVs 302, including active TSVs 104. The plurality of active TSVs 302 surround the device wafer. Figure 2 The outermost perimeter p1 of 134 is provided. Thus, multiple active TSVs 302 are laterally arranged around the device region 138. In some embodiments, the number of dummy vias 304 and the height / width of the dummy vias can be selected based on design constraints and structural criteria to eliminate layer and wafer delamination and deformation within a multilayer stacked wafer.

[0049] existFigure 3 In the example of FIG. 3, dummy vias 304 are arranged such that the centers of the dummy vias 304 lie along horizontal lines 318 and vertical lines 320 that establish a series of rows and columns. Some of the horizontal and vertical lines are spaced equidistant from one another by a first distance dl to establish clusters of dummy vias (e.g., the centers of multiple dummy vias define a square when viewed from above). The first distance dl and the second distance d2 can also be less than the diameter width wd of the dummy vias. Then, nearest neighboring clusters are spaced apart from one another by a second distance d2, which is greater than the first distance dl. However, in other examples, the dummy vias can form linear clusters, triangular clusters, rectangular clusters, other polygonal clusters, or can be spaced randomly or pseudo-randomly apart to be separated at different / varying distances across the device region 138. Further, Figure 3 The plurality of active TSVs 302 in FIG. 3 form a structure that encloses or completely encloses the device region 138. Figure 3 The nearest plurality of active TSVs in FIG. 3 have centers that are spaced apart by a third distance that is greater than the first distance and can be greater or less than the second distance. Although Figure 3 FIG. 3 shows an example in which the plurality of active TSVs 302 is a single column thick, in other cases, multiple columns of active TSVs can be concentrically arranged around the device region 138.

[0050] Figure 4 FIG. 4 shows a cross-sectional view 400 of some embodiments of a semiconductor device including active TSVs 104 and dummy vias 126 corresponding to some other embodiments of a semiconductor device. Figure 1 FIG. 4 shows a cross-sectional view 400 of some embodiments of a semiconductor device including active TSVs 104 and dummy vias 126 corresponding to some other embodiments of a semiconductor device. Figure 4 FIG. 4 shows a cross-sectional view 400 of some embodiments of a semiconductor device including active TSVs 104 and dummy vias 126 corresponding to some other embodiments of a semiconductor device.

[0051] Figure 4 FIG. 4 shows a cross-sectional view 400 of some embodiments of a semiconductor device including active TSVs 104 and dummy vias 126 corresponding to some other embodiments of a semiconductor device.

[0052] The first dielectric liner 128 extends below the dummy via 126, and a bottom surface s1 of the dummy via 126 fully contacts the first dielectric liner 128. That is, the bottom surface s1 of the dummy via 126 contacts the first dielectric liner 128 across the entire bottom surface s1. The second dielectric liner 106 extends along the outer sidewall of the dummy via 126 from a top surface of the dummy via 126 to a top surface of the dielectric film 120 disposed above a bottom surface of the dummy via 126, with a vertical height that is less than the fourth height h4 of the dummy via 126. In this way, the first dielectric liner 128 is disposed between a bottom surface of the second dielectric liner 106 and the bottom surface s1 of the dummy via 126 along the outer sidewall of the dummy via 126. The first dielectric liner 128 extends from the bottom surface of the second dielectric liner 106 disposed above the lower dielectric layer 122 to below the bottom surface s1, and has a vertical height that is greater than the vertical height of the second dielectric liner 106 and less than the fourth height h4 of the dummy via 126.

[0053] When the first dielectric liner 128 and the second dielectric liner 106 are discussed in relation to the active TSV 104 and the dummy via 126 according to Figure 4 their aspects can correspond to formation techniques that achieve critical dimensions of the active TSV 104 and the dummy via 126.

[0054] Figure 5 Cross-sectional views 500 of some embodiments of semiconductor devices including an active TSV 104 and a dummy via 126 are shown corresponding to some other embodiments of semiconductor devices according to Figure 1 Figure 4 Alternative embodiments of the liner structure 140 and the dummy via 126 are shown.

[0055] Figure 5 The liner structure 140 is shown as a single dielectric structure. The liner structure 140 can be or include nitride, oxide, high-k dielectric, or other appropriate dielectric. The liner structure 140 extends along the outer sidewall of the active TSV 104 from a top surface of the active TSV 104 to a top surface of the ILD layer 116. The dummy via 126 extends from the upper dielectric layer 124 through the lower dielectric layer 122 and the dielectric film 120, with a bottom surface s1 of the dummy via 126 disposed within the device substrate 102 and above the front side surface 102f of the device substrate 102. The liner structure 140 extends from a top surface of the dummy via 126 to the bottom surface s1 of the dummy via 126. The bottom surface of the dummy via 126 fully contacts the device substrate 102.

[0056] Figure 6 Cross-sectional views 500 of some embodiments of semiconductor devices including an active TSV 104 and a dummy via 126 are shown corresponding to some other embodiments of semiconductor devices according to Figure 5 ​Cross-sectional view 600 of some other embodiments of the semiconductor device including active TSV 104 and dummy via 126. Figure 6 An alternative embodiment of the gasket structure 140 and the dummy through-hole 126 is shown.

[0057] Figure 6 The dummy via 126 extends from the bottom surface of the upper dielectric layer 124, with the bottom surface s1 of the dummy via 126 positioned above the bottom surface of the lower dielectric layer 122. The gasket structure 140 extends along the sidewall of the dummy via 126. The bottom surface s1 of the dummy via 126 is in complete contact with the lower dielectric layer 122.

[0058] Figure 1 , 4 Figures 5 and 6 show various configurations of the fourth height h4 of the dummy via 126 and the bottom surface s1 of the dummy via 126, the contact pad structure 140, the lower dielectric layer 122, the dielectric film 120, or the device substrate 102. Furthermore, various configurations of the pad structure 140 associated with the active TSV 104 are shown. These configurations are variations that achieve the desired critical dimensions of the dummy via 126, providing structural support to the device wafer 134 to prevent layer or wafer deformation or delamination of the stacked wafers. It should be understood that various configurations in one figure may be applicable to another figure. For example, the pad structure 140 shown as a single dielectric layer (… Figure 5 and Figure 6 ) can be applied to Figure 1 .and Figure 1 and Figure 4 The pad structure 140, which includes a first dielectric pad 128 and a second dielectric pad 106, can be applied to... Figure 5 and Figure 6 . Figure 5 and Figure 6 The height of the dummy through hole 126 can be used Figure 1 and Figure 4 ;vice versa.

[0059] Figure 7 It shows the relationship with Figure 2 Cross-sectional view 700 of some other embodiments of the stacked image sensor.

[0060] Figure 7A tie dielectric layer 704 is shown disposed on the bottom surface of the ILD layer 116 and the device dielectric layer 139. The tie dielectric layer 704 can be or include nitride, carbide, oxide, low-k dielectric, etc. A wire 706 is disposed within the tie dielectric layer 704 and contacts the bottom surface of the active TSV 104. The active TSV 104 can be connected to an active element (e.g., a device in the logic die 202, the device die 134, or the imaging die 204) through the wire 706 and / or one or more of the plurality of wires 130 disposed on the active TSV 104.

[0061] The wire 702, on the other hand, is disposed on the top surface of the dummy via 126 located within the upper dielectric layer 124. The wire 702 can provide additional structural support for the device die 134 that, in series with the dummy via 126, can prevent delamination or distortion of the layers and dies of the stacked image sensor. The wire 702 is electrically isolated from the active elements (e.g., elements in the logic die 202, the device die 134, or the imaging die 204). It should be understood that, Figure 1 Figure 2 and Figures 4-6 may include the wire 702 or the wire 706. Figure 7

[0062] Figure 8 shows cross-sectional views of some embodiments of a stacked image sensor according to other embodiments of the stacked image sensor. Figure 2 and Figure 7 shows cross-sectional views of some embodiments of a stacked image sensor according to other embodiments of the stacked image sensor. Figure 8 shows additional embodiments of the imaging die 204, the device die 134, and the logic die 202.

[0063] The imaging die 204 includes features described according to the imaging die 204. Figure 2 Figure 8 shows the tie pads 206 and tie pads 840 in the peripheral region 136 of the imaging die 204, where the device region 138 between the tie pads 206, 840 includes the associated circuitry in the photodetectors 214 and the imaging substrate 210. A plurality of floating diffusion nodes 228 are disposed below the plurality of photodetectors 214 within the imaging substrate 210. A dielectric interconnect structure 208 is disposed below the imaging substrate 210. A plurality of transfer transistors 212 are disposed within the dielectric interconnect structure 208. A plurality of wires 802 are disposed within the imaging substrate 210. The plurality of wires 802 can electrically couple one or more of the transfer transistors 212 or the tie pads 206, 840 to each other or to other active elements within the stacked image sensor. An imaging tie structure 804 is disposed on the dielectric interconnect structure 208. The imaging tie structure 804 includes an imaging tie dielectric 806 and a plurality of imaging tie pads 808. ​​​

[0064] The device wafer 134 has a first device bonding structure 816 including a first device bonding dielectric 814 and a plurality of device bonding contacts 810 and a plurality of device bonding pads 812. The imaging bonding structure 804 interfaces with the first device bonding structure 816 at a bonding interface, defining a bonding structure 842 connecting the imaging wafer 204 to the device wafer 134. The device wafer 134 further includes a device interconnect structure 818 disposed on a bottom side of the first device bonding structure 816, a device substrate 102 disposed on a bottom side of the device interconnect structure 818, and a second device bonding structure 824 disposed on a bottom side of the device bonding structure 816. The device interconnect structure 818 includes an interconnect dielectric structure 820 having a plurality of conductive lines and an interconnect structure 822.

[0065] The device substrate 102 has a plurality of active TSVs 302, 104 disposed in a peripheral region of the device wafer 134. The active TSVs 302, 104 extend from a bottom surface of the device substrate 102 through respective STI structures 108a, 845. The active TSVs 302, 104 extend into the interconnect dielectric structure 820 and are each electrically coupled to one or more of the plurality of conductive lines and the interconnect structure 822. Between the active TSVs 302, 104 and in the device region 138, a plurality of dummy vias 126, 304 are disposed within the device substrate 102. The plurality of dummy vias 126, 304 separate the plurality of active elements 144 and the plurality of STI structures 108b, 846 from the device substrate 102. Further, the plurality of dummy vias 126, 304 are electrically disconnected from the active elements of the stacked image sensor. The second device bonding structure 824 includes a second device bonding dielectric 826 having a plurality of device bonding contacts 828. The active TSVs 302, 104 are electrically coupled to one or more of the device bonding contacts 828.

[0066] The logic die 202 includes a logic bonding structure 830, a logic interconnect structure 838 disposed on the logic bonding structure 830, and a logic substrate 238 disposed on the logic bonding structure 830. The logic bonding structure 830 includes a logic bonding dielectric 832 that includes device bonding contacts 834 and device bonding pads 835. The second device bonding structure 824 meets the logic bonding structure 830 at a bonding interface, thereby defining a bonding structure 844 that connects the logic die 202 to the device die 134. The logic die 202 also includes a logic interconnect structure 838 disposed on the logic bonding structure 830 and a logic substrate 238 disposed on the logic bonding structure 830. The logic interconnect structure 838 includes a logic dielectric layer 236 having a plurality of conductive lines 836. The logic substrate 238 has a plurality of logic elements 232 separated from one another by a plurality of STI structures 234. The plurality of logic elements 232 are disposed within the device region 138 of the logic die 202.

[0067] The plurality of dummy vias 126, 304 are electrically isolated and disconnected from active elements. The plurality of dummy vias 126, 304 provide structural support to prevent delamination or distortion caused by stress between layers or dies of the stacked image sensor. For example, the plurality of dummy vias 126, 304 can prevent delamination of the device substrate 102 from the second device bonding dielectric 826 or delamination of the device die 134 from the logic die 202.

[0068] Figures 9-18 Various views 900-1800 illustrating some embodiments of a method for forming a stacked image sensor including dummy vias in a device region and active TSVs in a peripheral region are shown. Although the method is described with reference to the various views 900-1800, it should be understood that the method is not limited to the method described with reference to the various views 900-1800, but can be independent of the method. Moreover, although the method is described as a series of acts, it will be understood that the acts are not limited to the order in which they are presented, and that the disclosed method is applicable to other structures. Figures 9-18 The structures shown, however, should not be construed as limiting the method, but rather, the structures can be independent of the method. Moreover, although the method is described as a series of acts, it will be understood that the acts are not limited to the order in which they are presented, and that the disclosed method is applicable to other structures. In other embodiments, some of the acts shown and / or described can be omitted in whole or in part. Figures 9-18 The structures shown, however, should not be construed as limiting the method, but rather, the structures can be independent of the method. Moreover, although the method is described as a series of acts, it will be understood that the acts are not limited to the order in which they are presented, and that the disclosed method is applicable to other structures. In other embodiments, some of the acts shown and / or described can be omitted in whole or in part. Figures 9-18 The structures shown, however, should not be construed as limiting the method, but rather, the structures can be independent of the method. Moreover, although the method is described as a series of acts, it will be understood that the acts are not limited to the order in which they are presented, and that the disclosed method is applicable to other structures. In other embodiments, some of the acts shown and / or described can be omitted in whole or in part.

[0069] As Figure 9As shown in cross-sectional view 900, a plurality of STI structures 108a, 108b are formed within the device substrate 102 disposed along the front surface 102f of the device substrate 102. The STI structure 108a is formed within a peripheral region 136 of the device substrate 102, and the STI structure 108b is formed within a device region 138 of the device substrate 102. The peripheral region 136 extends around the outer periphery (not shown) of the device substrate 102, wherein the peripheral region 136 surrounds the device region 138. In some embodiments, the device substrate 102 may be or include a bulk silicon substrate, single-crystal silicon, epitaxial silicon, silicon-germanium (SiGe), or another suitable semiconductor material and / or include a first doping type (e.g., p-type). In some embodiments, the plurality of STI structures 108a, 108b may be or include silicon dioxide, silicon nitride, silicon carbide, low-k dielectric, etc.

[0070] In some embodiments, a patterned photoresist (not shown) is formed along the front surface 102f. An etching process (not shown) is performed through the patterned photoresist to form openings (not shown) in the peripheral region 136 and device region 138 of the device substrate 102, and the patterned photoresist is removed. A dielectric layer (not shown) is filled into the openings, and the dielectric material may be deposited along the front surface 102f. A removal process (not shown), such as a chemical mechanical planarization (CMP) process, is applied to the dielectric layer to remove the dielectric layer from the front surface 102f and form a plurality of STI structures 108a, 108b.

[0071] like Figure 10 As shown in cross-sectional view 1000, a plurality of dielectric layers 132, an ILD layer 116, and a bonding dielectric layer 704 are formed over the front surface 102f of the device substrate 102. The plurality of dielectric layers 132 are formed along the front surface 102f of the device substrate 102 and along the exposed surfaces of the plurality of STI structures 108a, 108b. The plurality of dielectric layers 132 includes a first dielectric layer 110 formed on the front surface 102f, a second dielectric layer 112 formed on the first dielectric layer 110, and a third dielectric layer 114 formed on the second dielectric layer 112. For example, the plurality of dielectric layers 132 can be formed by a series of deposition processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), thermal oxidation, etc. In some embodiments, the first dielectric layer 110 is a barrier layer or a photoresist protective oxide, which may be or includes a dielectric, a low-k dielectric, or an oxide (e.g., silicon dioxide). In some embodiments, the second dielectric layer 112 is a contact etch stop layer and may be or include a dielectric, a low-k dielectric, or a nitride (e.g., silicon nitride). In some embodiments, the third dielectric layer 114 is a dielectric filler layer and may be or include an oxide or other dielectric material.

[0072] ILD layer 116 is formed on third dielectric layer 114 and can be formed according to a deposition process such as CVD, PECVD, ALD, etc. ILD layer 116 can be or include nitride, carbide, oxide, low-k dielectric, etc. Bonding dielectric layer 704 is formed on ILD layer 116 and can be formed according to a deposition process such as CVD, PECVD, ALD, etc. Bonding dielectric layer 704 can be or include nitride, carbide, oxide, low-k dielectric, etc. Wire 706 is formed within bonding dielectric layer 704 aligned with perimeter region 136. Wire 706 can be formed according to etching (not shown) through a patterned photoresist (not shown), a deposition process (not shown) of metal, and a subsequent removal process such as planarization (not shown). Wire 706 can be or include copper, tungsten, aluminum, or other metals.

[0073] As shown in cross-sectional view 1100, Figure 11 Figure 10 The structure is rotated 180 degrees for further processing steps on the backside surface 102b of device substrate 102 opposite the frontside surface 102f. Dielectric film 120 is formed along the frontside surface 102f. Dielectric film 120 can be formed according to a deposition process such as CVD, PECVD, ALD, etc. Dielectric film 120 can be or include oxide such as silicon dioxide, low-k dielectric material, etc. Lower dielectric layer 122 is formed on the top surface of dielectric film 120 according to a deposition process such as CVD, PECVD, ALD, etc. Lower dielectric layer 122 can be or include nitride, carbide, oxide, low-k dielectric, etc. Patterned photoresist 1102 is formed on lower dielectric layer 122. Patterned photoresist 1102 can be patterned according to a photolithography process (not shown) where TSV opening 1104 is formed over lower dielectric layer 122 in perimeter region 136 and aligned with wire 706. Patterned photoresist 1102 forms a dummy via opening 1106 over lower dielectric layer 122 in device region 138. TSV opening 1104 is larger than dummy via opening 1106. In some embodiments, the width of TSV opening 1104 ranges from one to two, two to three, or more than three times the width of dummy via opening 1106.

[0074] As shown in cross-sectional view 1100, Figure 12 ​As shown in cross-sectional view 1200, a first etching 1202 is performed through the TSV opening 1104 and the dummy via opening 1106 of the patterned photoresist 1102. In some embodiments, the first etching 1202 may be a dry etching, reactive ion etching (RIE), plasma etching, wet etching, or other etching processes. The first etching 1202 forms an active TSV opening 1204 aligned below the TSV opening 1104 in the peripheral region 136. The active TSV opening 1204 extends through the lower dielectric layer 122, the dielectric film 120, the device substrate 102, the STI structure 108a, and the plurality of dielectric layers 132. The active TSV opening 1204 is exposed on the top surface of the ILD layer 116 aligned above the conductor 706.

[0075] The first etching 1202 also forms a dummy via opening 1206 in device region 138 aligned with the lower dummy via opening 1106. The dummy via opening 1206 extends through the lower dielectric layer 122 and into the dielectric film 120, thereby exposing the dielectric film 120, wherein the bottom surface of the dummy via opening 1206 is above the bottom surface of the dielectric film 120. In other embodiments (not shown), the dummy via opening 1206 extends into the lower dielectric layer 122, and its bottom surface is above the bottom surface of the lower dielectric layer 122. In other embodiments (not shown), the dummy via opening 1206 extends through both the lower dielectric layer 122 and the dielectric film 120, and into the device substrate 102, wherein the bottom surface of the dummy via opening 1206 is on the front side above. Because the dummy via opening 1106 in the patterned photoresist 1102 is smaller than the TSV opening 1104 in the patterned photoresist 1102, the dummy via opening 1206 is formed to have a critical dimension (e.g., height and width) smaller than the critical dimension of the active TSV opening 1204.

[0076] like Figure 13 As shown in the cross-sectional view 1300, the pad structure 140 is formed above the lower dielectric layer 122, and the active TSV opening 1204 and the dummy via opening 1206 are also present. Figure 12 The liner structure 140 is formed by a first dielectric liner 128 and a second dielectric liner 106. The first dielectric liner 128 extends along the top surface of the lower dielectric layer 122 and the active TSV opening 1204 and the dummy via opening 1206. Figure 12 The exposed sidewalls of the dielectric layer 122, dielectric film 120, device substrate 102, STI structure 108a, multiple dielectric layers 132, and ILD layer are deposited. The first dielectric pad 128 can be deposited according to CVD, PECVD, ALD, or some other suitable deposition or growth process.

[0077] A second dielectric pad 106 is formed above the top surface of the first dielectric pad 128 and along the sidewalls of the first dielectric pad 128. In some embodiments, the second dielectric pad 106 is not formed on the bottom surface of the first dielectric pad 128 within the peripheral region 136 or device region 138. In other embodiments, the second dielectric pad 106 is formed on the bottom surface (not shown) of the first dielectric pad 128. The second dielectric pad 106 may be deposited according to a CVD process, a PECVD process, an ALD process, or some other suitable deposition or growth process. In some embodiments, the thickness of the second dielectric pad 106 deposited is greater than the thickness of the first dielectric pad 128.

[0078] In some embodiments, the first dielectric pad 128 and the second dielectric pad 106 comprise the same material. In other embodiments, the first dielectric pad 128 and the second dielectric pad 106 comprise different materials, wherein the first dielectric pad 128 may be or comprise a nitride such as silicon nitride, a high-k dielectric comprising a nitride, or other nitrides, and the second dielectric pad 106 may be or comprise an oxide, such as silicon dioxide, a high-k dielectric comprising an oxide, or other oxides. In some embodiments, the first dielectric pad 128 is formed of a material having a faster etch rate relative to the etch rate of the second dielectric pad 106. After the pad structure 140 is formed, an active TSV opening 1302 is defined within a peripheral region 136 defined by the sidewalls of the second dielectric pad and the first exposed surface of the first dielectric pad 128 perpendicularly aligned with the plurality of dielectric layers 132. Furthermore, after forming the liner structure 140, a dummy through-hole opening 1304 is defined within the device region 138 defined by the sidewall of the second dielectric liner and the second exposed surface of the first dielectric liner 128 perpendicularly aligned with the dielectric film 120. Thus, the second exposed surface of the first dielectric liner 128 is located above the first exposed surface of the first dielectric liner 128. It should be understood that... Figure 13 It can be modified to have a pad structure with a single material, instead of the first and second dielectric pads 128, 106, for example, as Figures 5-6 The pad structure 140 shown.

[0079] like Figure 14 As shown in the cross-sectional view 1400, a second etching 1402 is performed over the second dielectric pad 106 within the active TSV opening 1302 and the dummy via opening 1304. In some embodiments, the second etching 1402 may be dry etching, RIE, plasma etching, wet etching, or other etching processes. The second etching 1402 thins the second dielectric pad 106 and etches through the first exposed surface of the first dielectric pad 128. Figure 13). For example, the height of the top surface of the second dielectric liner 106 is reduced by a reduction amount 1408. In addition, the thickness of the portions of the second dielectric liner 106 extending into the active TSV opening 1302 and the dummy via opening 1304 are reduced. In the peripheral region 136, the second etch 1402 etches through the ILD layer 116 and exposes the wire 706. In the device region 138, the second etch 1402 etches through the second exposed surface of the first dielectric liner 128 Figure 13 ) and exposes the dielectric film 120. In this way, the size of the active TSV opening 1302 is increased to an active TSV opening 1404 in the peripheral region 136 defined by the sidewalls of the second dielectric liner 106, the sidewalls of the ILD layer 116, and the top surface of the wire 706. The size of the dummy via opening 1304 is increased to a dummy via opening 1406 in the device region 138 defined by the sidewalls of the second dielectric liner 106 and the dielectric film 120. The active TSV opening 1404 is formed to have a first height hi extending from the top surface of the second dielectric liner 106 to the top surface of the wire 706. The second dielectric liner 106 is formed to have a second height h2 extending from the top surface of the second dielectric liner 106 disposed above the lower dielectric layer 122 to the top surface of the ILD layer 116. The first dielectric liner 128 is formed to have a third height h3 extending from the top surface of the first dielectric liner 128 disposed above the lower dielectric layer 122 to the top surface of the ILD layer 116. The dummy via opening 1406 is formed to have a fourth height h4 extending from the top surface of the second dielectric liner 106 to the exposed surface of the dielectric film 120.

[0080] As shown in the cross-sectional view 1500 of Figure 15 , a metal layer 1502 is formed over the second dielectric liner 106 and within the active TSV opening 1404 of Figure 14 and the dummy via opening 1406 of Figure 14 . The metal layer 1502 can be deposited according to a CVD process, a PECVD process, an ALD process, or some other suitable deposition or growth process. The metal layer 1502 can be or include one or more of copper, tungsten, aluminum, or another suitable metal. The metal layer 1502 is deposited in the peripheral region 136 and the device region 138, extending along the inner sidewalls of the second dielectric liner 106, the inner sidewalls of the ILD layer 116, and contacting the wire 706 and the dielectric film 120. In addition, the metal layer 1502 is deposited on the exposed surface of the dielectric film 120.

[0081] As shown in the cross-sectional view 1600 of Figure 16 , the metal layer 1502 is removed from the exposed surface of the dielectric film 120. The metal layer 1502 can be removed according to a wet etch process, a dry etch process, or some other suitable removal process. The metal layer 1502 is removed from the exposed surface of the dielectric film 120, leaving the metal layer 1502 in the peripheral region 136 and the device region 138, extending along the inner sidewalls of the second dielectric liner 106, the inner sidewalls of the ILD layer 116, and contacting the wire 706 and the dielectric film 120. In addition, the metal layer 1502 is removed from the exposed surface of the dielectric film 120. Figure 15A removal process is applied to the metal layer 1502 to form the active TSV 104 and the dummy via 126. The removal process can be a planarization process or an etching process, which removes the metal layer 1502 from the top surface of the second dielectric pad 106. Figure 15 Following the removal process, an active TSV 104 is formed, extending from the top surface of the second dielectric pad 106 to the top surface of the conductor 706 within the peripheral region 136. Following the removal process, an exposed surface extending from the top surface of the second dielectric pad 106 to the dielectric film 120 is formed. Figure 14 ) ) dummy through hole 126.

[0082] like Figure 17 As shown in cross-sectional view 1700, an upper dielectric layer 124 is formed along the top surface of the second dielectric pad 106 and the top surfaces of the active TSV 104 and the dummy via 126. The upper dielectric layer 124 can be formed according to deposition processes such as CVD, PECVD, ALD, etc. The upper dielectric layer 124 can be or include nitrides, carbides, oxides, low-k dielectrics, etc. Multiple conductive lines 130 are formed within the upper dielectric layer 124. The multiple conductive lines 130 can be formed by etching (not shown) through patterned photoresist (not shown) and subsequently filled with a metal layer (not shown) extending through the planarized upper dielectric layer 124 and above the upper dielectric layer 124. One of the multiple conductive lines 130 is formed to contact the top surface of the active TSV 104. Some of the multiple conductive lines 130 are formed within the upper dielectric layer 124, adjacent to but not in contact with the dummy via 126 in the device region 138. The upper dielectric layer 124, the bonding dielectric layer 704, and the layers and feature-defined device wafer 134 between the two.

[0083] like Figure 18 As shown in cross-sectional view 1800, the logic chip 202 and the imaging chip 204 are formed from active elements. The logic chip 202 is bonded to the top side of the device chip 134. The imaging chip 204 is bonded to the bottom side of the device chip 134. The logic chip 202 includes various features, such as a plurality of logic elements 232, and the imaging chip 204 includes various features, such as a plurality of photodetectors 214, and according to... Figure 2 Other features discussed.

[0084] Figures 19-22 Cross-sectional views 1900-2200 illustrate an alternative embodiment of a method for forming a stacked image sensor, the method being derived from... Figure 11 An alternative embodiment begins, wherein active TSV openings and dummy via openings are formed by separate etching.

[0085] like Figure 19A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figure 11 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138.

[0086] A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figure 20 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figure 12 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138.

[0087] A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figure 21 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figure 20 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138.

[0088] A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figure 22 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figure 12 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figure 13 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138. Figures 14-18 A cross-sectional view 1900 of the device 100 is shown in FIG. 19. A patterned photoresist 1902 is formed over the lower dielectric layer 122. The patterned photoresist 1902 is an alternative feature to the patterned photoresist 1102 of FIG. 11, where the patterned photoresist 1902 has a TSV opening 1104 formed over the lower dielectric layer 122 in the peripheral region 136 and aligned with the conductive line 706. The patterned photoresist 1902 covers the device region 138.

[0089] Figure 23Some embodiments of a method 2300 of forming a stacked image sensor or semiconductor device including active TSVs in a peripheral region of a device wafer and dummy vias in a device region are shown. Although the method 2300 is shown and / or described as a series of acts or events, it is understood that the method is not limited to the order shown or acts. Accordingly, in some embodiments, these acts can be performed in an order different than that shown, and / or can be performed concurrently. Further, in some embodiments, the acts or events shown can be subdivided into multiple acts or events, which can be performed at separate times or concurrently with other acts or sub-acts. In some embodiments, some of the acts or events shown can be omitted, and other acts or events not shown can be included.

[0090] At act 2302, a plurality of dielectric layers are formed on a front side surface of a device substrate. The device substrate has a peripheral region laterally offset from a device region. An ILD layer is formed on the plurality of dielectric layers. A bonding dielectric layer is formed on the ILD layer, and a wire is formed within the bonding dielectric layer in the peripheral region. Figures 9-10 Cross-sectional views 900-1000 corresponding to some embodiments of act 2302 are shown.

[0091] At act 2304, a dielectric film is formed on the device substrate, and a lower dielectric layer is formed on the dielectric film. A patterned photoresist is formed on the lower dielectric layer. Figure 11 and Figure 19 Cross-sectional views 1100 and 1900 corresponding to some embodiments of act 2304 are shown.

[0092] At act 2306, active TSV openings are formed in the peripheral region, and dummy via openings are formed in the device region. The TSV openings are formed through the lower dielectric layer, the dielectric film, and the plurality of dielectric layers. The dummy via openings are formed through the lower dielectric layer and extend to the dielectric pad. The dummy via openings are formed to a height less than a height of the active TSV openings. Figure 12 、 20 Cross-sectional views 1200, 2000, 2100, and 2200 corresponding to some embodiments of act 2306 are shown.

[0093] At act 2308, a pad structure including a first dielectric pad and a second dielectric pad is formed over the lower dielectric layer and within the active TSV openings and the dummy via openings. Figure 13 Cross-sectional view 1300 corresponding to some embodiments of act 2308 is shown.

[0094] At act 2310, etching is performed through a bottom surface of the pad structure to expose the metal wire in the peripheral region and the dielectric film in the device region.Figure 14 A cross-sectional view 1400 is shown corresponding to some embodiments of act 2310.

[0095] At act 2312, an active TSV is formed within the active TSV opening extending from the top surface of the spacer structure to the metal wire, and a dummy via is formed within the dummy via opening extending from the top surface of the spacer structure to the dielectric film. Figures 15-16 A cross-sectional view 1500-1600 is shown corresponding to some embodiments of act 2312.

[0096] At act 2314, an upper dielectric layer is formed over the dielectric spacer, the active TSV, and the dummy via. A metal wire is formed within the upper dielectric layer on the active TSV. Figure 17 A cross-sectional view 1700 is shown corresponding to some embodiments of act 2314.

[0097] At act 2316, a logic die is formed and an imaging die is formed, the logic die is bonded to the upper dielectric layer, and the imaging die is bonded to the bonding dielectric layer, wherein the dummy via is electrically isolated from the active element. Figure 18 A cross-sectional view 1800 is shown corresponding to some embodiments of act 2316.

[0098] Accordingly, in some embodiments, the disclosure relates to a semiconductor device having one or more dummy vias disposed within a device region and one or more active TSVs disposed in a peripheral region laterally surrounding the device region. The one or more dummy vias are electrically isolated from the active element.

[0099] In some embodiments, the disclosure relates to a semiconductor device having a device substrate having a front side surface opposite a backside surface, an upper dielectric layer over the backside surface, a substrate through via (TSV) extending from the upper dielectric layer through the device substrate, and a dummy via laterally offset from the TSV. A top surface of the dummy via and a top surface of the TSV are substantially coplanar, and a bottom surface of the dummy via is separated from the front side surface by the device substrate. The dummy via is electrically isolated from one or more active elements.

[0100] In some embodiments, the disclosure relates to a semiconductor device having an imaging die, a logic die, and a device substrate disposed between the logic die and the imaging die, the device substrate having a front side surface opposite a backside surface, wherein the device substrate has a peripheral region laterally separated from a device region. The semiconductor device also has an upper dielectric layer over the backside surface, a wire disposed under the front side surface and within the peripheral region, a substrate through via (TSV) disposed within the device substrate, the TSV extending from the upper dielectric to the wire; a dummy via disposed within the device region and extending from a bottom surface of the upper dielectric layer toward the device substrate. The dummy via is separated from the front side surface of the device substrate, and a bottom surface of the dummy via is broken from the metal structure.

[0101] A method of forming a semiconductor device, the method including forming a lower dielectric layer over a backside surface of a device substrate, wherein the device substrate has a front side surface opposite the backside surface, and the device substrate has a peripheral region laterally separated from a device region. The method includes forming a wire over the front side surface of the device substrate within the peripheral region. The method includes one or more etches through a top surface of the lower dielectric layer. The one or more etches form a substrate through via (TSV) opening extending the lower dielectric layer and the device substrate within the peripheral region. A bottom surface of the TSV opening is separated from the wire. The one or more etches form a dummy via opening extending into the lower dielectric layer within the device region. A bottom surface of the dummy via opening is over the front side surface of the device substrate. The method includes forming a dielectric liner within the TSV opening and the dummy via opening. The method includes performing a second etch through the TSV opening, the second etch extending the TSV opening to a top surface of the wire. The method includes forming a metal layer within the TSV opening and the dummy via opening, wherein the metal layer forms a TSV within the TSV opening and a dummy via within the dummy via opening.

[0102] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, include: The device substrate has a front surface opposite to the back surface; An upper dielectric layer is located above the back side surface; A substrate via extends from the upper dielectric layer through the device substrate; as well as A dummy through-hole is laterally offset from the through-hole of the substrate, wherein the top surface of the dummy through-hole and the top surface of the through-hole of the substrate are substantially coplanar, and the bottom surface of the dummy through-hole is separated from the front surface by the device substrate.

2. The semiconductor device according to claim 1, characterized in that, Also includes: The lower device dielectric is located between the upper dielectric layer and the device substrate, and the dummy via is disposed within the lower device dielectric; as well as A first dielectric pad is disposed between the substrate through-hole and the outer side wall of the device substrate, and the first dielectric pad is disposed between the outer side wall of the dummy through-hole and the lower device dielectric.

3. The semiconductor device according to claim 2, characterized in that, Also includes: A second dielectric pad is disposed along the sidewall of the substrate through-hole and the sidewall of the dummy through-hole, wherein the second dielectric pad extends along the inner sidewall of the first dielectric pad to separate the substrate through-hole and the dummy through-hole from the first dielectric pad.

4. The semiconductor device according to claim 2, characterized in that, The first dielectric pad spans the entire bottom surface of the dummy through-hole and directly contacts the bottom surface of the dummy through-hole.

5. The semiconductor device according to claim 1, characterized in that, Also includes: A conductor is disposed within the upper dielectric layer, wherein the conductor contacts the dummy through-hole.

6. The semiconductor device according to claim 1, characterized in that, Also includes: A lower dielectric layer disposed below the upper dielectric layer, and a dielectric film disposed between the lower dielectric layers, wherein the substrate via extends through the lower dielectric layer and the dielectric film, and the dummy via extends through the lower dielectric layer and into the dielectric film.

7. A semiconductor device, characterized in that, include: Imaging chip; Logic chip; as well as A device substrate is disposed between the logic wafer and the imaging wafer, the device substrate having a front surface opposite to the back surface, wherein the device substrate has a peripheral region laterally separated from the device region. An upper dielectric layer is located above the back side surface; A wire is disposed below the front surface and located within the surrounding area; A substrate through-hole is disposed within the device substrate, the substrate through-hole extending from the upper dielectric layer to the conductor; as well as A dummy via is disposed within the device region and extends from the bottom surface of the upper dielectric layer toward the device substrate, wherein the dummy via is separated from the front surface of the device substrate.

8. The semiconductor device according to claim 7, characterized in that, The substrate via is one of a plurality of substrate vias, and the dummy via is one of a plurality of dummy vias. The plurality of substrate through-holes are disposed in the peripheral area, the plurality of dummy through-holes are disposed in the device area, and the plurality of substrate through-holes surround the outer periphery of the plurality of dummy through-holes.

9. The semiconductor device according to claim 8, characterized in that, The plurality of dummy vias are perpendicularly separated from the plurality of active elements disposed within the device substrate in the device region.

10. The semiconductor device according to claim 7, characterized in that, The substrate via and the dummy via extend from a common surface defined by the bottom surface of the upper dielectric layer, wherein the height of the substrate via is greater than the height of the dummy via, and the width of the top surface of the substrate via is greater than the width of the top surface of the dummy via.

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