Passivation contact battery with selective polycrystalline silicon layer

Abstract

The utility model discloses a passivation contact cell with a selective polycrystalline silicon layer, which comprises a silicon wafer body with a back surface and a back metal electrode, and the back metal electrode comprises a back main gate electrode and a back fine gate electrode. The back surface comprises a plurality of first structures, a plurality of second structures and a plurality of third structures, and the first structures and the second structures are alternately distributed. According to the utility model, the laser slotting area is 40%-80% of the total area of the back of the cell, which is beneficial to balancing the passivation performance of the cell while reducing the parasitic absorption of the polysilicon to light. The passivation contact cell provided by the utility model has high short-circuit current, open-circuit voltage and fill factor.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of solar cell, concretely relates to a passivated contact cell with selective poly-silicon layer. BACKGROUND

[0002] The emergence of tunnel oxide passivated contact solar cell (TOPCon) has attracted great attention to high-efficiency crystalline silicon solar cell technology. TOPCon cell uses N-type silicon as substrate material, which is composed of ultra-thin silicon oxide layer and highly doped poly-silicon layer. Since the tunneling potential (4.5eV) of the tunnel oxide layer is higher than the tunneling potential (3.1eV) of the electron, it can reduce the carrier recombination between the metal electrode and the silicon, so that the electron is more easily tunneling and collected. Another function of the tunnel oxide layer is full-area passivation. The excellent passivation capability further improves the efficiency of the TOPCon solar cell. The record of the photoelectric conversion efficiency of the TOPCon cell has exceeded 26.5%.

[0003] Selective poly-silicon passivated contact is an ideal choice to reduce the parasitic absorption of N-type crystalline silicon solar cell and provide better current collection. TOPCon cell uses a passivated contact structure of tunnel oxide layer and doped poly-silicon layer. Since the doped poly-silicon layer itself has serious parasitic absorption, this structure is only used on the back surface of the TOPCon cell. The current industrialization thickness of the tunnel oxide layer is 1-2nm, and the thickness of the doped poly-silicon layer is 100-150nm. In order to further reduce the negative impact of the parasitic absorption of the doped poly-silicon layer itself on the electrical performance of the cell, a processing technology capable of forming a selective doped poly-silicon layer is usually used. Among them, the most important one is to ablate the phosphorus-doped poly-silicon in the non-metalized area by laser. The laser pattern scheme usually adopts parallel to the fine grid line. Since the main grid paste does not burn through the passivation film, the laser avoidance position of the main grid is not considered. Compared with the conventional cell structure, the short-circuit current density (Jsc) of this type of cell is increased by about 0.5mA / cm 2 .

[0004] However, this type of laser pattern scheme usually adopts the way of partially overlapping laser spot path, which results in the existence of the area where two laser paths overlap. This part has undergone two laser scans, which causes more damage to the cell silicon substrate than once laser scan, and the Voc electrical performance of the cell will be reduced.

[0005] Secondly, the existing laser pattern scheme avoids the position of the fine grid line on the back surface of the cell and then performs laser processing. The laser area accounts for 90%-95% of the back surface area of the cell. This scheme can maximize the reduction of the parasitic absorption of poly-silicon to light and improve the current density Jsc of the cell, but it will damage the TOPCon characteristic passivation structure of the cell, resulting in reduced passivation performance in the laser area, which is not conducive to the Voc of the cell.

[0006] Finally, the prior art laser patterning scheme, generally using parallel to the fine grid uninterrupted scanning, the heavily doped polysilicon layer in the laser scanning area is removed, the heavily doped polysilicon layer has a conductive property similar to metal, and the carrier transport resistance on it can be ignored, and the removal of the heavily doped polysilicon layer will cause the resistance of the carrier transport in this area to increase rapidly. And in the prior art, because the main grid paste does not have the burning-through property for SiNx, and does not directly contact the silicon substrate or the phosphorus-doped polysilicon, whether to avoid the main grid part is ignored in the design of the laser patterning structure, and such a structure scheme causes the carrier transport distance in the laser scanning area to be longer, the resistance loss is larger, and the solar cell fill factor FF is reduced. Practical new type content

[0007] In view of the defects and shortcomings of the prior art, the present application provides an improved passivated contact cell with a selective polysilicon layer, which balances the passivation performance of the cell while reducing the parasitic absorption of polysilicon to light, and has improved open-circuit voltage, fill factor, and short-circuit current.

[0008] To achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows:

[0009] A passivated contact cell, comprising a silicon wafer body having a back surface and a back metal electrode, the back metal electrode comprising a back main grid electrode and a back fine grid electrode; the back surface comprising a first structure, a second structure and a third structure, the first structure and the second structure each having a plurality of and alternatingly distributed;

[0010] The first structure comprises a first tunneling oxide layer, a first doped polysilicon layer and a first back passivation layer formed in sequence on the back surface of the silicon wafer body, and the back fine grid electrode penetrating through the first back passivation layer and in contact with the first doped polysilicon layer;

[0011] The second structure comprises m open hole regions and n carrier transport regions, and m=n+1, m is greater than or equal to 2, and any two adjacent open hole regions are separated by one carrier transport region;

[0012] The open hole region comprises a second back passivation layer formed on the back surface of the silicon wafer body;

[0013] The carrier transport region comprises a second tunneling oxide layer, a second doped polysilicon layer and a third back passivation layer formed in sequence on the back surface of the silicon wafer body;

[0014] The third structure comprises a third tunneling oxide layer, a third doped polysilicon layer, a fourth back passivation layer and a back main grid electrode formed in sequence on the back surface of the silicon wafer body.

[0015] The first tunneling oxide layer, the second tunneling oxide layer, the third tunneling oxide layer are connected or integrally formed, the first doped polysilicon layer, the second doped polysilicon layer, the third doped polysilicon layer are connected or integrally formed, the first back surface passivation layer, the second back surface passivation layer, the third back surface passivation layer, the fourth back surface passivation layer are connected or integrally formed; wherein the doped polysilicon layer is a phosphorus-doped polysilicon layer.

[0016] Preferably, the doping concentration of phosphorus atoms in the phosphorus-doped polysilicon is 3.0 x 10 20 ~8.0 x 10 20 / cm 3 , and the sheet resistance value is 40~100Ω / sq.

[0017] In some embodiments, the first tunneling oxide layer, the second tunneling oxide layer, the third tunneling oxide layer are integrally formed, the first doped polysilicon layer, the second doped polysilicon layer, the third doped polysilicon layer are integrally formed, the first back surface passivation layer, the second back surface passivation layer, the third back surface passivation layer, the fourth back surface passivation layer are integrally formed.

[0018] In some embodiments, the cross section of the opening region is selected from at least one of a rectangle, a square, a trapezoid or a rhombus.

[0019] In some embodiments, the width of each opening region is 100~500µm.

[0020] In some embodiments, in each second structure, the distance between every two adjacent opening regions is equal. The distance refers to the line distance, i.e. the distance between the centers of the two opening regions.

[0021] In some embodiments, in each second structure, the distance between every two adjacent opening regions is 200~600µm.

[0022] In some embodiments, the cross section of the carrier transport region is selected from at least one of a rectangle, a square, a trapezoid or a rhombus.

[0023] In some embodiments, in each carrier transport region, the width of the second tunneling oxide layer and the second doped polysilicon layer is the same.

[0024] In some embodiments, the total area of the opening regions accounts for 40%~80% of the total area of the region of the back surface of the silicon wafer body other than the back surface main grid electrode and the back surface fine grid electrode.

[0025] In some embodiments, the thickness of the first tunneling oxide layer, the second tunneling oxide layer, and the third tunneling oxide layer is the same.

[0026] In some embodiments, the thickness of the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer is the same.

[0027] In some embodiments, the thickness of the first back surface passivation layer, the second back surface passivation layer, the third back surface passivation layer, and the fourth back surface passivation layer is the same.

[0028] In some embodiments, the line width of the back surface main grid electrode is 30-100 µm, and the interval is 10-20 mm.

[0029] In some embodiments, the line width of the back surface fine grid electrode is 10-60 µm, and the interval is 0.9-1.5 mm.

[0030] In some embodiments, the back surface main grid electrode and the back surface fine grid electrode are perpendicular to each other.

[0031] In some embodiments, the silicon wafer body is an N-type single crystal silicon substrate.

[0032] In some embodiments, the resistivity of the silicon wafer body is 0.8-1.5 Ω•cm, and the thickness is 100-180 µm.

[0033] In some embodiments, the tunneling oxide layer is SiO x with a thickness of 0.5-2.5 nm, preferably 1.0-1.5 nm.

[0034] In some embodiments, the front surface of the silicon wafer body is textured, and the front surface structure layer includes a boron-doped emitter and a front surface passivation layer formed on the front surface of the silicon wafer body.

[0035] In some embodiments, the front surface passivation layer is a combination of two or three of aluminum oxide, silicon nitride, silicon oxynitride, silicon dioxide, and magnesium fluoride. Preferably, the front surface passivation layer adopts a passivation stack design of aluminum oxide + silicon carbide, wherein the preferred thickness of aluminum oxide is 2-10 nm, and the preferred thickness of silicon nitride is 20-50 nm, and the refractive index of silicon nitride is 2.1-2.2.

[0036] In some embodiments, the back surface passivation layer is a stack film composed of two of aluminum oxide, titanium dioxide, silicon nitride, and silicon oxynitride.

[0037] In some embodiments, the back surface passivation layer is an aluminum oxide / silicon nitride stack, wherein the aluminum oxide has a thickness of 15-30 nm, the silicon nitride has a refractive index of 2.1-2.2, and the thickness of the silicon nitride is 50-65 nm.

[0038] The aforementioned passivated contact cell of the utility model can be used in photovoltaic modules. The photovoltaic module generally comprises a front encapsulation layer, a photovoltaic cell and a back encapsulation layer. The photovoltaic cell comprises the aforementioned passivated contact cell.

[0039] Compared with the prior art, the utility model has the following advantages:

[0040] The passivated contact cell with the selective polycrystalline silicon layer of the utility model balances the passivation performance of the cell while reducing the parasitic absorption of polycrystalline silicon to light, and the cell has improved open circuit voltage and fill factor. In addition, the cell structure of the utility model helps to reduce the transmission distance of the carriers in the laser ablation area, the carriers can be collected by the fine grid more quickly, and the fill factor FF of the cell is improved, which has great advantages, especially under special conditions such as broken grid. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 It is a plan view of the back surface of the cell in the specific embodiment of the utility model;

[0042] Figure 2 It is a plan view of the back surface of the cell in the specific embodiment of the utility model; Figure 1 It is an A-A sectional view of the cell piece in the specific embodiment of the utility model;

[0043] Figure 3 It is an A-A sectional view of the cell piece in the specific embodiment of the utility model; Figure 1 It is a B-B sectional view of the cell piece in the specific embodiment of the utility model;

[0044] Figure 4 It is a schematic diagram of the processing area of a traditional cell;

[0045] Figure 5 It is a schematic diagram of the cross-sectional structure of a traditional cell;

[0046] Figure 6 It is a schematic diagram of the structure of a selective polycrystalline silicon cell formed by the laser processing method of the prior art;

[0047] Figure 7 It is a schematic diagram of the structure of a selective polycrystalline silicon cell formed by the laser processing method of the prior art; Figure 6 It is a schematic diagram of the structure of a selective polycrystalline silicon cell formed by the laser processing method of the prior art;

[0048] Figure 8 It is a schematic diagram of the structure of a selective polycrystalline silicon cell formed by the laser processing method of the prior art; Figure 6 It is a schematic diagram of the structure of a selective polycrystalline silicon cell formed by the laser processing method of the prior art;

[0049] Wherein: 1-silicon wafer body, 2-boron-doped emitter, 3-tunneling oxide layer, 31-first tunneling oxide layer, 32-second tunneling oxide layer, 33-third tunneling oxide layer, 4-doped polysilicon layer, 41-first doped polysilicon layer, 42-second doped polysilicon layer, 43-third doped polysilicon layer, 5-opening region, 6-secondary opening region, 71-front surface passivation layer, 72-back surface passivation layer, 721-first back surface passivation layer, 722-second back surface passivation layer, 723-third back surface passivation layer, 724-fourth back surface passivation layer, 81-front surface fine grid electrode, 82-back surface fine grid electrode, 9-back surface main grid electrode. DETAILED DESCRIPTION

[0050] In the prior art, when a passivated contact cell with a selective polysilicon layer is prepared, a processing technology capable of forming a selectively doped polysilicon layer is usually used. However, first, the laser pattern scheme usually adopts a method in which laser spot paths partially overlap (in order to fully etch, so as to avoid that some areas are not etched), so that there is an area where two laser paths overlap, and this part is subjected to twice laser scanning, which causes greater damage to the silicon substrate of the cell than once laser scanning, and the Voc electrical performance of the cell is thus reduced. Second, in the existing laser pattern scheme, after avoiding the position of the back surface fine grid line of the cell, laser processing is performed, and the laser area accounts for 90% to 95% of the back surface area of the cell. Such a scheme can maximize the reduction of parasitic absorption of polysilicon to light and improve the current density Jsc of the cell, but it will damage the passivation structure of the TOPCon feature of the cell, resulting in reduced passivation performance in the laser area, which is not conducive to the Voc of the cell. Finally, in the existing laser pattern scheme, an uninterrupted scanning parallel to the fine grid is usually adopted, and the heavily doped polysilicon layer in the laser scanning area is removed. The heavily doped polysilicon layer has a conductive property similar to that of metal, and the transmission resistance of the carrier thereon can be ignored. The removal of the heavily doped polysilicon layer will cause the resistance of the carrier transmission in this area to increase rapidly. Moreover, in the prior art, because the main grid paste does not have a burn-through property to SiNx and does not directly contact the silicon substrate or the phosphorus-doped polysilicon, whether the main grid part is avoided is ignored in the design of the laser pattern structure. Such a structure scheme causes the transmission distance of the carrier in the laser scanning area to be longer and the resistance loss to be greater, which will cause the fill factor FF of the solar cell to decrease.

[0051] The main idea of the utility model lies in: the utility model adopts a new laser pattern scheme to form a new selective polysilicon passivated contact structure on the back surface of a TOPCon solar cell. Each laser path in the scheme adopts a separate form (the laser opening area is separated from the carrier transmission area), and there is no laser path overlap area. Therefore, there is no damage to the silicon substrate caused by twice laser scanning, and the open-circuit voltage Voc will be improved to a certain extent.

[0052] Secondly, in the design of the laser grooving pattern in this scheme, the laser grooving area is set to 40% to 80% of the total area of ​​the back of the battery. This is beneficial to reduce the parasitic absorption of light by polycrystalline silicon while balancing the passivation performance of the battery.

[0053] Finally, in this invention, each laser scanning line on the back of the Topcon solar cell is separated by a phosphorus-doped polycrystalline silicon layer, eliminating the overlap of laser scanning paths and retaining part of the phosphorus-doped polycrystalline silicon layer structure around the main grid. This structural approach helps reduce the transport distance of charge carriers in the laser ablation region, allowing them to be collected more quickly by the fine grid. In conventional solutions, the ablation width formed by the overlap of multiple laser lines is W2, and charge carriers in the central region need to travel a distance of 1 / 2*W2 to reach the doped polycrystalline silicon layer (e.g., ...). Figure 6 In this invention, the ablation width formed by the laser scanning line is W1. The charge carriers in the central region need to travel a distance of 1 / 2 * W1 to reach the doped polycrystalline silicon layer (e.g., ...). Figure 1 The charge carriers then travel through a portion of the phosphorus-doped polysilicon layer surrounding the main gate to the fine gate lines. The heavily doped polysilicon layer has metal-like conductivity, and the carrier transport resistance on it is negligible. Removing the heavily doped polysilicon layer rapidly increases the carrier transport resistance in this region. Since the width of W1 is much smaller than the width of W2, this solution can significantly reduce the carrier transport distance in the high-resistance region of laser scanning, reducing carrier transport losses and helping carriers to be collected more quickly by the fine gate, thus improving the battery's fill factor FF. This solution is particularly advantageous under special conditions such as gate breakage.

[0054] The back surface of the battery structure is subjected to a phosphorus diffusion process, and a selectively polycrystalline silicon passivation contact structure is formed on the back surface of the solar cell by using a specially designed laser slotting scheme; the laser pattern is parallel to the fine grid, the laser line spacing is greater than the width of a single light spot, there is no overlapping part, and meanwhile, a part of the area near the main grid is avoided, and 40% to 80% of the entire back surface area of the battery is subjected to laser processing. The polycrystalline silicon selective structure has the following advantages: ① there is no overlapping part of the laser, and damage to the silicon substrate caused by secondary laser is avoided, which is beneficial to improving the passivation performance of the solar cell and improving the open-circuit voltage Voc; ② the laser slotting area of 40% to 80% keeps balance between reducing the parasitic absorption of polycrystalline silicon to light and the passivation performance of the battery; ③ the middle is separated by a phosphorus heavily doped polycrystalline silicon layer, there is no overlapping of the laser scanning lines, and part of the phosphorus doped polycrystalline silicon layer structure around the main grid is reserved, and such a structure helps to reduce the transmission distance of the carriers in the laser ablation area, the carriers can be collected by the fine grid more quickly, in addition, the heavily doped polycrystalline silicon layer has a metal-like conductive property, and the transmission resistance of the carriers thereon can be ignored, after the heavily doped polycrystalline silicon layer is removed, the resistance of the carrier transmission in this area increases rapidly, therefore, the scheme can significantly reduce the transmission distance of the carriers in the high-resistance area of the laser scanning, reduce the transmission loss of the carriers, and help the carriers to be collected by the fine grid more quickly, improve the fill factor FF of the battery, and the scheme has more advantages under special conditions such as broken grid.

[0055] In the description of the utility model, it is understood that the terms "first", "second", "third" and "fourth" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second", "third" and "fourth" can explicitly or implicitly include at least one of the features. In the description of the utility model, the meaning of "multiple" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0056] Based on this, the utility model provides a kind of polycrystalline silicon passivation contact battery.

[0057] Specifically, the structure of polycrystalline silicon passivation contact battery is as shown in Figures 1-3 The top view of the back surface of the battery, Figure 1 The top view of the back surface of the battery, Figure 2 The A-A sectional view of the battery piece (perpendicular to the fine grid electrode, and avoids the main grid electrode part), Figure 1 The A-A sectional view of the battery piece (perpendicular to the fine grid electrode, and avoids the main grid electrode part), Figure 3 The B-B sectional view of the battery piece (passing through the main grid electrode, and the sectional view perpendicular to the main grid electrode). Figure 1 The B-B sectional view of the battery piece (passing through the main grid electrode, and the sectional view perpendicular to the main grid electrode).

[0058] The battery includes a silicon wafer body 1 with a back surface and a back metal electrode, the back metal electrode includes a back main grid electrode 9 and a back fine grid electrode 82, the back surface includes a first structure, a second structure and a third structure, the first structure and the second structure are respectively provided with a plurality of and are alternately distributed;

[0059] The first structure includes a first tunneling oxide layer 31, a first doped polysilicon layer 41 and a first back passivation layer 721 formed in sequence on the back surface of the silicon wafer body 1, and the back fine grid electrode 82 penetrating through the first back passivation layer 721 and in contact with the first doped polysilicon layer 41;

[0060] The second structure includes m opening regions 5 and n carrier transport regions, and m=n+1, m is greater than or equal to 2, and any two adjacent opening regions are separated by one carrier transport region (although Figure 2 m is 2 in the figure, but the utility model is not limited to 2, and can be 3 or more opening regions 5);

[0061] The opening region 5 includes a second back passivation layer 722 formed on the back surface of the silicon wafer body 1;

[0062] The carrier transport region includes a second tunneling oxide layer 32, a second doped polysilicon layer 42 and a third back passivation layer 723 formed in sequence on the back surface of the silicon wafer body 1;

[0063] The third structure includes a third tunneling oxide layer 33, a third doped polysilicon layer 43, a fourth back passivation layer 724 and a back main grid electrode 9 formed in sequence on the back surface of the silicon wafer body 1;

[0064] The first tunneling oxide layer 31, the second tunneling oxide layer 32 and the third tunneling oxide layer 33 are connected or integrally formed, the first doped polysilicon layer 41, the second doped polysilicon layer 42 and the third doped polysilicon layer 43 are connected or integrally formed, and the first back passivation layer 721, the second back passivation layer 722, the third back passivation layer 733 and the fourth back passivation layer 724 are connected or integrally formed. The doped polysilicon layer 4 is a phosphorus doped polysilicon layer.

[0065] The processing area and the battery cross-sectional structure of the conventional battery are respectively shown in Figure 4 、 5 The laser processing method and the selective polysilicon battery structure formed by the prior art are respectively shown in Figures 6-8 (Wherein, Figure 7 is Figure 6 the battery chip A-A cross-sectional view in Figure 8 is Figure 6The second laser opening area 6 is damaged by the laser overlapping scanning on the silicon wafer 1 after the laser ablation treatment on the silicon wafer.

[0066] Through the comparison of the three different laser patterning schemes and the battery structure, the utility model has the following advantages: ① there is no overlapping part of the laser, which avoids the damage of the secondary laser to the silicon substrate (such as Figure 8 The laser slotting area is 40% to 80%, which balances the reduction of the parasitic absorption of the polysilicon to light and the passivation performance of the battery; ③ between the parallel adjacent laser paths, the middle is separated by the heavily doped polysilicon layer, there is no overlap of the laser scanning line, and part of the phosphorus-doped polysilicon layer structure around the main grid is reserved, which helps to reduce the transmission distance of the carriers in the laser ablation area, and the carriers can be collected by the fine grid more quickly. In addition, the heavily doped polysilicon layer has a metal-like conductive property, and the transmission resistance of the carriers thereon can be ignored. After the heavily doped polysilicon layer is removed, the resistance of the carrier transmission in this area increases rapidly. Therefore, the utility model can significantly reduce the transmission distance of the carriers in the high-resistance area of the laser scanning, reduce the transmission loss of the carriers, help the carriers to be collected by the fine grid more quickly, and improve the fill factor FF of the battery. Especially under special conditions such as broken grid, the utility model scheme has more advantages.

[0067] Further, the first tunneling oxide layer, the second tunneling oxide layer, the third tunneling oxide layer are integrally formed, the first doped polysilicon layer, the second doped polysilicon layer, the third doped polysilicon layer are integrally formed, and the first back surface passivation layer, the second back surface passivation layer, the third back surface passivation layer, and the fourth back surface passivation layer are integrally formed.

[0068] Further, the cross section of the opening area is selected from a rectangle, a square, a trapezoid, or a rhombus. Although the drawing shows a square, it is only an example, and the utility model is not limited thereto.

[0069] Further, the width of each opening area is 100-500µm.

[0070] Further, in each second structure, the distance between adjacent two opening areas is equal.

[0071] Further, in each second structure, the distance between adjacent two opening areas is 200-600µm.

[0072] Further, the cross section of the carrier transmission area is selected from a rectangle, a square, a trapezoid, or a rhombus.

[0073] Further, the width of the second tunneling oxide layer and the second doped polysilicon layer in each carrier transport region is the same.

[0074] Further, the total area of the opening region accounts for 40% to 80% of the total area of the region on the back surface of the silicon wafer body other than the back surface main grid electrode and the back surface fine grid electrode.

[0075] Further, the thickness of the first tunneling oxide layer, the second tunneling oxide layer, and the third tunneling oxide layer is the same; the thickness of the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer is the same; and the thickness of the first back surface passivation layer, the second back surface passivation layer, the third back surface passivation layer, and the fourth back surface passivation layer is the same.

[0076] Further, the line width of the back surface main grid electrode is 30 to 100 µm, and the interval is 10 to 20 mm.

[0077] Further, the line width of the back surface fine grid electrode is 10 to 60 µm, and the interval is 0.9 to 1.5 mm.

[0078] Further, the back surface main grid electrode and the back surface fine grid electrode are perpendicular to each other.

[0079] In some embodiments, the silicon wafer body 1 is an N-type single crystal silicon substrate, and the N-type single crystal silicon substrate is subjected to wet cleaning to remove the surface damage layer of the silicon wafer, clean the surface metal impurities and oil stains, and form a textured surface. The back surface is polished and cleaned to form a flat surface. Boron diffusion treatment is then performed to form a boron-doped emitter 2 on the front surface and the back surface of the N-type silicon wafer, respectively. The emitter on the back surface of the N-type silicon wafer is removed, and the back surface is polished. Then, a tunneling oxide layer 3 and a doped polysilicon layer 4 are grown on the back surface using conventional methods in the field.

[0080] Laser ablation is then performed to form a selective polysilicon layer. In the non-metallized region, the non-metallized region is subjected to ablation treatment using a laser patterning scheme specially designed by the present application. The laser spot is a rectangular or square spot, the length of the spot is 100 µm to 500 µm, the width is 100 µm to 500 µm, the line spacing is 200 µm to 600 µm, there is no overlapping part between the spot lines, and the main grid electrode part is also reserved with a width of 100 µm to 500 µm without laser treatment. In terms of laser, picosecond or nanosecond laser with a wavelength of 200 to 1200 nm is used, preferably 355 nm ultraviolet laser, 532 nm green laser, 650 nm red laser, 820 nm near-infrared laser, or 1030 nm infrared laser, the laser frequency is 50 to 300 KHz, the laser scanning speed is 5 to 25 m / s, and the energy density of the laser treatment is 0.1 to 5 J / cm2 Finally, a passivation film is deposited on the front and rear surfaces using methods conventional in the art; metal electrodes are printed and sintered on the front and rear surfaces.

[0081] The above scheme is further described below in conjunction with specific examples; it should be understood that these examples are used to illustrate the basic principles, main features and advantages of the present application, and the present application is not limited in scope by the following examples; the implementation conditions used in the examples can be further adjusted according to specific requirements, and the implementation conditions not specified are usually the conditions in conventional experiments.

[0082] The example is a laser pattern scheme designed using the present application, forming a polysilicon layer passivation structure. Comparative Example 1 is a conventional TOPCon cell without a selective polysilicon structure on the back; Comparative Example 2 is a cell structure of an existing laser processing scheme, with some overlap between the spot lines.

[0083] Example 1:

[0084] Using the foregoing specific structure, the parameters are designed during preparation: the spot uses a square spot of 250x250µm, the scheme of avoiding the main grid line + laser path separation is used, the path line spacing is 300µm, 3 times of laser path scanning are performed at each grid line interval, 300µm is reserved on one side of the main grid line without laser processing, the fine grid interval is 1000µm, the main grid interval is 10.8mm, and the laser opening area ratio is 70.8%.

[0085] Example 2:

[0086] Using the foregoing specific structure, the parameters are designed during preparation: the spot uses a square spot of 250x250µm, the scheme of avoiding the main grid line + laser path separation is used, the path line spacing is 300µm, 2 times of laser path scanning are performed at each grid line interval, 300µm is reserved on one side of the main grid line without laser processing, the fine grid interval is 1000µm, the main grid interval is 10.8mm, and the laser opening area ratio is 47.2%.

[0087] Comparative Example 1:

[0088] The conventional TOPCon cell does not have a selective polysilicon structure on the back, and the back sequentially has a tunneling oxide layer, a phosphorus-doped polysilicon layer and a back passivation layer, and the same back fine grid electrode and back main grid electrode as in Example 1 are provided.

[0089] Comparative Example 2:

[0090] The battery structure of the existing laser processing scheme has a part of the spot lines overlapping. The preparation is basically the same as that of Example 1, but the parameters are designed as follows: a square spot with a size of 250x250 µm is used, a scheme of avoiding the main grid lines and superimposing the laser path is used, the line spacing of the laser path lines is 220 µm, 4 times of laser path scanning are performed at each grid line interval, the overlapping width between the laser path lines is 30 µm, the fine grid interval is 1000 µm, the main grid interval is 10.8 mm, and the laser opening area ratio is 91%. Comparative Example 3:

[0091] The preparation is basically the same as that of Example 1, but the parameters are designed as follows: a square spot with a size of 708x708 µm is used, the main grid lines are not avoided, only one time of laser path scanning is performed between the fine grid lines, 300 µm is reserved on one side of the main grid line without laser processing, the fine grid interval is 1000 µm, the main grid interval is 10.8 mm, and the laser opening area ratio is the same as that of Example 1, which is 70.8%.

[0092] Performance test:

[0093] The batteries obtained in the above examples and comparative examples are subjected to the following performance tests, and the test method is as follows: an IV tester is used to test the battery photoelectric conversion efficiency under standard light power and related electrical performance parameters under a simulated solar light source.

[0094] The specific test results are shown in Table 1 (Eta; conversion efficiency, Voc: open circuit voltage, Jsc: short circuit current density, FF: fill factor), and the electrical performance data is the average data of 100 Pcs batteries.

[0095] Table 1 Performance results

[0096]

[0097] It can be seen that, compared with Comparative Example 1, the conversion efficiency and short circuit current density of the battery of Example 1 are obviously improved (although the difference is small, but in the field of solar cells, a change of 0.1% is usually a huge progress); compared with Comparative Example 2, the conversion efficiency of the battery of Example 1 is improved, and the open circuit voltage is also obviously improved; compared with Comparative Example 3, the conversion efficiency of the battery of Example 1 is improved, and the fill factor is also improved. The battery of Example 1 has excellent comprehensive performance.

[0098] The above examples are only for illustrating the technical concept and characteristics of the present application, the purpose is to enable those skilled in the art to understand the content of the present application and to implement it, and it cannot limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit and essence of the present application should be covered within the protection scope of the present application.

[0099] The endpoints of the ranges and any values disclosed herein are not limited to the precise values recited as exactly that endpoint point. The endpoints of the ranges and any values are understood to be approximate values. For ranges having an upper and lower limit, the range can be understood to include each integer within the defined range. The upper and lower limits of the range can independently be included in the range, or independently excluded from the range. The range can also be understood to include single values within the range, which can be the upper or lower limit of the range. For ranges having an upper and lower limit, the range can be understood to include each integer within the defined range. The upper and lower limits of the range can independently be included in the range, or independently excluded from the range. The range can also be understood to include single values within the range, which can be the upper or lower limit of the range.

Claims

1. A passivated contact cell with selective poly-silicon layer comprising a silicon wafer body having a back surface and a back surface metal electrode, the back surface metal electrode comprising a back surface main grid electrode and a back surface fine grid electrode; characterized in that: The back surface comprises a first structure, a second structure and a third structure, the first structure and the second structure each have a plurality of and are alternately distributed; The first structure comprises a first tunneling oxide layer, a first doped polysilicon layer and a first back passivation layer formed in sequence on the back surface of the silicon wafer body, and the back surface fine grid electrode penetrating through the first back passivation layer and in contact with the first doped polysilicon layer; The second structure comprises m opening regions and n carrier transport regions, and m=n+1, m is greater than or equal to 2, and any two adjacent opening regions are separated by one carrier transport region; The opening region comprises a second back passivation layer formed on the back surface of the silicon wafer body; The carrier transport region comprises a second tunneling oxide layer, a second doped polysilicon layer and a third back passivation layer formed in sequence on the back surface of the silicon wafer body; The third structure comprises a third tunneling oxide layer, a third doped polysilicon layer, a fourth back passivation layer and a back surface main grid electrode formed in sequence on the back surface of the silicon wafer body; The first tunneling oxide layer, the second tunneling oxide layer and the third tunneling oxide layer are connected or integrally formed, the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer are connected or integrally formed, and the first back passivation layer, the second back passivation layer, the third back passivation layer and the fourth back passivation layer are connected or integrally formed.

2. The passivated contact cell of claim 1, wherein: The first tunneling oxide layer, the second tunneling oxide layer and the third tunneling oxide layer are integrally formed, the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer are integrally formed, and the first back passivation layer, the second back passivation layer, the third back passivation layer and the fourth back passivation layer are integrally formed; wherein the doped polysilicon layer is a phosphorus doped polysilicon layer.

3. The passivated contact cell of claim 1, wherein: The cross section of the opening region is selected from at least one of a rectangle, a square, a trapezoid or a rhombus; and / or, the cross section of the carrier transport region is selected from at least one of a rectangle, a square, a trapezoid or a rhombus.

4. The passivated contact cell of claim 3, wherein: The width of each opening region is 100-500μm.

5. The passivated contact cell of claim 3, wherein: In each second structure, the distance between any two adjacent opening regions is equal.

6. The passivated contact cell of claim 3, wherein: In each second structure, the distance between any two adjacent opening regions is 200-600μm.

7. The passivated contact cell of claim 1, wherein: In each carrier transport region, the width of the second tunneling oxide layer and the second doped polysilicon layer is the same.

8. The passivated contact cell of claim 1, wherein: The total area of the opening region accounts for 40%-80% of the total area of the region of the back surface of the silicon wafer body excluding the back surface main grid electrode and the back surface fine grid electrode.

9. The passivated contact cell of claim 1, wherein: The thickness of the first tunneling oxide layer, the second tunneling oxide layer and the third tunneling oxide layer is the same; and / or, the thickness of the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer is the same; and / or, the thickness of the first back passivation layer, the second back passivation layer, the third back passivation layer and the fourth back passivation layer is the same.

10. The passivated contact cell of claim 1, wherein: The line width of the back main grid electrode is 30-100 μm, and the interval is 10-20 mm; and / or, the line width of the back fine grid electrode is 10-60 μm, and the interval is 0.9-1.5 mm; and / or, the back main grid electrode and the back fine grid electrode are perpendicular to each other.

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