Deep trench isolation structure and integrated device

Abstract

The embodiment of the utility model provides a deep trench isolation structure. The deep trench isolation structure comprises a deep trench isolation core extending into a substrate, a first film surrounding the deep trench isolation core, a second film located between the first film and the deep trench isolation core, and a third film located between the second film and the deep trench isolation core, the first film has a first conduction band at a first band energy, the second film has a second conduction band at a second band energy less than the first band energy, and the third film has a third conduction band at a third band energy greater than the second band energy. The deep trench isolation structure isolates different semiconductor devices from each other, thereby reducing the amount of dark current and parasitic capacitance occurring between the semiconductor devices.

Description

TECHNICAL FIELD

[0001] Embodiments of the present utility model relate to an integrated device, and particularly to a deep trench isolation structure in an integrated device. BACKGROUND

[0002] In integrated circuits, front-end-of-line (FEOL) devices can interfere with each other when in close proximity. Such interference can occur through charge transfer and parasitic capacitance formed between the devices. Various isolation techniques have been developed to reduce the amount of dark current and parasitic capacitance that can occur between adjacent devices on a substrate. Deep trench isolation is a technique used to reduce interference between different pixels and semiconductor devices. Deep trench isolation involves forming a deep trench isolation (DTI) structure that extends directly into a substrate between devices formed on the substrate. SUMMARY

[0003] Embodiments of the present utility model provide a deep trench isolation structure including a deep trench isolation core extending into a substrate, a first film surrounding the deep trench isolation core and comprising a first material having a first conduction band at a first band energy, a second film between the first film and the deep trench isolation core comprising a second material having a second conduction band at a second band energy that is less than the first band energy, and a third film between the second film and the deep trench isolation core comprising a third material having a third conduction band at a third band energy that is greater than the second band energy.

[0004] Embodiments of the present utility model provide an integrated device including a plurality of photodetectors within a substrate, a plurality of floating diffusion nodes arranged in an array on a first side of the substrate, an interconnect structure coupled to the plurality of floating diffusion nodes, and a deep trench isolation core on a second side of the substrate, wherein the deep trench isolation core is spaced apart from the plurality of photodetectors, the plurality of floating diffusion nodes, and the interconnect structure by a first film, a second film, and a trapping film extending between the first film and the second film.

[0005] Based on the above, the deep trench isolation structure of the embodiment of the present application comprises a first film, a second film, a third film and a deep trench isolation core. The energy difference of the materials used for the first film, the second film and the third film forms a potential well around the deep trench isolation core to trap electrons in the potential well. The trapped electrons repel electrons from the interface between the first film and the substrate out of the deep trench isolation structure. The repulsion of the electrons forms an enhanced depletion region around the deep trench isolation structure, which in turn accumulates a larger number of holes at the interface. The enhanced depletion region reduces the number of electrons interacting with charge trapping at the interface between the substrate and the deep trench isolation structure. The larger negative charge at the interface and the enhanced depletion region reduce the dark current that can travel between semiconductor devices isolated by the deep trench isolation structure.

[0006] In order to make the above features and advantages of the embodiments of the present application more obvious and easy to understand, the following embodiments are specifically described, and the detailed description is made below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] FIG. 1A 、 FIG. 1B and FIG. 1C show cross-sectional views and band diagrams of some embodiments of a DTI structure having a first film, a second film and a third film around a DTI core, where the second film is a trapping film.

[0008] FIG. 2A 、 FIG. 2B and FIG. 2C show cross-sectional views and top views of an integrated device including FIG. 1A and FIG. 1B DTI structures.

[0009] FIG. 3A and FIG. 3B show cross-sectional views and band diagrams of alternative embodiments of a DTI structure including a fourth film extending between the DTI core and the third film.

[0010] FIG. 4 to FIG. 10 show a series of cross-sectional views of some embodiments of a method of forming a DTI structure having a first film, a second film and a third film around a DTI core, where the second film is a trapping film.

[0011] FIG. 11 show a flowchart of some embodiments of a method of forming a DTI structure having a first film, a second film and a third film around a DTI core, where the second film is a trapping film.

[0012] REFERENCE NUMERALS

[0013] 100a, 100c, 200a, 200b, 300a, 400, 600, 700, 800, 900, 1000: sectional view; 100b, 300b: band diagram; 102: substrate; 102a: first surface; 102b: second side; 103: DTI structure; 104: DTI core; 105: rounded distal end; 106: first membrane; 108: second membrane; 110: third membrane; 112: potential well; 114: difference; 116: first band energy; 118: second band energy; 120: third band energy; 122, 304: fourth band energy; 124: fifth band energy; 126: electron; 127: interface; 128: hole; 130: depletion region; 200c: top view; 202: photodetector; 204: pixel; 206: floating diffusion node; 208: transfer transistor; 210: interconnect structure; 212: contact; 214: wiring layer level; 216: via layer level; 218: color filter; 220: lens; 222: semiconductor device; 224: source / drain terminal; 302: fourth membrane; 402: first mask layer; 404: first etch process; 406: first opening; 602: first conformal membrane; 702: second conformal membrane; 802: third conformal membrane; 902: conformal fill layer; 1002: planarization process; 1100: flowchart; 1102, 1104, 1106, 1108, 1110, 1112: operation; A-A': line; B: rectangle; E c : conduction band; E f : Fermi level. DETAILED DESCRIPTION

[0014] The following disclosure provides different embodiments or examples, for implementing various features of the present disclosure. Specific examples of structures and arrangements are presented in order to provide a thorough description of the present disclosure. Of course, these are merely examples and are in no way intended to limit the scope of this disclosure. For example, in the following description, a first feature formed "on" or "above" a second feature can include embodiments where the first feature is formed directly on the second feature as well as embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Additionally, the present disclosure can use component numbers and / or letters repeatedly throughout various examples. Such repetition is for the sake of simplicity and clarity in describing the present disclosure and is not intended to limit the relationship between various embodiments and / or configurations.

[0015] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] The DTI structure includes an insulating film and a DTI core. The DTI structure extends between and isolates different semiconductor devices or components on a substrate, thereby reducing the amount of dark current and parasitic capacitance that can occur between the semiconductor devices. In some embodiments, the insulating film is silicon dioxide. The silicon dioxide insulating film has an inherent negative charge that repels electrons and accumulates holes near the interface between the insulating film and the substrate. Since dark current is dominated by electrons repelled by the negative charge, the accumulation of holes reduces the dark current between devices separated by the DTI structure. Due to the inherent negative charge, the DTI structure acts as an n-type transistor with a gate voltage below the threshold voltage. Thus, the inherent negative charge of the insulating film creates a depletion region around the DTI structure such that there is little or no conduction between semiconductor devices separated by the DTI structure. Since no bias is applied to the DTI core, no channel between the semiconductor devices is induced during normal operation.

[0017] As semiconductor manufacturing technology improves, semiconductor devices utilizing new technologies are often formed more closely together to reduce form factor, lower size limitations, and increase manufacturing yield of the devices. Reducing the amount of space between devices increases the amount of dark current that can exist between the semiconductor devices. For example, in a pixel array, the close proximity of photodetector regions, body contacts, and floating diffusion regions to one another can result in undesirable charge transfer or false readings, thereby causing greater interference between the components and between different pixels. In some embodiments, the increased amount of interference between semiconductor devices can result in false readings of the sensor and failure of the device. Isolating DTI structures with a single insulating film can not provide enough resistance to dark current to effectively isolate the semiconductor devices. Thus, a DTI structure with increased resistance to dark current is desired.

[0018] A DTI structure is provided that includes a first film, a second film, and a third film surrounding a DTI core, where the second film is a trapping film. The trapping film includes a material having a conduction band with a band energy that is significantly lower (e.g., at least 1 electron volt lower) than the band energy of the materials used for the first film and the third film. The difference in the band energy of the materials used for the first film, the second film, and the third film forms a potential well surrounding the DTI core. A process is performed after forming the first film, the second film, and the third film to trap electrons within the potential well. The trapped electrons repel electrons from the interface between the first film and the substrate out of the DTI structure. The repelling of the electrons results in the formation of an enhanced depletion region surrounding the DTI structure, which in turn accumulates a greater number of holes at the interface. The enhanced depletion region reduces the number of electrons that interact with charge trapping at the interface between the substrate and the DTI structure. The greater negative charge at the interface and the enhanced depletion region reduce the dark current that can travel between semiconductor devices isolated by the DTI structure.

[0019] FIG. 1A FIG. 1B FIG. 1C Cross-sectional views 100a, band diagrams 100b, and cross-sectional views 100c illustrate some embodiments of a DTI structure having a first film, a second film, and a third film surrounding a DTI core, where the second film is a trapping film. The band diagrams 100b show the conduction band energy of the layers taken along line A-A’ of the cross-sectional views 100a. FIG. 1A FIG. 1C The cross-sectional views 100c of FIG. 1A show the subset taken from rectangle B of

[0020] As shown in FIG. 1A ​​​As shown in cross-sectional view 100a, the DTI structure 103 extends into the substrate 102. The DTI structure 103 includes a DTI core 104, a first film 106, a second film 108, and a third film 110. In some embodiments, the DTI core 104 is a semiconductor material or contains a semiconductor material, such as polysilicon. The DTI core 104 is surrounded by the first film 106, the second film 108, and the third film 110. The first film 106 extends between the substrate 102 and the second film 108. The second film 108 extends between the first film 106 and the third film 110. The second film 108 may also be referred to as a trapping film. The second film 108 is spaced apart from the substrate 102 by the first film 106, and the second film 108 is spaced apart from the DTI core 104 by the third film 110. The first film 106, the second film 108, and the third film 110 space the DTI core 104 from the substrate 102. The DTI structure 103 extends from the first surface 102a of the substrate 102 and has a circular distal end 105 facing away from the first surface 102a. The circular distal end 105 approximately maintains the uniform thickness of the first film 106, the second film 108, and the third film 110 of the DTI structure 103, thereby enhancing the depletion region (see...). FIG. 1C The thickness of 130) is approximately uniform around the DTI structure 103.

[0021] like FIG. 1B The band structure diagram 100b shows the conduction band E of the DTI core 104, the first film 106, the second film 108, the third film 110, and the substrate. c In a steady state, each layer of the DTI structure 103 has a Fermi level E that is constant at both ends of the interface between the DTI structure 103 and the substrate 102. f In a steady state, the conduction band E c With Fermi level E f The differences lie in the material properties of both the DTI structure 103 and the substrate 102. The conduction band E measured within the first film 106... c It has a first band energy of 116. The conduction band E measured within the second membrane 108. c The conduction band Ec, measured within the third film 110, has a second band energy of 118. The conduction band Ec, measured within the substrate 102, has a third band energy of 120. c It has a fourth band energy of 122. The conduction band E measured within the DTI core 104. c It has a fifth band energy 124. In some embodiments, the third band energy 120 is greater than the first band energy 116. In other embodiments, the third band energy 120 is equal to or less than the first band energy 116.

[0022] The first membrane 106 comprises a first material having conduction bands with a first band energy 116. The second membrane 108 comprises a second material having conduction bands with a second band energy 118. The third membrane 110 comprises a third material having conduction bands with a third band energy 120. In some embodiments, the first material and the second material are the same material. The first, second, and third materials are all selected such that the first band energy 116 and the third band energy 120 are 1 electron volt greater than or equal to the second band energy 118. That is, the difference 114 between the second band energy 118 and the first band energy 116 and the third band energy 120 is greater than 1 electron volt. This configuration forms a potential well 112 between the first membrane 106 and the third membrane 110.

[0023] Potential well 112 is configured at the conduction band E of the second membrane 108 c Electrons are trapped in the substrate. The first film 106 and the third film 110 surrounding the second film 108 isolate the trapped electrons from the semiconductor material of the substrate 102 or the DTI core 104. Electrons escape from the conduction band of the second film 108. c To enter the substrate 102 or the DTI core 104, electrons must be excited to a first band energy 116 of the first film 106 or a third band energy 120 of the third film 110, respectively. The difference between the second band energy 118 and the first band energy 116 and the third band energy 120 reduces the number of electrons escaping the potential well. Furthermore, the energy difference between the second film and the first film 106 and the third band energy 110 reduces the likelihood of electrons escaping the potential well without an external energy source acting on the DTI structure 103. The trapped electrons repel electrons from the interface between the DTI structure 103 and the substrate 102, thereby forming an enhanced depletion region at the interface. The interaction between electrons and charge trapping at the interface is a major contributor to the dark current between isolated semiconductor devices. The enhancement of the depletion region reduces the amount of dark current that can travel around the DTI structure 103 and between semiconductor devices.

[0024] like FIG. 1C As shown in the cross-sectional view 100c, multiple electrons 126 are trapped in the second membrane 108. This is due to the first band energy, the second band energy, and the third band energy (see...). FIG. 1BThe difference between 116, 118, and 120) prevents the plurality of electrons 126 from escaping via the first film 106 or the third film 110. The plurality of electrons 126 repel electrons from the interface 127 between the first film 106 and the substrate 102. This electron repulsion creates an enhanced depletion region 130 at the interface 127 between the substrate 102 and the DTI structure 103. The enhanced depletion region 130 is dominated by holes 128. In some embodiments where the first film 106 is silicon dioxide or contains silicon dioxide, the inherent negative charge of the first film 106 can further enhance the effect of the enhanced depletion region 130.

[0025] FIG. 2A , FIG. 2B and FIG. 2C Showing includes FIG. 1A to FIG. 1C Cross-sectional views 200a, 200b and top view 200c of the integrated device with DTI structure. FIG. 2A The sectional view 200a is along FIG. 2C It is intercepted by line A-A'.

[0026] like FIG. 2A As shown in cross-sectional view 200a, in some embodiments, the DTI structure 103 comprises multiple segments arranged in a grid pattern surrounding a plurality of pixels 204 arranged in an array within the substrate 102. The plurality of pixels 204 include photodetectors 202 located directly between the segments of the DTI structure 103. The plurality of pixels 204 further include a floating diffusion node 206 and a transfer transistor 208. The transfer transistor 208 is configured to activate a channel between the photodetector 202 and the floating diffusion node 206, allowing signals generated by the photodetector 202 to enter an interconnect structure 210 on a first surface 102a of the substrate 102. The interconnect structure 210 includes a plurality of contacts 212 arranged to guide electrical signals through an integrated device, wiring layers 214, and via layers 216. In some embodiments, the interconnect structure 210 connected to the transfer transistor 208 and the floating diffusion node 206 may be further connected to image processing circuitry that converts signals from the photodetector 202 into an image. In other embodiments, the interconnect structure 210 connected to the transfer transistor 208 and the floating diffusion node 206 can be further coupled to a security system, enabling information to be transmitted to another device in response to light illuminating the photodetector 202. In some embodiments, a plurality of color filters 218 are overlaid on the plurality of pixels 204. In a further embodiment, a plurality of lenses 220 are overlaid on the plurality of color filters 218.

[0027] like FIG. 2BAs shown in cross-sectional view 200b, in some embodiments, the DTI structure 103 is one or more segments extending between a plurality of semiconductor devices 222. In some embodiments, the plurality of semiconductor devices 222 may include transistor devices (e.g., planar FETs, FinFETs, gate-all-around (GAA) devices, etc.). In some embodiments, the plurality of semiconductor devices 222 includes source / drain terminals 224 located within a substrate 102. The source / drain terminals 224 of different semiconductor devices 222 are isolated by the DTI structure 103. The semiconductor devices 222 are coupled to an interconnect structure 210. The interconnect structure 210 includes a plurality of contacts 212, wiring steps 214, and via steps 216. Without a second film (see...), FIG. 1A In embodiment 108), the source / drain terminals 224 being brought close together and biased can induce a current between the semiconductor devices 222 around the DTI structure 103. However, having a first film and a third film (see...) FIG. 1A The second membrane between 106 and 110 (see FIG. 1A 108) and several captured electrons (see ... FIG. 1C The embodiment of (126) has an enhanced depletion region, which reduces the amount of current that can travel along the outer wall of the DTI structure.

[0028] like FIG. 2C As shown in top view 200c, in some embodiments, the DTI structure 103 is one or more segments surrounding the photodetectors 202 (shown in dashed lines) to isolate the photodetectors 202 from each other. In some embodiments, the DTI structure 103 forms a continuous loop surrounding one or more photodetectors 202. In some embodiments, the DTI structure does not extend to the outer surface of the substrate 102, and a top cover structure (not shown) extends from the upper surface of the DTI structure 103 to the outer surface of the substrate 102. The DTI structure 103 reduces both the amount of light that can pass through the substrate 102 between the photodetectors 202 and the amount of dark current that can travel between the pixels 204. The reduction in light traveling between the pixels 204 improves the performance and accuracy of the resulting image, and the reduction in dark current reduces the number of false reads and interference between the pixels 204, thereby further improving the quality of the resulting image.

[0029] FIG. 3A and FIG. 3B Cross-sectional view 300a and band diagram 300b show an alternative embodiment of a DTI structure including a fourth membrane extending between the DTI core and the third membrane.

[0030] like FIG. 3AAs shown in cross-sectional view 300a, in some embodiments, a fourth membrane 302 extends between the third membrane 110 and the DTI core 104, separating the third membrane 110 from the DTI core 104. The fourth membrane 302 may also be referred to as an additional membrane. The fourth membrane 302 is an insulator or includes an insulator, such as silicon dioxide. In some embodiments, the thickness of the fourth membrane 302 is equal to or greater than the thickness of the third membrane.

[0031] In some embodiments, the first membrane 106 has a first thickness within a range of 5 angstroms to 150 angstroms, 1 angstrom to 100 angstroms, 2 angstroms to 120 angstroms, or another similar range. In some embodiments, the second membrane 108 has a second thickness within a range of 5 angstroms to 150 angstroms, 1 angstrom to 100 angstroms, 2 angstroms to 120 angstroms, or another similar range. In some embodiments, the third membrane 110 has a third thickness within a range of 5 angstroms to 150 angstroms, 1 angstrom to 100 angstroms, 2 angstroms to 120 angstroms, or another similar range. In some embodiments, the first thickness and the third thickness are substantially equal.

[0032] like FIG. 3B As shown in band structure diagram 300b, the fourth membrane 302 has a conduction band E c E c A fourth band energy 304 is at least 1 electron volt greater than the second band energy 118 of the second membrane 108. In some embodiments, the fourth band energy 304 is greater than the third band energy 120. In other embodiments, the fourth band energy 304 is equal to or less than the third band energy 120. In some embodiments, the fourth membrane 302 is configured to serve as an additional barrier between the DTI core 104 and the potential well 112 in the second membrane 108 to further reduce the number of electrons escaping from the potential well 112.

[0033] In some embodiments, due to band bending, the conduction band E c The bending occurs between the first membrane 106, the second membrane 108, and the third membrane 110. In a further embodiment, the minimum value of the second band energy 118 is related to the conduction band E within the first membrane 106. c The difference between the local maxima is greater than 1 electron volt. Furthermore, the minimum value of the second band energy 118 differs from the conduction band energy E in both the third membrane 110 and the fourth membrane 302. c The difference between the local maxima is greater than 1 electron volt.

[0034] FIG. 4 to FIG. 10A series of cross-sectional views 400 to 1000 illustrate some embodiments of a method for forming a DTI structure having a first membrane, a second membrane, and a third membrane surrounding a DTI core, wherein the second membrane is a trapping membrane. Although FIG. 4 to FIG. 10 The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of these actions may be changed in other embodiments, and the disclosed method may also be applied to other structures. In other embodiments, some of the actions shown and / or described may be omitted in whole or in part.

[0035] like FIG. 4 As shown in the cross-sectional view 400, a first mask layer 402 is formed on the substrate 102. The first mask layer 402 may be formed, for example, using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on process, etc. The first mask layer 402 is then patterned to expose the substrate 102 corresponding to the DTI structure to be formed thereafter (see...). FIG. 1A Part of 103). In some embodiments, the first mask layer 402 is photoresist or contains photoresist and / or is patterned using photolithography.

[0036] After patterning the first mask layer 402, a first etching process 404 is performed on the substrate 102 while the first mask layer 402 is positioned. The first etching process 404 removes the portion of the substrate exposed by the first mask layer 402, thereby forming a first opening 406 within the substrate 102. In some embodiments, the first opening is a series of segments depicted as an array on the substrate. In other embodiments, the first opening is a series of segments surrounding a portion of the substrate 102. In some embodiments, the first etching process 404 is a dry etching process. In some embodiments, the first opening 406 extends between 2 micrometers and 4 micrometers in the substrate 102, between 3 micrometers and 6 micrometers in the substrate 102, between 2 micrometers and 5 micrometers in the substrate 102, or another similar range. In some embodiments, the substrate 102 extends an additional 3 micrometers to 5 micrometers below the first opening 406, an additional 4 micrometers to 6 micrometers below the first opening 406, an additional 3 micrometers to 6 micrometers below the first opening 406, or another similar range. In some embodiments, the first opening 406 has a circular bottom surface. The circular bottom surface allows for a nearly uniform thickness of the subsequently deposited conformal layer, which maintains the surrounding DTI structure (see [link]). FIG. 1C The enhanced depletion region of 103) (see 103) FIG. 1C The thickness is 130.

[0037] like FIG. 5 As shown in the cross-sectional view 500, the first mask layer 402 is removed. The removal of the first mask layer 402 exposes the second side 102b of the substrate 102. In some embodiments, one or more of plasma etching, wet etching, ashing, etc., are used to remove the first mask layer 402.

[0038] like FIG. 6 As shown in the cross-sectional view 600, a first conformal film 602 is formed on the second side 102b of the substrate 102. In some embodiments, the first conformal film 602 is a first material or contains a first material, such as alumina (Al2O3), silicon dioxide (SiO2), etc. In some embodiments, the first conformal film 602 is formed using CVD, PVD, ALD, etc. The first conformal film 602 covers the second side 102b of the substrate 102 and extends along the inner sidewall and bottom surface of the first opening 406. The first conformal film 602 is conformal to the bottom surface of the first opening 406 such that the first conformal film 602 has a circular cross-section within the first opening 406. In some embodiments, the thickness of the first conformal film 602 along the inner sidewall is substantially equal to the thickness of the first conformal film 602 extending along the bottom surface of the first opening 406. In some embodiments where the first conformal film 602 contains silicon dioxide, the first conformal film may have an inherent negative charge.

[0039] like FIG. 7 As shown in the cross-sectional view 700, a second conformal film 702 is formed on top of a first conformal film 602. In some embodiments, the second conformal film 702 is a second material or contains a second material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon nitride (Si3N4), etc. The first material of the first conformal film 602 and the second material of the second conformal film 702 are selected as insulators, wherein the first material has a conduction band with an energy at least 1 electron volt lower than the conduction band energy of the second material. In some embodiments, the second conformal film 702 is formed using CVD, PVD, ALD, etc. The second conformal film 702 is overlaid on a second side 102b of the substrate 102 and extends within the first opening 406 along the inner sidewall and upper surface of the first conformal film 602. In some embodiments, since the first opening 406 has a rounded end, the thickness of the second conformal membrane 702 along the inner sidewall of the first conformal membrane 602 is substantially equal to the thickness of the second conformal membrane 702 extending between the inner sidewalls of the first conformal membrane 602.

[0040] like FIG. 8As shown in the cross-sectional view 800, a third conformal film 802 is formed on the second conformal film 702. In some embodiments, the third conformal film 802 is a third material or contains a third material, such as alumina (Al2O3), silicon dioxide (SiO2), etc. The third material of the third conformal film 802 is selected as an insulator having a conduction band having a third band energy at least 1 electron volt greater than the band energy of the second material. In some embodiments, the third conformal film 802 is formed using CVD, PVD, ALD, etc. The third conformal film 802 is deposited on the second side 102b of the substrate 102 and extends within the first opening 406 along the inner sidewall and upper surface of the second conformal film 702. In some embodiments, due to the circular end of the first opening 406 and the conformal deposition process, the thickness of the third conformal film 802 along the inner sidewall of the second conformal film 702 is substantially equal to the thickness of the third conformal film 802 extending between the inner sidewalls of the second conformal film 702.

[0041] like FIG. 9 As shown in the cross-sectional view 900, a conformal filling layer 902 is formed on the third conformal film 802. In some embodiments, the conformal filling layer 902 is a semiconductor material or contains a semiconductor material, such as polysilicon. In some embodiments, the conformal filling layer 902 is formed using CVD, PVD, ALD, etc. The conformal filling layer 902 covers the second side 102b of the substrate 102 and extends along the inner sidewall and upper surface of the third conformal film 802, thereby filling the first opening 406 (shown in dashed lines).

[0042] like FIG. 10 As shown in the cross-sectional view 1000, a planarization process 1002 is performed (e.g., chemical mechanical planarization (CMP) process). Planarization process 1002 removes the first conformal film (see...). FIG. 9 Part of 602), the second conformal membrane (see 602) FIG. 9 Part of 702), the third conformal membrane (see 702) FIG. 9 The 802) portion and the conformal fill layer (see 802) FIG. 9 Part 902). After planarization process 1002, the first film 106, the second film 108, the third film 110 and the DTI core 104 are retained in the substrate 102.

[0043] In some embodiments, during the formation of a conformal fill layer (see...) FIG. 9Before or after the planarization process 1002 (902), a process is performed to trap electrons within the second film 108. In some embodiments, the process may be a bias application process, wherein a bias is applied to the substrate 102 such that electrons outside the second film 108 gain sufficient energy to overcome the charge energy of the first film 106 or the third film 110. In other embodiments, the process may be a thermal process, wherein heat is applied to the substrate 102 or the DTI core 104 such that electrons outside the second film 108 gain sufficient energy to overcome the charge energy of the first film 106 or the third film 110.

[0044] FIG. 11 A flowchart 1100 illustrates some embodiments of a method for forming a DTI structure having a first membrane, a second membrane, and a third membrane surrounding a DTI core, wherein the second membrane is a trapping membrane. Although the methods shown and / or described herein are depicted as a series of actions or events, it should be understood that this disclosure is not limited to the shown order or actions. Therefore, in some embodiments, the actions may be performed in a different order than shown and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0045] At operation 1102, a first opening with a rounded end is formed within the substrate. For example, an example illustrating this step can be found in... FIG. 4 middle.

[0046] At operation 1104, a first conformal film is formed within the first opening. For example, an example of a diagram illustrating this step can be found in... FIG. 6 middle.

[0047] At operation 1106, a second conformal membrane is formed within the first opening to line the inner wall of the first conformal membrane. For example, an example of a diagram illustrating this step can be found in... FIG. 7 middle.

[0048] At operation 1108, a third conformal membrane is formed within the first opening to line the inner wall of the second conformal membrane. For example, an example of a diagram illustrating this step can be found in... FIG. 8 middle.

[0049] At operation 1110, a conformal filling layer is formed within the first opening, the conformal filling layer filling the first opening. For example, an example of a diagram illustrating this step can be found in... FIG. 9 middle.

[0050] At operation 1112, the portions of the first conformal film, the second conformal film, the third conformal film, and the conformal filler layer extending beyond the substrate are removed, such that the first, second, and third films surround the DTI core. For example, an example of a diagram illustrating this step can be found in... FIG. 10 middle.

[0051] Some embodiments relate to a deep trench isolation (DTI) structure, comprising: a DTI core extending into a substrate; a first film surrounding the DTI core and having a first material having a first conduction band at a first band energy; a second film located between the first film and the DTI core, the second film having a second material having a second conduction band at a second band energy lower than the first band energy; and a third film located between the second film and the DTI core, the third film having a third material having a third conduction band at a third band energy higher than the second band energy.

[0052] In some embodiments, the difference between the first band energy and the second band energy is greater than 1 electron volt, and the difference between the second band energy and the third band energy is greater than 1 electron volt. In some embodiments, the difference between the first band energy, the second band energy, and the third band energy causes a potential well to form between the first film and the second film. In some embodiments, the deep trench isolation structure further includes a circular distal end within the substrate, and wherein the first film has a first thickness along the sidewall of the deep trench isolation structure and a second thickness extending across the circular distal end, and wherein the first thickness and the second thickness are substantially equal. In some embodiments, the first material and the third material are the same material. In some embodiments, the deep trench isolation structure further includes a fourth film located between the third film and the deep trench isolation core, the fourth film comprising silicon dioxide.

[0053] Other embodiments relate to an integrated device including: a plurality of photodetectors located within a substrate; a plurality of floating diffusion nodes arranged in an array on a first side of the substrate; an interconnect structure coupled to the plurality of floating diffusion nodes; and a deep trench isolation (DTI) core located on a second side of the substrate, wherein the DTI core is spaced apart from the plurality of photodetectors, the plurality of floating diffusion nodes, and the interconnect structure by a first film, a second film, and a trapping film extending between the first film and the second film.

[0054] In some embodiments, the trapping membrane comprises a first material, and the first and second membranes each comprise a second material, wherein the first material has a first conduction band at a first energy level, and the second material has a second conduction band having a second energy level greater than the first energy level, and wherein the difference between the first and second energy levels is greater than 1 eV. In some embodiments, the first material comprises silicon nitride and the second material comprises aluminum oxide. In some embodiments, the integrated device further comprises an additional membrane located between the deep trench isolation core and the first membrane, wherein the additional membrane comprises a third material having a third conduction band at a third energy level, and wherein the difference between the first and third energy levels is greater than 1 eV. In some embodiments, the deep trench isolation core extends in a grid pattern surrounding the plurality of photodetectors, and wherein the plurality of photodetectors are isolated from each other by the deep trench isolation core. In some embodiments, the first membrane, the trapping membrane, and the second membrane are configured to trap electrons within the trapping membrane. In some embodiments, the first membrane, the trapping membrane, and the second membrane are configured to reduce the amount of dark current traveling between the plurality of photodetectors based on the electrons trapped in the trapping membrane.

[0055] Other embodiments relate to a method of forming a deep trench isolation (DTI) structure, including: forming a first opening having a circular end in a substrate; forming a first conformal film in the first opening; forming a second conformal film in the first opening to pave the inner sidewalls of the first conformal film; forming a third conformal film in the first opening to pave the inner sidewalls of the second conformal film; forming a conformal fill layer in the first opening to fill the first opening; and removing portions of the first conformal film, the second conformal film, the third conformal film, and the conformal fill layer extending out of the substrate, such that the first film, the second film, and the third film surround portions of the DTI core.

[0056] In some embodiments, the method further includes performing a process configured to draw electrons into the second film, wherein the process is a thermal treatment or a bias treatment. In some embodiments, the second conformal film comprises a first material, and the first conformal film and the third conformal film comprise materials from a second group of materials, wherein the second group of materials includes materials having conduction bands with band energies at least 1 electron volt greater than the band energy of the first material. In some embodiments, the conformal fill layer comprises a semiconductor material. In some embodiments, the method further includes forming a fourth conformal film after forming the third conformal film, the fourth conformal film extending into the first opening and surrounding the inner sidewall of the third conformal film. In some embodiments, the fourth conformal film comprises silicon dioxide. In some embodiments, forming the first conformal film comprises a deposition process, wherein the first conformal film has a circular end conforming to the circular end of the first opening.

[0057] It should be understood that the terms "first," "second," "third," etc., used in this written description and in the following claims are merely general identifiers for ease of explanation to distinguish different components of a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of the components and are not intended to illustrate corresponding components in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" illustrated in connection with the first figure may not necessarily correspond to "first dielectric layer" illustrated in connection with another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this utility model, and are not intended to limit it. Although the embodiments of this utility model have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A deep trench isolation structure, comprising: comprising: a deep trench isolation core extending into a substrate; a first film surrounding the deep trench isolation core, the first film having a first conduction band at a first band energy; a second film between the first film and the deep trench isolation core, the second film having a second conduction band at a second band energy less than the first band energy; and a third film between the second film and the deep trench isolation core, the third film having a third conduction band at a third band energy greater than the second band energy.

2. The deep trench isolation structure of claim 1, wherein, wherein a difference between the first band energy and the second band energy is greater than 1 electron volt, and a difference between the second band energy and the third band energy is greater than 1 electron volt.

3. The deep trench isolation structure of claim 1, wherein, wherein a difference between the first band energy, the second band energy, and the third band energy is such that a potential well is formed between the first film and the second film.

4. The deep trench isolation structure of claim 3, wherein, wherein the deep trench isolation structure further comprises a rounded distal end within the substrate, and wherein the first film has a first thickness along a sidewall of the deep trench isolation structure and a second thickness extending across the rounded distal end, and wherein the first thickness and the second thickness are substantially equal.

5. The deep trench isolation structure of claim 1, wherein, wherein the first film and the third film are of the same material.

6. The deep trench isolation structure of claim 1, wherein, further comprising a fourth film between the third film and the deep trench isolation core.

7. An integrated device, characterized by comprising: a plurality of photodetectors within a substrate; a plurality of floating diffusion nodes arranged in an array on a first side of the substrate; interconnect structures coupled to the plurality of floating diffusion nodes; and a deep trench isolation core on a second side of the substrate, wherein the deep trench isolation core is spaced apart from the plurality of photodetectors, the plurality of floating diffusion nodes, and the interconnect structures by a first film, a second film, and a trapping film extending between the first film and the second film.

8. The integrated device of claim 7, wherein, wherein the trapping film has a first conduction band at a first band energy, and the first film and the second film have a second conduction band at a second band energy greater than the first band energy, and wherein a difference between the first band energy and the second band energy is greater than 1 electron volt.

9. The integrated device of claim 7, wherein, wherein the deep trench isolation core extends in a grid pattern surrounding the plurality of photodetectors, and wherein the plurality of photodetectors are isolated from one another by the deep trench isolation core.

10. The integrated device of claim 9, wherein, wherein the first film, the trapping film, and the second film are configured to trap electrons within the trapping film.

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