Semiconductor device and power conversion device

Abstract

The utility model provides a structure, which can ensure the layout freedom degree of a driving wire through enabling the area of a semiconductor device capable of being connected with the driving wire to be larger than the prior art, thereby realizing the miniaturization of the semiconductor device. In a semiconductor device according to the present disclosure, an emitter driving wiring connected to an emitter control terminal is directly connected to a wiring board. In addition, an emitter drive wiring connected to the emitter control terminal is connected via the circuit board. In addition, a power conversion device related to the semiconductor device is also obtained.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device in which a wiring board is joined to a semiconductor element. BACKGROUND

[0002] In the related art, a lead wire is routed between a wiring pattern and an upper surface electrode (emitter electrode, gate electrode) of an IGBT. (For example, Patent Document 1)

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-12726 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, in the related art, since a drive wiring needs to be formed in a narrow region on a semiconductor element, there is a problem in that the layout degree of freedom of the drive wiring is low, and the semiconductor device is difficult to be downsized.

[0008] The present disclosure was completed in order to solve the above problem, and an object thereof is to provide a structure capable of ensuring the layout degree of freedom of a drive wiring and achieving downsizing of a semiconductor device by making a region in which the drive wiring of the semiconductor device is connectable larger than ever before.

[0009] TECHNICAL SOLUTION TO THE PROBLEM

[0010] The semiconductor device according to the present disclosure includes: a circuit pattern; a semiconductor element provided in the circuit pattern and having a gate electrode and an emitter electrode; a wiring board provided on a side opposite to the circuit pattern of the semiconductor element and electrically connected to the emitter electrode; a gate control terminal and an emitter control terminal that control the semiconductor element; a first drive wiring connected to the gate control terminal and the gate electrode; and a second drive wiring connected to the emitter control terminal and the wiring board.

[0011] Further, a semiconductor device according to the present disclosure includes a circuit pattern, a semiconductor element provided in the circuit pattern and having a gate electrode and an emitter electrode, a wiring board provided on a side opposite to the semiconductor element from the circuit pattern and electrically connected to the emitter electrode, a gate control terminal and an emitter control terminal that control the semiconductor element, a tape carrier board provided on a side opposite to the semiconductor element from the wiring board, a first drive wiring connected to the gate control terminal and the gate electrode via the tape carrier board, and a second drive wiring connected to the emitter control terminal and the wiring board via the tape carrier board.

[0012] Further, a semiconductor device according to the present disclosure includes a circuit pattern, a semiconductor element provided in the circuit pattern and having a gate electrode and an emitter electrode, a wiring board provided on a side opposite to the semiconductor element from the circuit pattern and electrically connected to the emitter electrode, a gate control terminal and an emitter control terminal that control the semiconductor element, a tape carrier board provided on a side opposite to the semiconductor element from the wiring board, a first drive wiring connected to the gate control terminal and the gate electrode via the tape carrier board, and a second drive wiring connected to the emitter control terminal and the wiring board via the tape carrier board.

[0013] Utility model effect

[0014] According to the semiconductor device of the present disclosure, the degree of freedom of the layout of the drive wiring can be improved, and the semiconductor device can be downsized. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a side view schematic diagram illustrating a semiconductor device of Embodiment 1 of the present disclosure.

[0016] Figure 2 is a plan view schematic diagram illustrating a semiconductor device of Embodiment 1 of the present disclosure.

[0017] Figure 3 is a plan view schematic diagram illustrating a semiconductor device of Embodiment 1 of the present disclosure.

[0018] Figure 4 is a side view schematic diagram illustrating a semiconductor device of Embodiment 2 of the present disclosure.

[0019] Figure 5 is a plan view schematic diagram illustrating a semiconductor device of Embodiment 2 of the present disclosure.

[0020] Figure 6is a side view diagram schematically showing a semiconductor device according to Embodiment 3 of the present disclosure.

[0021] Figure 7 is a plan view diagram schematically showing a semiconductor device according to Embodiment 3 of the present disclosure.

[0022] Figure 8 is a plan view diagram schematically showing a semiconductor device according to Embodiment 3 of the present disclosure.

[0023] Figure 9 is a schematic diagram showing a power conversion system according to Embodiment 4 of the present disclosure. DETAILED DESCRIPTION

[0024] Embodiment 1.

[0025] With Figure 1 , Figure 2 , Figure 3 Embodiment 1 of the semiconductor device will be described. Figure 1 is a diagram schematically showing a state in which the semiconductor device of Embodiment 1 is viewed from the side. In addition, the side refers to a vertical direction perpendicular to a stacking direction of each structure described later.

[0026] As Figure 1 shown, the semiconductor device 1 according to the present embodiment includes a cooler 2, a bonding material 3 provided on an upper surface of the cooler 2, a conductor foil 4 provided on an upper surface of the bonding material 3, an insulating layer 5 provided on an upper surface of the conductor foil 4, a circuit pattern 6 provided on an upper surface of the insulating layer 5, a plurality of bonding materials 3 provided on an upper surface of the circuit pattern 6, a first semiconductor element 7 and a second semiconductor element 8 provided on upper surfaces of the plurality of bonding materials 3, respectively, a plurality of bonding materials 3 provided on upper surfaces of the first semiconductor element 7 and the second semiconductor element 8, respectively, and a wiring board 9 provided so as to cover the upper surfaces of the plurality of bonding materials 3.

[0027] That is, the upper surfaces and the lower surfaces of the first semiconductor element 7 and the second semiconductor element 8 are sandwiched by the bonding material 3. In addition, the upper surface indicates a surface on which the bonding material 3 and the like structure are provided with the cooler 2 as a reference. A surface different from the upper surface, that is, an opposite side of the upper surface is referred to as the lower surface. The following description is the same.

[0028] In addition, the semiconductor device 1 according to the present embodiment includes the bonding material 3 provided on the upper surface of the circuit pattern 6 at a position adjacent to the first semiconductor element 7 and the second semiconductor element 8, and an output terminal 10 provided on an upper surface of the bonding material 3.

[0029] In addition, the semiconductor device 1 according to the present embodiment includes a gate control terminal 11 and an emitter control terminal 12 provided above the output terminal 10 when the semiconductor device 1 is viewed from the side.

[0030] Further, the semiconductor device 1 according to the present embodiment includes a first drive wiring 13 connecting the gate control terminal 11 and the gate electrode 15 of the first semiconductor element 7; and a second drive wiring 14 connecting the emitter control terminal 12 and the wiring board 9.

[0031] The first semiconductor element 7 is, for example, an IGBT (Insulated Gate Bipolar Transistor), and the second semiconductor element is, for example, a diode. Further, the cooler 2, the bonding material 3, the conductor foil 4, the insulating layer 5, the circuit pattern 6, the bonding material 3, the first semiconductor element 7 or the second semiconductor element 8, the bonding material 3, and the wiring board 9 have a structure in which they are stacked in this order. In Figure 1 In the present embodiment, the wiring board 9 is disposed on the opposite side of the circuit pattern 6 when viewed from the semiconductor element. Further, in the case of simply referring to the semiconductor element, at least one of the first semiconductor element 7 and the second semiconductor element 8 is meant.

[0032] The circuit pattern 6 and the first semiconductor element 7 and the second semiconductor element 8, and the first semiconductor element 7 and the second semiconductor element 8 and the wiring board 9 are electrically connected by the bonding material 3 such as solder or silver. Further, the cooler 2 and the bonding material 3 and the conductor foil 4 formed on the upper surface of the cooler 2 are insulated from the circuit pattern 6 and the structure formed on the upper surface of the circuit pattern 6 by the insulating layer 5.

[0033] The circuit pattern 6 is formed of copper having a small conductor resistance. The gate electrode 15 and the emitter electrode 16 are formed on the upper surface of the first semiconductor element 7, that is, the surface of the first semiconductor element 7 on the wiring board 9 side. In the upper surface of the first semiconductor element 7, the region other than the gate electrode 15 is the emitter electrode 16.

[0034] The first electrode is formed on the upper surface of the second semiconductor element 8, that is, the surface of the second semiconductor element 8 on the wiring board 9 side. Further, the second electrode is formed on the lower surface of the second semiconductor element 8, that is, the surface of the second semiconductor element 8 on the circuit pattern 6 side. However, the first electrode and the second electrode are electrodes having different polarities from each other.

[0035] The first drive wiring 13 is a gate drive wiring and is connected to the gate control terminal 11 and the gate electrode 15 of the first semiconductor element 7. The second drive wiring 14 is an emitter drive wiring and is connected to the emitter control terminal 12 and the wiring board 9. Further, the second drive wiring 14 is not limited to being connected to the surface of the wiring board 9, and can be connected to, for example, the end portion of the wiring board 9. By connecting the second drive wiring 14 to an arbitrary portion of the wiring board 9, the wiring degree of freedom of the emitter drive wiring can be ensured.

[0036] like Figure 1 As shown, the conductor foil 4, insulating layer 5, circuit pattern 6, first semiconductor element 7, and second semiconductor element 8 are all sealed with sealing material 18 such as epoxy resin. A portion of the bonding material 3, wiring board 9, output terminal 10, gate control terminal 11, and emitter control terminal 12 sandwiched between the cooler 2 and conductor foil 4 is also sealed. Figure 1 As shown, when viewed from the side, the sealing material 18 is a cuboid, but not limited to a cuboid, and can be any shape.

[0037] This embodiment illustrates a transfer-molded semiconductor device obtained by placing a component or structure other than the sealing material 18 in a mold, and then allowing the sealing material 18 to flow into the mold. However, the scope of this invention is not limited to transfer molding. For example, it can be applied to a housing-type semiconductor device obtained by placing a component or structure other than the sealing material 18 inside a housing, and then allowing the sealing material 18 to flow into the housing.

[0038] Figure 2 This is a schematic diagram showing the upper surface of the semiconductor device according to Embodiment 1. Figure 2 In, with Figure 1 The same labels indicate the same structure. Figure 2 In the text, sealing material 18 is omitted. Additionally, in... Figure 2 In the diagram, the bonding material 3, the first semiconductor element 7, and the second semiconductor element 8, which are disposed below the wiring board 9, are represented by dashed lines.

[0039] Figure 2 The diagram shows four semiconductor elements bonded to wiring board 9. Of the four semiconductor elements, two are arranged parallel to wiring board 9 in the extending direction, and two are arranged parallel to wiring board 9 in a direction perpendicular to the extending direction. That is, two elements are arranged in the longitudinal direction and two in the transverse direction on the surface parallel to wiring board 9.

[0040] Of the four semiconductor elements, the two semiconductor elements disposed on the side opposite to the direction in which the wiring board 9 is partially exposed from the sealing material 18 are first semiconductor elements 7, and the two semiconductor elements disposed on the side in which the wiring board 9 is partially exposed from the sealing material 18 are second semiconductor elements 8. The two first semiconductor elements are connected in parallel. Figure 2 As shown, the first semiconductor element 7 includes a gate electrode 15 and an emitter electrode 16 on the wiring board 9 side.

[0041] For example, the gate electrode 15 has a rectangular shape, and as described above, the area on the upper surface of the first semiconductor element 7 other than the gate electrode 15 is the emitter electrode 16. Furthermore, the gate electrode 15 is not limited to a rectangular shape; it can be any shape, including circular or curved shapes.

[0042] Furthermore, multiple semiconductor elements can be electrically connected to the wiring board 9, and the number of connected semiconductor elements is not limited to four. The wiring board 9 is electrically bonded to the emitter electrode 16 such that the emitter electrode 16 of all the first semiconductor elements 7 is covered by the bonding material 3. The wiring board 9 is electrically bonded such that it covers the first electrode disposed on the upper surface of all the second semiconductor elements 8. The wiring board 9 connected to the emitter electrode 16 of the first semiconductor elements 7 is the same board as the wiring board 9 connected to the first electrode of the second semiconductor elements 8.

[0043] Additionally, the wiring board 9 can be configured to cover the entire emitter electrode 16 of the first semiconductor element 7 and the electrodes of the second semiconductor element 8, or it can be configured as follows: Figure 2 The image shows a portion of the emitter electrode 16 covering the first semiconductor element 7.

[0044] like Figure 2 As shown, the first driving wiring 13 is connected to the gate electrode 15 and the gate control terminal 11 formed in the first semiconductor element 7. In the case of multiple semiconductor elements, the first driving wiring 13 is connected to the gate electrode 15 and the gate control terminal 11 of each of the multiple first semiconductor elements 7. Figure 2 As shown, the semiconductor device 1 according to Embodiment 1 includes at least two first driving wirings 13. Furthermore, the number of first driving wirings 13 can be multiple, for example, three or four.

[0045] The second drive wiring 14 is connected to the emitter control terminal 12 and the wiring board 9. Alternatively, the second drive wiring 14 can be connected to the emitter control terminal 12 and the emitter electrode 16.

[0046] Furthermore, although the wiring of the semiconductor device shown in the figure is 1-in-1, wiring other than 1-in-1, such as 2-in-1 or 6-in-1, can also be used.

[0047] like Figure 3 As shown, the output terminal 10, the gate control terminal 11, and the emitter control terminal 12 are arranged in a direction opposite to the direction in which the wiring board 9 is partially exposed from the sealing material 18. Furthermore, when the semiconductor device 1 is viewed from the top surface, the gate control terminal 11, the emitter control terminal 12, and the output terminal 10 are arranged sequentially in a direction perpendicular to the extending direction of the wiring board 9 on a surface parallel to the wiring board 9.

[0048] Figure 2 This is a schematic diagram showing the upper surface involved in a variation of the semiconductor device according to Embodiment 1, and shows that it is configured to be... Figure 3 Semiconductor devices with different wiring configurations. In Figure 1 In, with Figure 2 andFigure 3 The same labels indicate the same structure. Additionally, in Figure 4 The sealing material 18 is omitted.

[0049] The first driving wiring 13 is formed to directly connect the gate electrodes 15 of a plurality of first semiconductor elements 7 connected in parallel. That is, the first driving wiring 13 is connected to the gate electrode 15 formed in the first semiconductor element 7 and the gate control terminal 11 via another first semiconductor element 7 connected in parallel.

[0050] In the semiconductor device described in this embodiment, the first semiconductor element 7 and the second semiconductor element 8 can be replaced with an RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor). Alternatively, switching elements other than RC-IGBTs can be used as semiconductor elements.

[0051] By using RC-IGBTs, the number of chips can be reduced, thereby enabling further miniaturization of semiconductor devices.

[0052] Furthermore, in this embodiment, SiC (silicon carbide) can be used as the first semiconductor element 7. By using low-loss SiC, miniaturization of the semiconductor device can be achieved. In addition, by using the wiring board 9 shown in this embodiment, low inductance can be achieved, thereby reducing losses in the high-frequency operating region where the effects of SiC are utilized, and improving the lifespan of the semiconductor device.

[0053] According to the semiconductor device of this embodiment, by connecting the second driving wiring 14 to the upper surface of the wiring board 9, the number of dot positions of the second driving wiring 14 is greatly increased, thereby improving the layout freedom of the driving wiring and enabling miniaturization of the semiconductor device.

[0054] Furthermore, according to the semiconductor device of this embodiment, the structure of forming a wiring board on the upper surface of the semiconductor element reduces the conductive wiring that should be formed in the form of a circuit pattern on the lower surface of the semiconductor element, thus contributing to the miniaturization of the semiconductor device. In addition, compared to the conventional method, inductance can be reduced and the heat dissipation performance of the semiconductor element can be improved.

[0055] Implementation method 2.

[0056] use Figure 5 , Figure 4 The semiconductor device of Embodiment 2 will be described below. Descriptions of structures identical to those in Embodiment 1 are omitted. Furthermore, in Figure 5 and Figures 1-3 In, with Figure 4 The same label indicates the same or equivalent parts.

[0057] Figure 4 This is a schematic view of the semiconductor device according to Embodiment 2, viewed from the side. Compared to the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 2 has a circuit board 20 provided on the upper surface of the wiring board 9. That is, when viewed from the wiring board 9, the circuit board 20 is provided on the opposite side of the semiconductor element. Figure 5 As shown, the circuit board 20 has multiple different conductor portions on its upper surface. Furthermore, the circuit board 20 and the wiring board 9 are insulated from each other.

[0058] The first driving wiring 13 connects the gate control terminal 11 to the gate electrode 15 of the first semiconductor element 7 via the first conductor portion of the circuit board 20. The second driving wiring 14 connects the emitter control terminal 12 to the wiring board 9 via the second conductor portion of the circuit board 20. That is, the first driving wiring 13 and the second driving wiring 14 are electrically insulated.

[0059] Figure 2 This is a schematic diagram showing the upper surface of the semiconductor device according to Embodiment 2. A circuit board 20 is disposed on the upper surface of the wiring board 9. Figure 5 The above, Figure 5 In the middle, two first semiconductor elements 7 and two second semiconductor elements 8 are respectively set.

[0060] The first driving wiring 13 connects the gate control terminal 11 to the gate electrode 15 of the first semiconductor element 7 via the first conductor portion of the circuit board 20. That is, as... Figure 5 As shown, when multiple semiconductor elements are provided, the first driving wiring 13 is connected to the gate electrode 15 of each of the multiple first semiconductor elements 7.

[0061] like Figure 5 As shown, the semiconductor device 1 according to Embodiment 2 includes at least three first driving wirings 13. Furthermore, the number of first driving wirings 13 can be multiple, for example, four or five. Additionally, the first driving wirings 13 can be formed to directly connect between the gate electrodes 15 of a plurality of first semiconductor elements 7 connected in parallel.

[0062] In other words, Figure 6 In this circuit, although the two first driving wirings are connected to the first semiconductor element 7 connected in parallel from the first conductor portion of the circuit board 20, the first driving wiring of either one can be omitted. The gate electrode 15 of the first semiconductor element 7 on the side where the first driving wiring 13 is omitted can be connected to the gate electrode 15 of the other first semiconductor element 7.

[0063] The second drive wiring 14 is connected to the emitter control terminal 12 and the wiring board 9 via the circuit board 20. Alternatively, the second drive wiring 14 can be connected to the emitter control terminal 12 and the emitter electrode 16 via the second conductor portion of the circuit board 20.

[0064] According to the semiconductor device of Embodiment 2, compared with the semiconductor device of Embodiment 1, the wiring freedom of the driving wiring is increased, thereby achieving miniaturization of the semiconductor device. Furthermore, when multiple semiconductor elements are arranged on the upper surface of the circuit pattern 6, heat generated from each semiconductor element during driving can cause interference, leading to increased internal temperature of the semiconductor device. However, by adopting this structure, the layout freedom of the semiconductor elements can be increased, allowing for a longer distance between the semiconductor elements. This prevents the semiconductor device from overheating, thereby improving its lifespan.

[0065] Implementation method 3.

[0066] use Figure 7 , Figure 8 , Figure 6 The semiconductor device of Embodiment 3 will be described below. Descriptions of structures identical to those in Embodiment 1 are omitted. Furthermore, in Figure 7 , Figure 8 and Figures 1-5 In, with Figure 6 The same label indicates the same or equivalent parts.

[0067] Figure 7 This is a schematic view showing a side view of the semiconductor device according to Embodiment 3. In the semiconductor device of Embodiment 3, compared to the semiconductor device of Embodiment 2, the circuit board 20 is disposed on the upper surface of the circuit pattern 6 instead of the upper surface of the wiring board 9. That is, when viewed from the circuit pattern 6, the circuit board 20 is disposed on the same side as the semiconductor element. The structure of the circuit board is the same as that of Embodiment 2. The first driving wiring 13 connects the gate control terminal 11 to the gate electrode 15 of the first semiconductor element 7 via the first conductor portion of the circuit board 20. The second driving wiring 14 connects the emitter control terminal 12 to the emitter electrode 16 of the second semiconductor element 8 via the second conductor portion of the circuit board 20.

[0068] Figure 7 This is a schematic diagram showing the upper surface of the semiconductor device according to Embodiment 3. The first driving wiring 13 connects the gate control terminal 11 to the gate electrode 15 of the first semiconductor element 7 via a first conductor portion of the circuit board 20. In the case of multiple semiconductor elements, the first driving wiring 13 connects to the gate electrode 15 and the gate control terminal 11 of each of the multiple first semiconductor elements 7. Figure 8As shown, the semiconductor device 1 according to Embodiment 3 includes at least three first driving wirings 13. Furthermore, the number of first driving wirings 13 can be multiple, for example, four or five.

[0069] The second driving wiring 14 connects the emitter control terminal 12 to the emitter electrode 16 of the second semiconductor element 8 via the circuit board 20. The semiconductor device 1 of Embodiment 3 includes at least two second driving wirings 14. Additionally, the number of first driving wirings 13 can be multiple, for example, three or four. Furthermore, the second driving wirings 14 are connected to the emitter control terminal 12 and the wiring board 9 via the second conductor portion of the circuit board 20.

[0070] Figure 7 This is a schematic diagram showing the upper surface of the semiconductor device according to Embodiment 3, and shows that it is configured to be... Figure 9 Semiconductor devices with different wiring. Sealing material 18 omitted.

[0071] The first driving wiring 13 connects the gate control terminal 11 to the gate electrode 15 of the first semiconductor element 7 via the circuit board 20. The first driving wiring 13 is formed to directly connect the gate electrodes 15 of the plurality of first semiconductor elements 7 connected in parallel.

[0072] The second drive wiring 14 connects the emitter control terminal 12 to the wiring board 9 via the second conductor portion of the circuit board 20. Additionally, the second drive wiring 14 can be connected to both the emitter control terminal 12 and the emitter electrode 16.

[0073] According to this embodiment, by using the circuit board 20, the degree of freedom in wiring can be increased without reducing the area of ​​the circuit pattern 6, thereby improving the heat dissipation performance of the semiconductor device, and thus achieving increased lifespan and miniaturization. The increased degree of freedom in the wiring for driving enables miniaturization of the semiconductor device.

[0074] Implementation method 4.

[0075] In this embodiment, the semiconductor device described in embodiments 1 to 3 above is applied to a power conversion device. This invention is not limited to a specific power conversion device, but the application of this invention to a three-phase inverter is described. Figure 9 This is a block diagram illustrating the structure of a power conversion system using the power conversion device described in this embodiment.

[0076] Figure 9The power conversion system shown consists of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and provides DC power to the power conversion device 200. The power supply 100 can be configured in various forms; for example, it can be composed of a DC system, solar cells, a battery, or a rectifier circuit or AC / DC converter connected to an AC system. Furthermore, the power supply 100 can be configured using a DC / DC converter that converts DC power output from a DC system into a specified power.

[0077] The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, which converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. For example... ​ As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts direct current into alternating current and outputs it; a drive circuit 202 that outputs drive signals for driving the switching elements of the main conversion circuit 201; and a control circuit 203 that outputs control signals to the drive circuit 202 for controlling the drive circuit 202.

[0078] Load 300 is a three-phase motor driven by AC power supplied from power conversion device 200. Furthermore, load 300 is not limited to a specific application, but is a motor installed in various electrical equipment, such as motors used in hybrid or electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0079] The power conversion device 200 will now be described in detail. The main conversion circuit 201 includes switching elements and return diodes (not shown). The switching elements convert the DC power supplied from the power supply 100 into AC power, which is then supplied to the load 300. While the specific circuit structure of the main conversion circuit 201 varies, the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six return diodes connected in anti-parallel to each switching element.

[0080] The semiconductor device described in any one of embodiments 1 to 3 is applied to each of the switching elements of the main conversion circuit 201. Each pair of the six switching elements is connected in series to form an upper and lower arm, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0081] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and provides them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, based on the control signals from the control circuit 203 (described later), drive signals for turning the switching elements to the on state and drive signals for turning the switching elements to the off state are output to the control electrodes of each switching element.

[0082] When the switching element is held in the ON state, the drive signal is a voltage signal above the threshold voltage of the switching element (ON signal). When the switching element is held in the OFF state, the drive signal is a voltage signal below the threshold voltage of the switching element (OFF signal).

[0083] Control circuit 203 controls the switching elements of main conversion circuit 201 to provide the desired power to load 300. Specifically, the on-time (on-state) of each switching element of main conversion circuit 201 is calculated based on the power to be supplied to load 300. For example, main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the voltage to be output.

[0084] Then, a control command (control signal) is output to the drive circuit 202, causing an on signal to be output to the switching element that should be in the on state at each time, and an off signal to be output to the switching element that should be in the off state. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to the control signal.

[0085] In the power conversion device according to this embodiment, since the semiconductor device according to Embodiments 1 to 3 is used as the switching element of the main conversion circuit 201, that is, the semiconductor device according to Embodiments 1 to 3 is included, including: a main conversion circuit that converts and outputs the input power, a drive circuit that outputs a drive signal to the semiconductor device for driving the semiconductor device, and a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit, the miniaturization of the power conversion device can be realized.

[0086] In this embodiment, an example of applying the present invention to a two-level three-phase inverter has been described, but the present invention is not limited thereto and can be applied to various power conversion devices. Although a two-level power conversion device is used in this embodiment, it can also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the present invention can be applied to a single-phase inverter. Furthermore, when supplying power to DC loads, the present invention can be applied to a DC / DC converter or an AC / DC converter.

[0087] Furthermore, the power conversion device using this invention is not limited to the case where the load is an electric motor. For example, it can be used as a power supply device for electrical discharge machining and laser processing machines, or induction heating cookers and non-contact power supply systems. It can also be used as a power regulator for solar power generation systems and energy storage systems.

[0088] The descriptions in this disclosure are merely illustrative of embodiments of the present invention, and the embodiments may be appropriately combined without departing from the scope of this disclosure.

[0089] Label Explanation

[0090] 1 Semiconductor device, 6 Circuit pattern, 7 First semiconductor element, 8 Second semiconductor element, 9 Wiring board, 11 Gate control terminal, 12 Emitter control terminal, 13 First drive wiring, 14 Second drive wiring, 15 Gate electrode, 16 Emitter electrode, 20 Circuit board, 100 Power supply, 200 Power conversion device, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, 300 Load.

Claims

1. A semiconductor device, characterized in that, include: Circuit pattern; A semiconductor element disposed in the circuit pattern and having a gate electrode and an emitter electrode; A wiring board disposed on the side of the semiconductor element opposite to the circuit pattern and electrically connected to the emitter electrode; A gate control terminal and an emitter control terminal, which control the semiconductor element; The first driving wiring is directly connected to the gate control terminal and the gate electrode respectively; as well as The second driving wiring is connected to the emitter control terminal and the wiring board.

2. The semiconductor device as claimed in claim 1, characterized in that, It includes a plurality of said semiconductor elements, and the plurality of said semiconductor elements are connected in parallel between said circuit pattern and said wiring board.

3. The semiconductor device as claimed in claim 2, characterized in that, The gate electrodes of each of the plurality of semiconductor elements are connected to each other via a first driving wiring.

4. The semiconductor device as claimed in claim 1, characterized in that, RC-IGBTs are used in the semiconductor device.

5. The semiconductor device as claimed in claim 1, characterized in that, SiC is used in the semiconductor device.

6. A power conversion device, characterized in that, include: A main conversion circuit having a semiconductor device as described in any one of claims 1 to 5, which converts and outputs the input power; A driving circuit that outputs a driving signal to the semiconductor device for driving the semiconductor device; as well as A control circuit that outputs control signals to the drive circuit for controlling the drive circuit.

7. A semiconductor device, characterized in that, include: Circuit pattern; A semiconductor element disposed in the circuit pattern and having a gate electrode and an emitter electrode; A wiring board disposed on the side of the semiconductor element opposite to the circuit pattern and electrically connected to the emitter electrode; A gate control terminal and an emitter control terminal, which control the semiconductor element; A circuit board is disposed on the side of the wiring board opposite to the semiconductor element; A first driving wiring is connected to the gate control terminal and the gate electrode via the circuit board; as well as The second driving wiring is connected to the emitter control terminal and the wiring board via the circuit board.

8. The semiconductor device as claimed in claim 7, characterized in that, It includes a plurality of said semiconductor elements, and the plurality of said semiconductor elements are connected in parallel between said circuit pattern and said wiring board.

9. The semiconductor device as claimed in claim 8, characterized in that, The gate electrodes of each of the plurality of semiconductor elements are connected to each other via a first driving wiring.

10. The semiconductor device as claimed in claim 7, characterized in that, RC-IGBTs are used in the semiconductor device.

11. The semiconductor device as claimed in claim 7, characterized in that, SiC is used in the semiconductor device.

12. A power conversion device, characterized in that, include: A main conversion circuit having a semiconductor device as described in any one of claims 7 to 11, which converts and outputs the input power; A driving circuit that outputs a driving signal to the semiconductor device for driving the semiconductor device; as well as A control circuit that outputs control signals to the drive circuit for controlling the drive circuit.

13. A semiconductor device, characterized in that, include: Circuit pattern; A semiconductor element disposed in the circuit pattern and having a gate electrode and an emitter electrode; A wiring board disposed on the side of the semiconductor element opposite to the circuit pattern and electrically connected to the emitter electrode; A gate control terminal and an emitter control terminal, which control the semiconductor element; A circuit board is disposed on the same side of the circuit pattern as the semiconductor element. A first driving wiring is connected to the gate control terminal and the gate electrode via the circuit board; as well as The second driving wiring is connected to the emitter control terminal and the emitter electrode or the wiring board via the circuit board.

14. The semiconductor device as claimed in claim 13, characterized in that, It includes a plurality of said semiconductor elements, and the plurality of said semiconductor elements are connected in parallel between said circuit pattern and said wiring board.

15. The semiconductor device as claimed in claim 14, characterized in that, The gate electrodes of each of the plurality of semiconductor elements are connected to each other via a first driving wiring.

16. The semiconductor device as claimed in claim 13, characterized in that, RC-IGBTs are used in the semiconductor device.

17. The semiconductor device as claimed in claim 13, characterized in that, SiC is used in the semiconductor device.

18. A power conversion device, characterized in that, include: A main conversion circuit having a semiconductor device as described in any one of claims 13 to 17, which converts and outputs the input power; A driving circuit that outputs a driving signal to the semiconductor device for driving the semiconductor device; as well as A control circuit that outputs control signals to the drive circuit for controlling the drive circuit.

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