Display device

Abstract

According to the display device provided by the utility model, the first gate driving unit in the gate driving circuit of the non-display area in the display device comprises the first output module and the second output module, and the first gate driving unit provides two corresponding gate signals for two rows of sub-pixels respectively, so that the two rows of sub-pixels are driven; two clock signals used for generating two gate signals are transmitted through two clock lines, and each of the two clock lines is arranged nearby the first output module or the second output module acting on the two clock lines.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and more specifically to display devices. Background Technology

[0002] OLED (Organic Light-Emitting Diode) display devices have advantages such as high contrast and low power consumption, making them more suitable for scenarios with high image quality requirements.

[0003] However, the subpixels of OLED displays require initialization, detection, and compensation processes to achieve better light emission. This results in a large number of devices required for the GOA (Gate-driver On Array), leading to a larger size of the gate driving unit. Furthermore, as the resolution increases, the number of cascaded gate driving units in the GOA and the number of clock lines acting on the GOA also increase. All of these factors occupy a significant amount of bezel space in OLED displays, which is detrimental to the development of narrow bezels in OLED displays. Utility Model Content

[0004] The present invention provides a display device to solve the technical problem that existing OLED display devices are difficult to achieve narrow bezels.

[0005] An embodiment of this utility model provides a display device, including a plurality of sub-pixels and a gate driving circuit. The plurality of sub-pixels include a plurality of first sub-pixels located in one row and a plurality of second sub-pixels located in another row. The gate driving circuit includes cascaded multi-stage first gate driving units, each first gate driving unit comprising:

[0006] The first control module, the first control module of the first level, is electrically connected to the first frame start line, and the first control module of the nth level is electrically connected to the transmission terminal of the nkth level, where n is a positive integer greater than 1 and k is a positive integer less than n.

[0007] The first output module is electrically connected to the first control module and the first clock line, and is used to output a first gate signal to a plurality of corresponding first sub-pixels through the first output terminal;

[0008] The second output module is electrically connected to the first control module and the second clock line, and is used to output a second gate signal to the corresponding plurality of second sub-pixels through the second output terminal;

[0009] The first clock line and the second clock line are located on the same side or different sides of the gate drive circuit;

[0010] Wherein, the distance between the first clock line and the side of the first output module closest to the first clock line is less than the distance between the first clock line and the side of the corresponding first control module closest to the first clock line, and the distance between the second clock line and the side of the second output module closest to the second clock line is less than the distance between the second clock line and the side of the corresponding first control module closest to the second clock line.

[0011] This utility model provides a display device. By setting the first gate driving unit in the gate driving circuit of the non-display area of ​​the display device to include a first output module and a second output module, it can provide corresponding two gate signals to two rows of sub-pixels respectively, thereby driving the two rows of sub-pixels. The two clock signals used to generate the two gate signals are transmitted through two clock lines, and each of the two clock lines is set close to the first output module or the second output module that acts on it, thereby reducing the bezel size of the display device. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the display device provided for an embodiment of the present invention.

[0013] Figure 2 This is a schematic diagram of the gate drive circuit provided for an embodiment of the present invention.

[0014] Figure 3 , Figure 8 and Figure 11 The circuit diagrams are provided for the first gate driving unit, the second gate driving unit, and the third gate driving unit, respectively, according to embodiments of this utility model.

[0015] Figure 4 A layout diagram of the gate drive circuit provided for an embodiment of this utility model.

[0016] Figure 5 , Figure 12 and Figure 13 The diagrams show the layout of the first gate driving unit, the third gate driving unit, and the second gate driving unit provided in the embodiments of this utility model.

[0017] Figure 6 , Figure 7 An enlarged layout diagram of the two parts of the first gate driving unit provided for an embodiment of the present invention.

[0018] Figure 9 , Figure 10 This is a spatial graph showing the voltage values ​​of the first node and the first (second) output terminal in the display area provided as a comparative example and embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0020] In this invention, the terms "first," "second," "third," etc., are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or devices.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] The present invention provides a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0023] In some embodiments, such as Figure 1 and Figure 2 As shown, the display device 100 includes a plurality of sub-pixels and a gate driving circuit 10. The plurality of sub-pixels includes a plurality of first sub-pixels P1 and a plurality of second sub-pixels P2. The gate driving circuit 10 includes cascaded multi-stage first gate driving units 101, such as... Figure 3As shown, the first gate driving unit 101 includes: a first control module 20, the first control module 20 of the first stage is electrically connected to the first frame start line, the first control module 20 of the nth stage is electrically connected to the cascade terminal Cont[nk] of the nkth stage, where n is a positive integer greater than 1 (the attached figure shows k as 2 as an example, in which case n needs to start from 3), and k is a positive integer less than n; a first output module 301, the first output module 301 of the nth stage is electrically connected to the first control module 20 and the first clock line CKBO, and is used to output a first gate signal to the corresponding plurality of first sub-pixels P1 through the first output terminal Gn1[n] of the nth stage; a second output module 302, the second output module 302 of the nth stage is electrically connected to the first control module 20 and the second clock line CKBJ, and is used to output a second gate signal to the corresponding plurality of second sub-pixels P2 through the second output terminal Gn2[n] of the nth stage; combined with Figure 3 , Figure 4 and Figure 5 As shown, the distance d1 between the first clock line CKBO and the side of the first output module 301 closest to the first clock line CKBO (e.g., the distance between the center position of CKB2 to CKB8 in the first clock line CKBO and the right side of the first output module 301) is less than the distance d2 between the first clock line CKBO and the corresponding side of the first control module 20 closest to the first clock line CKBO (e.g., the distance between the center position of CKB2 to CKB8 in the first clock line CKBO and the left side of the first control module 20). The distance d3 between the second clock line CKBJ and the side of the second output module 302 closest to the second clock line CKBJ (e.g., the distance between the center position of CKB1 to CKB7 in the second clock line CKBJ and the left side of the first control module 20) is less than the distance d4 between the second clock line CKBJ and the corresponding side of the first control module 20 closest to the second clock line CKBJ (e.g., the distance between the center position of CKB1 to CKB7 in the second clock line CKBJ and the left side of the first control module 20).

[0024] The display device 100 may include a display area A1 for displaying an image and a non-display area A2 located on at least one side of the display area A1. The display area A1 contains a plurality of sub-pixels, and the non-display area A2 contains a gate driving circuit 10. For ease of description, this example illustrates a configuration where the plurality of sub-pixels are arranged in an array along a first direction D1 and a second direction D2, and the multi-level first gate driving units 101 are also arranged along the second direction D2. However, the actual configuration is not limited to this.

[0025] Specifically, a sub-pixel may include an electrically connected pixel circuit and a light-emitting element. The pixel circuit may be acted upon by at least the first gate signal or the second gate signal generated by the first gate driving unit 101 of the corresponding stage of the gate driving circuit 10, and also by the corresponding data voltage in the data signal generated by the source driver (not shown), so as to drive the corresponding light-emitting element to emit light of corresponding brightness in the corresponding time period.

[0026] In the attached diagram, k is illustrated as 2, meaning that starting from the 3rd level, the first control module 20 of each level is electrically connected to the transmission terminal of the 2nd level preceding it. Therefore, as... Figure 2 As shown, the first frame start line may include a first subframe start line STV11 and a second subframe start line STV12. The first control module 20 of the first level is electrically connected to the first subframe start line STV11, and the first control module 20 of the second level is electrically connected to the second subframe start line STV12.

[0027] Understandably, in addition to the first control module 20, the first gate driving unit 101 of this embodiment also includes a first output module 301 and a second output module 302, which are both controlled by the first control module 20 but are also controlled by the signals transmitted by the first clock line CKBO and the second clock line CKBJ, respectively. These output modules generate a first gate signal acting on the corresponding row of first sub-pixels P1 and a second gate signal acting on the corresponding row of second sub-pixels P2. In other words, the first gate driving unit 101 can drive at least the pixel circuits in the row of first sub-pixels P1 and the row of second sub-pixels P2, so that the number of first gate driving units 101 can be half or even less than the number of rows of sub-pixels. This reduces the size of the non-display area A2 in the second direction D2 and reduces the size of the bezel of the display device 100.

[0028] Meanwhile, although in this embodiment, the first gate driving unit 101 at the same level needs to be electrically connected to at least the first clock line CKBO and the second clock line CKBJ to work properly, but if Figure 2 As shown, considering that the connecting line 90 extends along the first direction D1 and multiple connecting lines 90 are arranged along the second direction D2, in this embodiment, the first clock line CKBO connected to the first output module 301 is set close to the first output module 301, and the second clock line CKBJ connected to the second output module 302 is set close to the second output module 302. This can reduce the length of the connecting line 90, and since the number of first gate driving units 101 is small, the number of connecting lines 90 is reduced, thereby reducing the size of the bezel of the display device 100.

[0029] Combination Figure 1 , Figure 3 and Figure 5 As shown, this invention does not limit the number of rows in which the sub-pixels electrically connected to the first output terminal Gn1[n] and the second output terminal Gn2[n] are located, that is, it does not limit the arrangement of the multiple first sub-pixels P1 and the multiple second sub-pixels P2. For example, if all sub-pixels in the same row are either first sub-pixels P1 or second sub-pixels P2, and the first sub-pixels P1 and the second sub-pixels P2 are arranged alternately along the second direction D2, then the multiple first output terminals are electrically connected to the sub-pixels in multiple odd-numbered rows, and the multiple second output terminals are electrically connected to the sub-pixels in multiple even-numbered rows. That is, the first output terminal Gn1[n] of the nth level is electrically connected to the sub-pixel in the nth row, and the second output terminal Gn2[n] of the nth level is electrically connected to the sub-pixel in the (n+1)th row. In this case, the number of first gate driving units 101 is half the number of rows of sub-pixels.

[0030] In some embodiments, such as Figure 5 As shown, the first output module 301 and the second output module 302 are both located on the first side L1 of the first clock line CKBO and the second clock line CKBJ, and are arranged along the directions in which the first clock line CKBO and the second clock line CKBJ extend. Specifically, the first clock line CKBO and the second clock line CKBJ can be arranged in parallel, and can be located on the same side of the first output module 301 and the second output module 302. It can be considered that the directions in which the first clock line CKBO and the second clock line CKBJ extend can be close to the direction of the arrangement of the multi-level first gate driving units 101 (e.g., the second direction D2).

[0031] Understandably, this embodiment takes into account that the widths of both the first clock line CKBO and the second clock line CKBJ are relatively small. To facilitate wiring, they can be arranged adjacent to each other. In this embodiment, the first output module 301 and the second output module 302 are arranged along a direction close to the second direction D2, so that the distance between each of the first output module 301 and the second output module 302 and the first clock line CKBO or the second clock line CKBJ is approximately the same. At this time, the vertical position relationship between the two is not limited. At the same time, the size of the non-display area A2 in the first direction D1 can be reduced, and the size of the bezel of the display device 100 can be reduced.

[0032] In some embodiments, combined with Figures 1 to 5As shown, the first gate driving unit 101 further includes: a stage transmission module 303, wherein the nth stage transmission module 303 is electrically connected to the first control module 20 and the third clock line CKA, and is used to output a first stage transmission signal to the stage transmission terminal Cont[n] of this stage; wherein, the distance between the third clock line CKA and the side of the stage transmission module 303 near the third clock line CKA is less than each of the distance between the third clock line CKA and the side of the first output module 301 near the third clock line CKA, and the distance between the third clock line CKA and the second output module 302.

[0033] Similarly, in this embodiment, based on the requirement to set the third clock line CKA to be electrically connected to the transmission module 303 so that the transmission module 303 can generate the first transmission signal, the third clock line CKA and the transmission module 303 connected to it are set close to each other. This can also reduce at least one of the length or number of the connecting lines used to connect the third clock line CKA and the transmission module 303, and further reduce the size of the bezel of the display device 100.

[0034] In some embodiments, such as Figure 5 As shown, the cascading module 303 is located on the second side L2, opposite to the first side L1, between the first clock line CKBO and the second clock line CKBJ. The third clock line CKA is located on the side of the cascading module 303 furthest from the second side L2. Since the third clock line CKA needs to be electrically connected to the cascading module 303, it is positioned close to the cascading module 303. This embodiment illustrates the case where the cascading module 303 is located between the first clock line CKBO, the second clock line CKBJ, and the third clock line CKA. In this case, because the third clock line CKA is located on the side of the cascading module 303 furthest from the second side L2, its distance from the cascading module 303 is closer than its distance from the first output module 301 and the second output module 302.

[0035] Of course, in other embodiments, the first clock line CKBO, the second clock line CKBJ, and the third clock line CKA can all be located between the first output module 301, the second output module 302, and the transmission module 303, as long as the first clock line CKBO is closer to the first output module 301, the second clock line CKBJ is closer to the second output module 302, and the third clock line CKA is closer to the transmission module 303.

[0036] In some embodiments, combined with Figures 1 to 5As shown, the number of first clock lines CKBO and the number of second clock lines CKBJ are both greater than 1; at least two first output modules 301 in two first gate drive units 101 are electrically connected to different first clock lines CKBO, and at least two second output modules 302 in two first gate drive units 101 are electrically connected to different second clock lines CKBJ (for example, including but not limited to 4 first clock lines CKB2, CKB4, CKB6 and CKB8, and 4 second clock lines CKB1, CKB3, CKB5 and CKB7, with different 4-level first output modules 301 connected to 4 first clock lines CKB2, CKB4, CKB6 and CKB8 respectively). Different 4-level second output modules 302 are respectively connected to 4 second clock lines (CKB1, CKB3, CKB5, CKB7); wherein, the distance between the multiple first clock lines CKB1 and the side of the multiple first output modules 301 closest to the multiple first clock lines CKB1 is less than the distance between the multiple first clock lines CKB1 and the side of the multiple first control modules 20 closest to the multiple first clock lines CKB1, and the distance between the multiple second clock lines CKB1 and the side of the multiple second output modules 302 closest to the multiple second clock lines CKB1 is less than the distance between the multiple second clock lines CKB1 and the side of the multiple first control modules 20 closest to the multiple second clock lines CKB1.

[0037] Understandably, the more first clock lines CKBO there are, the fewer first gate drive units 101 connected to each first clock line CKBO, resulting in a smaller signal load and less signal attenuation. The same applies to the second clock line CKBJ and the third clock line CKA. This embodiment does not limit whether the number of the three clock lines is equal.

[0038] When the number of first clock lines CKBO and the number of second clock lines CKBJ are both greater than 1, multiple first clock lines CKBO are arranged close to multiple first output modules 301, and multiple second clock lines CKBJ are arranged close to multiple second output modules 302. At this time, the length and number of connecting lines used to connect the first clock lines CKBO and the first output modules 301 are reduced to a greater extent, as are the length and number of connecting lines used to connect the second clock lines CKBJ and the second output modules 302, thereby reducing the size of the bezel of the display device 100 to a greater extent.

[0039] Similarly, when the number of third clock lines CKA is also greater than 1, multiple third clock lines CKA can be set up close to multiple transmission modules 303.

[0040] Figure 3 and Figure 5 Taking an example where the number of first clock lines CKBO and the number of second clock lines CKBJ are both 4, the first gate drive unit 101 in the same stage can be controlled by CKB2 and CKB1, or by CKB4 and CKB3, or by CKB6 and CKB5, or by CKB8 and CKB7. Furthermore, the number of third clock lines CKA can also be 4, with the four third clock lines CKA1, CKA2, CKA3, and CKA4 corresponding to the four first clock lines CKB2, CKB4, CKB6, and CKB8, respectively.

[0041] In some embodiments, such as Figure 5 As shown, the first clock line CKBO and the second clock line CKBJ are arranged alternately. The first clock signal transmitted by the first clock line CKBO and the second clock signal transmitted by the adjacent preceding second clock line CKBJ both have a first phase difference. The first clock signal transmitted by the first clock line CKBO and the second clock signal transmitted by the adjacent following second clock line CKBJ both have a second phase difference. The first phase difference and the second phase difference are opposites of each other. Among them, multiple first output modules 301 and multiple second output modules 302 are located on the first side of multiple first clock lines CKBO and multiple second clock lines CKBJ. The first output modules 301 and the corresponding second output modules 302 are arranged along the direction in which the multiple first clock lines CKBO and multiple second clock lines CKBJ extend.

[0042] Specifically, the timing controller (not shown) in the display device 100 can generate multiple first-type clock signals (e.g., multiple first-type clock signals and multiple second-type clock signals). The periods, duty cycles, corresponding high levels, and corresponding low levels of two adjacent first-type clock signals can be equal. Among two adjacent first-type clock signals, the latter has a first phase difference with the former, and the former has a second phase difference with the latter, and the first phase difference and the second phase difference are opposite numbers. The eight clock lines CKB1 to CKB8 can be connected to eight terminals arranged in a single sequence in the timing controller, thereby transmitting the eight first-type clock signals arranged with delays of either the first or second phase difference.

[0043] For example, for CKB1 to CKB8 arranged sequentially, CKB2i and CKB2i-1 have a first phase difference, and CKB2i-1 and CKB2i have a second phase difference, where i can be an integer from 1 to 4. For example, the eight clock pulses in a set of clock pulses corresponding to CKB1 to CKB8 can be arranged one at a time on the time axis.

[0044] Understandably, in this embodiment, in order to facilitate the connection of CKB1 to CKB8 with multiple terminals of the timing controller, and considering that CKB2, CKB4, CKB6, and CKB8 need to be set close to the first output module 301, and that CKB1, CKB3, CKB5, and CKB7 need to be set close to the second output module 302, CKB1 to CKB8 are arranged sequentially, so that the first clock line CKBO and the second clock line CKBJ are arranged alternately. At this time, regardless of whether the first output module 301 and the corresponding second output module 302 are located on the same side or different sides of CKB1 to CKB8, the distance between the first output module 301 and the multiple first clock lines CKBO, and the distance between the second output module 302 and the multiple second clock lines CKBJ are approximately the same, and are relatively close.

[0045] As can be seen from the above discussion, in this embodiment, multiple first output modules 301 and multiple second output modules 302 are arranged on the same side of CKB1 to CKB8, and both are arranged along the direction of extension of CKB1 to CKB8. This can avoid increasing the size of the bezel area in the first direction D1 and reduce the size of the bezel of the display device 100.

[0046] For ease of understanding of the whole text, the specific structure of the first control module 20 of the first gate drive unit 101 of the nth stage is illustrated here, but it is not limited to this.

[0047] Combination Figures 3 to 7As shown, the first control module 20 may include: a first precharge module 201, electrically connected to the stage transmission terminal Cont[n-2] of the (n-2)th stage, the first voltage line VGH1, and the first node Q[n], used to control the signal of the first node Q[n] according to the corresponding signal. Of course, it can also be controlled by the signals of the stage transmission terminals of other preceding stages; a first inverter module 202, electrically connected to the first node Q[n], the stage transmission terminal Cont[n-2] of the (n-2)th stage, the oscillation line LC, and the second node K[n], used to control the signal of the second node K[n] according to the corresponding signal; and a first pull-down sustaining module 203, electrically connected to the first node Q[n], the second voltage line VGL1, the second node K[n], and the third node N[n]. The first reset module 204 is electrically connected to the reset line VST, the third node N[n], the second voltage line VGL1 and the first node Q[n], and is used to control the signal of the first node Q[n] according to the corresponding signal; the first pull-down module 205 is electrically connected to the stage transmission terminal Cont[n+2] of the (n+2)th stage, the third node N[n], the second voltage line VGL1 and the first node Q[n], and is used to control the signal of the first node Q[n] according to the corresponding signal; the first anti-negative bias module 207 is electrically connected to the first node Q[n], the third node N[n] and the first voltage line VGH1, and is used to control the signal of the third node N[n] according to the corresponding signal. The first gate driving unit 101 may further include: a second pull-down module 304, electrically connected to the second node K[n], the second voltage line VGL1, the third voltage line VGL2, the first node Q[n], the first output terminal Gn1[n], and the second output terminal Gn2[n], for controlling the signals of the first node Q[n], the first output terminal Gn1[n], and the second output terminal Gn2[n] according to the corresponding signals.

[0048] Among them, the signals transmitted by the first voltage line VGH1, the second voltage line VGL1, and the third voltage line VGL2 can be three constant voltage signals with different amplitudes. A first capacitor C1 can be set between the first node Q[n] and the stage transmission terminal Cont[n].

[0049] Specifically, the first output module 301 includes a first output transistor T23, the second output module 302 includes a second output transistor T22, and the cascade module 303 includes a first cascade transistor T21. The gates of the three transistors are electrically connected to the first node Q[n]. The sources or drains of the three transistors are electrically connected to the corresponding first clock line CKBO, the corresponding second clock line CKBJ, and the corresponding third clock line CKA, respectively. The drains or sources of the three transistors are electrically connected to the first output terminal Gn1[n], the second output terminal Gn2[n], and the cascade terminal Cont[n], respectively.

[0050] Specifically, the second pull-down module 304 includes a first pull-down transistor T31, a second pull-down transistor T32, and a third pull-down transistor T33. The gates of the three transistors are all electrically connected to the second node K[n]. The source or drain of the first transistor is electrically connected to the second voltage line VGL1, and the source or drain of the latter two transistors is electrically connected to the third voltage line VGL2. The drain or source of the three transistors is electrically connected to the first node Q[n], the second output terminal Gn2[n], and the first output terminal Gn1[n], respectively.

[0051] Specifically, the first precharge module 201 includes a first precharge transistor T11; the first pull-down module 205 includes a first pull-down transistor T41A and a second pull-down transistor T41B; the first pull-down sustaining module 203 includes a first pull-down sustaining transistor T42A and a second pull-down sustaining transistor T42B; the first reset module 204 includes a first reset transistor T43A and a second reset transistor T43B; the first inverter module 202 includes a first inverter transistor T51_1, a second inverter transistor T51_2, a third inverter transistor T52, a fourth inverter transistor T53, a fifth inverter transistor T54, and a sixth inverter transistor T55; and the first negative bias protection module 207 includes a first negative bias protection transistor T71_1 and a second negative bias protection transistor T71_2. The electrical connections of the transistors and signal lines described above can be found in [reference needed]. Figure 3 .

[0052] The physical connections and spatial relationships of the multiple transistors, first voltage line VGH1, second voltage line VGL1, third voltage line VGL2, oscillation line LC, multiple first clock lines CKBO, multiple second clock lines CKBJ, and multiple third clock lines CKA in the first gate driving unit 101 can be referenced. Figures 4 to 7 The combination of, in Figure 6 and Figure 7 They are respectively Figure 5 Enlarged schematic diagram of the two different parts.

[0053] In some embodiments, such as Figure 5 As shown, at least two adjacent first gate driving units 101 are electrically connected to the same signal line (including at least one of the first voltage line VGH1, the second voltage line VGL1, the third voltage line VGL2, and the oscillation line LC) on the same side of the two via a connection line 90 located between them. Here, only the example of the first voltage line VGH1 being electrically connected to two adjacent first gate driving units 101 via the same connection line 90 is shown.

[0054] It should be noted that signal lines such as, but not limited to, the first voltage line VGH1, the second voltage line VGL1, the third voltage line VGL2, and the oscillation line LC need to act on at least two adjacent first gate driving units 101 (or even multiple consecutive first gate driving units 101). Since the direction of extension of the above signal lines is generally close to the direction of cascading of multiple first gate driving units 101 (second direction D2), multiple connecting lines 90 extending approximately along the first direction D1 can be provided to connect the corresponding devices in the corresponding multiple first gate driving units 101 to the same signal line.

[0055] Understandable, combined Figures 5 to 7 As shown, in this embodiment, by providing a connecting line 90 between at least two adjacent first gate driving units 101, since it is close to both adjacent first gate driving units 101, it can be configured as a main connecting line 900 with a relatively long length, including a connecting signal line (e.g., a first voltage line VGH1), and a first sub-connecting line 901 with a relatively short length that extends and connects to the first gate driving unit 101 of the previous stage and the second sub-connecting line 902 with a relatively short length that extends and connects to the first gate driving unit 101 of the next stage. This can at least halve the number of main connecting lines 90, thereby reducing the number of connecting lines 90, thereby reducing the size of the non-display area A2 in the second direction D2, and thus reducing the size of the bezel of the display device 100.

[0056] Furthermore, two adjacent first gate drive units 101 electrically connected to the same signal via the same connection line 90 can be mirror-symmetrical at least about the main connection line 900 (referred to as the axis of symmetry) in the connection line 90. For example, the second output module 302 and the first output module 301 in both are successively moved away from the "axis of symmetry", and the cascade module 303, the first capacitor C1, the second pull-down transistor T32, and the third pull-down transistor T33 in both are successively moved away from the "axis of symmetry".

[0057] In some embodiments, such as Figure 1 , Figure 4 and Figure 8 As shown, the gate driving circuit 10 further includes a plurality of cascaded second gate driving units 102. The second gate driving units 102 are electrically connected to the corresponding first output terminal (e.g., but not limited to the first output terminal Gn1[n] of the nth stage) or the corresponding second output terminal (e.g., but not limited to the second output terminal Gn2[n] of the nth stage), and are used to output a third gate signal to the corresponding plurality of first sub-pixels P1 or the plurality of second sub-pixels P2 through the corresponding third output terminal REF[n] according to the corresponding first gate signal or the corresponding second gate signal.

[0058] It should be noted that since the second gate driving unit 102 is only electrically connected to the corresponding row of sub-pixels (a row of first sub-pixels P1 or a row of second sub-pixels P2), the number of second gate driving units 102 can be equal to the number of rows of sub-pixels, that is, at least twice the number of rows of first gate driving units 101. However, the number of second gate driving units 102 can be close to or even the same as the sum of the first output terminals and second output terminals of multiple first gate driving units 101. Therefore, multiple second gate driving units 102 can be electrically connected to at least one of the multiple first output terminals and multiple second output terminals of multiple first gate driving units 101, respectively.

[0059] For example, the second gate driving units 102 of the 2n-1 stage and the 2n stage can be electrically connected to the first output terminal Gn1[n] and the second output terminal Gn2[n] of the nth stage, respectively. That is, multiple second gate driving units 102 are sequentially connected to the first output terminal and the second output terminal of multiple first gate driving units 101 that are cascaded in sequence. For another example, the second gate driving units 102 of the 2n-1 stage and the 2n stage can both be electrically connected to the first output terminal Gn1[n] or the second output terminal Gn2[n] of the nth stage. That is, multiple second gate driving units 102 are sequentially connected to the first output terminal Gn1[n] or the second output terminal Gn2[n] of multiple first gate driving units 101 that are cascaded in sequence. Figure 8 It is only shown that the control terminal of the third pull-down module 401 in the second gate drive unit 102 of at least the 2nth stage is electrically connected to the first output terminal Gn1[n-1] in the first gate drive unit 101 of the nth stage.

[0060] In some embodiments, combined with Figure 3 and Figure 8 As shown, in the same first gate driving unit 101, taking the nth stage as an example, the first output terminal Gn1[n] is electrically connected to a second gate driving unit 102, and the corresponding second output terminal Gn2[n] is electrically connected to the corresponding other second gate driving unit 102. That is, as discussed above, "the second gate driving units 102 of the (2n-1)th stage and the 2nth stage can be electrically connected to the first output terminal Gn1[n] and the second output terminal Gn2[n] of the nth stage, respectively." In this case, the first output terminal and the second output terminal of each first gate driving unit 101 are respectively connected to the two corresponding second gate driving units 102.

[0061] Understandably, taking the nth level as an example, in this invention, since the first node Q[n] is electrically connected to the second output terminal Gn2[n] and the first output terminal Gn1[n], and regardless of whether there are only multiple first output terminals, only multiple second output terminals, or multiple first output terminals and multiple second output terminals electrically connected to multiple second gate driving units 102 in the multi-level first gate driving units 101, for the first nodes of different levels, the number of second gate driving units 102 connected to the corresponding level's second output terminal and first output terminal is the same (1 or 2), making the load of the first nodes of different levels close, thereby improving the uniformity of the screen display.

[0062] Regardless of whether only the first output terminal, only the second output terminal, or both the first and second output terminals in the first gate driving unit 101 are electrically connected to the corresponding second gate driving unit 102, taking the nth stage as an example, in the case of... Figure 9 As shown, the voltage values ​​Qv of the first node Q[n] and Gv of the first (second) output terminal are displayed at different positions in the comparative example (i.e., the first gate driving unit 101 includes only one output terminal to drive the corresponding row of sub-pixels through its output gate signal). Figure 10 As shown, the voltage values ​​Qv of the first node Q[n] and Gv of the first (second) output terminal are displayed at different positions in the embodiment (i.e., the first gate driving unit 101 includes a first output terminal and a second output terminal to output corresponding first gate signals and second gate signals to drive the corresponding two rows of sub-pixels respectively). In the display area A1, a1 and a2 are the odd-numbered positions and even-numbered row positions in the upper region, respectively; b1 and b2 are the odd-numbered row positions and even-numbered row positions in the middle region, respectively; and c1 and c2 are the odd-numbered row positions and even-numbered row positions in the lower region, respectively.

[0063] Taking the direction of the cascaded multi-level first gate driving units 101 (second direction D2) as top to bottom, and with the first output terminal and second output terminal of the first gate driving unit 101 of the same level connected to adjacent odd-numbered row sub-pixels and even-numbered row sub-pixels respectively as an example, the following analysis can be made:

[0064] Figure 9In the comparative example, the multi-stage second gate drive unit 102 may be electrically connected to the first nodes of the first gate drive unit 101 respectively, resulting in a large difference between the potential of the first node of the first gate drive unit 101 that is not electrically connected to the second gate drive unit 102 and the potential of the first node of the first gate drive unit 101 that is electrically connected to the second gate drive unit 102 nearby. It is possible that only the multiple first nodes of the even-numbered stages are electrically connected to the corresponding multiple second gate drive units 102, resulting in a larger load on the first node of each even-numbered stage compared to the first node of the previous stage (odd-numbered stage). Furthermore, in the middle region compared to the upper region, due to the increase in the number of stages, the difference between the two Qv corresponding to b2 and b1 is greater than the difference between the two Qv corresponding to b2 and b1, and the difference between the two Gv corresponding to b2 and b1 is also greater. In addition, in the lower region compared to the middle region, due to the increase in the number of stages, the difference between the two Qv corresponding to c2 and c1 is also greater than the difference between the two Qv corresponding to b2 and b1, and the difference between the two Gv corresponding to c2 and c1 is also greater.

[0065] Figure 10 In the embodiments, regardless of whether the multi-level second gate driving units 102 are electrically connected to some or all of the first nodes of the first gate driving units 101, since the first node of each level of the first gate driving unit 101 is electrically connected to the first output terminal and the second output terminal, and is electrically connected to one or two corresponding second gate driving units 102 through the corresponding two, the load of the first node of each first gate driving unit 101 is the same. Therefore, the difference between the two Qv of the odd-numbered levels and the adjacent even-numbered levels (a2 and a1, or b2 and b1, c2 and c1) in the same area (upper area, middle area or lower area) in the display area A1 is small, and the difference between the two Gv is also small, thereby reducing the brightness difference of odd-numbered row sub-pixels and even-numbered row sub-pixels and improving the uniformity of the display.

[0066] In some embodiments, such as Figure 1 , Figure 4 and Figure 11 As shown, the gate driving circuit 10 further includes multiple cascaded third gate driving units 103. Each third gate driving unit 103 includes: a second control module 50, where the first-stage second control module 50 is electrically connected to the second frame start line, and the nth-stage second control module 50 is electrically connected to the fourth output terminal INI[nj] of the nj-th stage (the attached diagram shows j as 2 as an example), where j is a positive integer less than n, and j and k are equal or unequal; and a fourth output module 601, electrically connected to the second control module 50 and the fourth clock line CKC, used to output a fourth gate signal to the corresponding multiple first sub-pixels P1 or multiple second sub-pixels P2 through the fourth output terminal INI[n] of this stage; wherein, as... Figure 12As shown, the distance d5 between the fourth clock line CKC and the side of the fourth output module 601 closest to the fourth clock line CKC (for example, the distance between the center position of CKC1 to CKC4 in the fourth clock line CKC and the right side of the fourth output module 601) is less than the distance d6 between the fourth clock line CKC and the side of the second control module 50 closest to the fourth clock line CKC (for example, the distance between the center position of CKC1 to CKC4 in the fourth clock line CKC and the left side of the second control module 50).

[0067] In the attached diagram, j is 2 as an example, meaning that starting from the third level, the second control module 50 of each level is electrically connected to the fourth output terminal of the preceding second level. Therefore, as... Figure 2 As shown, the second frame start line may include the third subframe start line STV21 and the fourth subframe start line STV22. The first-level second control module 50 is electrically connected to the first subframe start line STV11, and the second-level second control module 50 is electrically connected to the second subframe start line STV12.

[0068] Understandably, in this embodiment, the fourth clock line CKC connected to the fourth output module 601 is located close to the fourth output module 601, avoiding the need to connect the fourth output module 601 and the fourth clock line CKC through long and numerous connecting lines. This reduces at least one of the length and number of connecting lines, further reducing the size of the bezel of the display device 100.

[0069] Furthermore, there can be multiple fourth clock lines CKC. At least two fourth output modules 601 in the two third gate driving units 103 are electrically connected to two different first clock lines CKC (for example, there can be, but are not limited to, four fourth clock lines CKC1, CKC2, CKC3, and CKC4, with different four-level fourth output modules 601 connected to the four fourth clock lines CKC1, CKC2, CKC3, and CKC4 respectively). Similarly, the more fourth clock lines CKC there are, the fewer third gate driving units 103 are connected to each fourth clock line CKC, resulting in a smaller signal load and less signal attenuation. In this case, multiple fourth clock lines CKC and multiple fourth output modules 601 can still be arranged close together, thereby further reducing the size of the bezel of the display device 100.

[0070] Similarly, since the third gate driving unit 103 is only electrically connected to the corresponding row of sub-pixels (row of first sub-pixel P1 or row of second sub-pixel P2), the number of second gate driving units 102 can be equal to the number of rows of sub-pixels, that is, at least twice the number of rows of first gate driving units 101. However, the number of second gate driving units 102 can be close to or even the same as the sum of the first output terminals and second output terminals of multiple first gate driving units 101.

[0071] In some embodiments, such as Figure 1 and Figure 4 As shown, in the direction of the gate driving circuit 10 pointing towards the multiple sub-pixels, multiple first gate driving units 101, multiple third gate driving units 103, and multiple second gate driving units 102 are arranged sequentially. That is, the multiple second gate driving units 102, multiple third gate driving units 103, and multiple first gate driving units 101 are arranged sequentially away from the display area A1. It can be considered that the third gate signal output by the second gate driving unit 102 closest to the display area A1 has the weakest driving force, while the first gate driving unit 101 furthest from the display area A1 outputs both the first gate signal and the second gate signal with the strongest driving force. Of course, the arrangement order of the above three gate driving units can also be set for the convenience of wiring.

[0072] Furthermore, in order to improve the driving force of the three gate driving units, the three can be set as bilateral driving, that is, the above-mentioned gate driving circuit 10 can be set in the non-display area A2 on both sides of the display area A1, and the three gate driving units in the gate driving circuit 10 on both sides can be at the same relative distance from the display area A1. That is, the multiple second gate driving units 102, multiple third gate driving units 103, and multiple first gate driving units 101 in the gate driving circuit 10 on the other side can also be moved away from the display area A1 in sequence.

[0073] For ease of understanding of the whole text, the specific structure of the third gate driving unit 103 and the second gate driving unit 102 of the nth stage is illustrated here, but it is not limited to this.

[0074] Combination Figure 11 and Figure 12As shown, the second control module 50 may include: a second precharge module 501, electrically connected to the fourth output terminal INI[n-2] of the (n-2)th stage, the first voltage line VGH1, and the fourth node Q'[n], used to control the signal of the fourth node Q'[n] according to the corresponding signal. Of course, it can also be controlled by the signals of the fourth output terminals of other preceding stages; a second inverter module 502, electrically connected to the fourth node Q'[n], the fourth output terminal INI[n-2] of the (n-2)th stage, the oscillation line LC, and the fifth node K'[n], used to control the signal of the fifth node K'[n] according to the corresponding signal; a second pull-down sustaining module 503, electrically connected to the fourth node Q'[n], the third voltage line VGL2, the fifth node K'[n], and the sixth node N'[n], used to control the signal of the sixth node N'[n] according to the corresponding signal; and a second reset module 504, electrically connected to the fourth node Q'[n], the third voltage line VGL2, the fifth node K'[n], and the sixth node N'[n], used to control the signal of the sixth node N'[n] according to the corresponding signal; and a second reset module 504, electrically connected to the fourth node Q'[n], the third voltage line VGL2, the fifth node K'[n], and the sixth node N'[n]. A fourth pull-down module 505 is electrically connected to the reset line VST, the sixth node N'[n], the third voltage line VGL2, and the fourth node Q'[n], and is used to control the signal of the fourth node Q'[n] according to the corresponding signal; a fifth pull-down module 506 is electrically connected to the fifth node K'[n], the third voltage line VGL2, and the fourth output terminal INI[n], and is used to control the signal of the fourth output terminal INI[n] according to the corresponding signal; a second anti-negative bias module 507 is electrically connected to the fourth node Q'[n], the sixth node N'[n], and the first voltage line VGH1, and is used to control the signal of the sixth node N'[n] according to the corresponding signal.

[0075] A second capacitor C2 can be set between the fourth node Q'[n] and the fourth output terminal INI[n].

[0076] Specifically, the fourth output module 601 includes a third output transistor T21_i, the gate of which is electrically connected to the fourth node Q'[n], its source or drain is electrically connected to the fourth clock line CKC, and its drain or source is electrically connected to the fourth output terminal INI[n].

[0077] Specifically, the fifth pull-down module 506 includes a fourth pull-down transistor T31_i, the gate of which is electrically connected to the fifth node K'[n], its source or drain is electrically connected to the third voltage line VGL2, and its drain or source is electrically connected to the fourth output terminal INI[n].

[0078] Specifically, the second precharge module 501 includes a second precharge transistor T11_i; the fourth pull-down module 505 includes a fifth pull-down transistor T41A_i and a sixth pull-down transistor T41B_i; the second pull-down sustaining module 503 includes a third pull-down sustaining transistor T42A_i and a fourth pull-down sustaining transistor T42B_i; the second reset module 504 includes a third reset transistor T43A_i and a fourth reset transistor T43B_i; the second inverter module 502 includes a seventh inverter transistor T51_1i, an eighth inverter transistor T51_2i, a ninth inverter transistor T52_i, a tenth inverter transistor T53_i, an eleventh inverter transistor T54_i, and a twelfth inverter transistor T55_i; and the second negative bias protection module 507 includes a third negative bias protection transistor T61_1i and a fourth negative bias protection transistor T61_2i. The electrical connections of the transistors and signal lines described above can be found in [reference needed]. Figure 11 The physical connections and spatial relationships can be referenced. Figure 12 .

[0079] Combination Figure 8 and Figure 13As shown, the second gate drive unit 102 may include: a third precharge module 701, electrically connected to the fourth output terminal INI[n+1] of the (n+1)th stage, the first voltage line VGH1, and the seventh node Q”[n], used to control the signal of the seventh node Q”[n] according to the corresponding signal. Of course, it can also be controlled by the signals of the fourth output terminals of other preceding stages; a third inverter module 702, electrically connected to the seventh node Q”[n], the fourth output terminal INI[n+1] of the (n+1)th stage, and the eighth node K”[n], used to control the signal of the eighth node K”[n] according to the corresponding signal; a third pull-down sustaining module 703, electrically connected to the seventh node Q”[n], the third voltage line VGL2, the eighth node K”[n], and the ninth node N”[n], used to control the signal of the ninth node N”[n] according to the corresponding signal; the aforementioned third pull-down module 401, electrically connected to The first output terminal Gn1[n-1] of the (n-1)th stage, the ninth node N”[n], the third voltage line VGL2 and the seventh node Q”[n] are used to control the signal of the seventh node Q”[n] according to the corresponding signal; the fifth pull-down module 706 is electrically connected to the eighth node K”[n], the fourth voltage line VGL3 and the third output terminal REF[n], and is used to control the signal of the fifth output terminal REF[n] according to the corresponding signal; the third anti-negative bias module 707 is electrically connected to the seventh node Q”[n], the ninth node N”[n] and the first voltage line VGH1, and is used to control the signal of the sixth node N'[n] according to the corresponding signal; the fourth output module 801 is electrically connected to the seventh node Q”[n], the fifth voltage line VGH2 and the third output terminal REF[n] (used to output the third gate signal), and is used to control the signal of the third output terminal REF[n] according to the corresponding signal.

[0080] Among them, a third capacitor C1_r can be set between the seventh node Q”[n] and the third output terminal REF[n].

[0081] Specifically, the fourth output module 801 includes a fourth output transistor T21_r, the gate of which is electrically connected to the seventh node Q”[n], its source or drain is electrically connected to the fifth voltage line VGH2, and its drain or source is electrically connected to the third output terminal REF[n].

[0082] Specifically, the fifth pull-down module 706 includes a fifth pull-down transistor T31_r, the gate of which is electrically connected to the eighth node K”[n], its source or drain is electrically connected to the fourth voltage line VGL3, and its drain or source is electrically connected to the third output terminal REF[n].

[0083] Specifically, the third precharge module 701 includes a second precharge transistor T11_r, the third pull-down module 401 includes a seventh pull-down transistor T41A_r and an eighth pull-down transistor T41B_r, the third pull-down sustaining module 703 includes a third pull-down sustaining transistor T42A_r and a fourth pull-down sustaining transistor T42B_r, the third inverter module 702 includes a thirteenth inverter transistor T51A_r, a fourteenth inverter transistor T51B_r, a fifteenth inverter transistor T52A_r, a sixteenth inverter transistor T52B_r, a seventeenth inverter transistor T53_r, an eighteenth inverter transistor T54_r, a nineteenth inverter transistor T55_r, and a twentieth inverter transistor T56_r, and the third anti-negative bias module 707 includes a fifth anti-negative bias transistor T61A_r and a sixth anti-negative bias transistor T61B_r. A fourth capacitor C2_r can be placed between the gate of the seventeenth inverting transistor T53_r and the first voltage line VGH1. The electrical connections of the transistors and signal lines described above can be found in [reference needed]. Figure 8 The physical connections and spatial relationships can be referenced. Figure 13 The combination of.

[0084] In order to facilitate the layout of the gate driving circuit 10, each of the third gate driving unit 103 and the second gate driving unit 102 can also be arranged in a mirror symmetry, and their axis of symmetry can be the same as the axis of symmetry of the first gate driving unit 101.

[0085] The display device provided by the embodiments of this utility model has been described in detail above. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the technical solution and core idea of ​​this utility model. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A display device, characterized in that, The system includes multiple sub-pixels and gate driving circuitry. The multiple sub-pixels include multiple first sub-pixels located in one row and multiple second sub-pixels located in another row. The gate driving circuitry includes cascaded multi-stage first gate driving units, each first gate driving unit comprising: The first control module, the first control module of the first level, is electrically connected to the first frame start line, and the first control module of the nth level is electrically connected to the transmission terminal of the nkth level, where n is a positive integer greater than 1 and k is a positive integer less than n. The first output module is electrically connected to the first control module and the first clock line, and is used to output a first gate signal to a plurality of corresponding first sub-pixels through the first output terminal; The second output module is electrically connected to the first control module and the second clock line, and is used to output a second gate signal to the corresponding plurality of second sub-pixels through the second output terminal; The first clock line and the second clock line are located on the same side or different sides of the gate drive circuit; Wherein, the distance between the first clock line and the side of the first output module closest to the first clock line is less than the distance between the first clock line and the side of the corresponding first control module closest to the first clock line, and the distance between the second clock line and the side of the second output module closest to the second clock line is less than the distance between the second clock line and the side of the corresponding first control module closest to the second clock line.

2. The display device according to claim 1, characterized in that, The first output module and the second output module are both located on the first side of the first clock line and the second clock line, and the first output module and the second output module are arranged along the direction in which the first clock line and the second clock line extend.

3. The display device according to claim 2, characterized in that, The first gate driving unit further includes: The transmission module is electrically connected to the first control module and the third clock line, and is used to output the first transmission signal to the transmission terminal of this stage. Wherein, the distance between the third clock line and the side of the transmission module closest to the third clock line is less than each of the distance between the third clock line and the side of the first output module closest to the third clock line, and the distance between the third clock line and the second output module.

4. The display device according to claim 3, characterized in that, The cascading module is located on the second side of the first clock line and the second clock line, opposite to the first side, and the third clock line is located on the side of the cascading module away from the second side.

5. The display device according to claim 1, characterized in that, The number of the first clock line and the number of the second clock line are both greater than 1; At least two of the first gate driving units are electrically connected to two different first clock lines, and at least two of the first gate driving units are electrically connected to two different second clock lines. Wherein, the distance between the plurality of first clock lines and the side of the plurality of first output modules near the plurality of first clock lines is less than the distance between the plurality of first clock lines and the side of the plurality of first control modules near the plurality of first clock lines, and the distance between the plurality of second clock lines and the side of the plurality of second output modules near the plurality of second clock lines is less than the distance between the plurality of second clock lines and the side of the plurality of first control modules near the plurality of second clock lines.

6. The display device according to claim 5, characterized in that, The first clock line and the second clock line are arranged alternately. The first clock signal transmitted by the first clock line and the second clock signal transmitted by the adjacent preceding second clock line both have a first phase difference. The first clock signal transmitted by the first clock line and the second clock signal transmitted by the adjacent following second clock line both have a second phase difference. The first phase difference and the second phase difference are opposites of each other. The plurality of first output modules and the plurality of second output modules are located on the first side of the plurality of first clock lines and the plurality of second clock lines, and the first output modules and the corresponding second output modules are arranged along the direction of extension of both the first clock lines and the second clock lines.

7. The display device according to any one of claims 1 to 6, characterized in that, At least two adjacent first gate drive units are electrically connected to the same signal line on the same side of both units via a connection line located between them.

8. The display device according to any one of claims 1 to 6, characterized in that, The gate driving circuit further includes a plurality of cascaded second gate driving units, each of which is electrically connected to a corresponding first output terminal or a corresponding second output terminal, and is used to output a third gate signal to a plurality of corresponding first sub-pixels or a plurality of second sub-pixels through a corresponding third output terminal according to the corresponding first gate signal or the corresponding second gate signal.

9. The display device according to claim 8, characterized in that, In the same first gate driving unit, the first output terminal is electrically connected to a second gate driving unit, and the corresponding second output terminal is electrically connected to another corresponding second gate driving unit.

10. The display device according to claim 8, characterized in that, The gate driving circuit further includes a plurality of cascaded third gate driving units, wherein the third gate driving unit includes: The second control module, the first level of the second control module is electrically connected to the second frame start line, and the nth level of the second control module is electrically connected to the fourth output terminal of the njth level, where j is a positive integer less than n, and j and k are equal or unequal; The fourth output module is electrically connected to the second control module and the fourth clock line, and is used to output a fourth gate signal to a plurality of corresponding first sub-pixels or a plurality of second sub-pixels through the fourth output terminal of this stage; Wherein, the distance between the fourth clock line and the side of the fourth output module closest to the fourth clock line is less than the distance between the fourth clock line and the side of the second control module closest to the fourth clock line.

11. The display device according to claim 10, characterized in that, In the direction in which the gate driving circuit points to the plurality of the aforementioned sub-pixels, a plurality of first gate driving units, a plurality of third gate driving units, and a plurality of second gate driving units are arranged sequentially.

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