Memory circuit and memory device

Abstract

The utility model discloses a memory circuit and a memory device. The memory circuit includes a memory array including a first portion and a second portion. The first portion includes a plurality of first memory cells, and the second portion includes a plurality of second memory cells. The memory circuit includes an input / output (I / O) circuit physically disposed alongside the memory array along a first lateral direction, coupled to the first portion and the second portion via a first access line and a second access line, respectively. The memory circuit includes a first pre-charge circuit disposed from the I / O circuit opposite the first portion entity and configured to charge the first access line prior to accessing the plurality of first memory cells. The memory circuit includes a second pre-charge circuit disposed opposite the second portion entity from the first pre-charge circuit and configured to charge at least a portion of the second access line prior to accessing the plurality of second memory cells.

Description

Technical Field

[0001] One embodiment disclosed herein relates to a high-density static random access memory (SRAM), and more particularly to a high-density SRAM suitable for bit-line precharging. Background Technology

[0002] The semiconductor industry has experienced rapid development due to the continuous increase in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, the improvement in integration density is due to the iterative reduction in the minimum feature size, which allows more components to be integrated into a given area. Utility Model Content

[0003] In some embodiments, a memory circuit is provided, comprising a memory array, an input / output circuit, a first precharge circuit, and a second precharge circuit. The memory array includes a first portion and a second portion. The first portion includes a plurality of first memory cells, and the second portion includes a plurality of second memory cells. The input / output circuit is physically disposed adjacent to the memory array along a first lateral direction. The input / output circuit is coupled to the first portion and the second portion via a first access line and a second access line, respectively. The first precharge circuit is physically disposed opposite to the first portion of the input / output circuit along the first lateral direction. The second precharge circuit is physically disposed opposite to the second portion of the first precharge circuit along the first lateral direction.

[0004] In some embodiments, a memory circuit is provided, including a memory array, a first precharge circuit, and a second precharge circuit. The memory array includes a first portion and a second portion, wherein the first portion includes a plurality of first memory cells coupled to each other via first bit lines, and the second portion includes a plurality of second memory cells coupled to each other via second bit lines, wherein the first bit lines extend along a first lateral direction, and the second bit lines include at least a portion extending along the first lateral direction. The first precharge circuit is physically disposed adjacent to the first portion along the first lateral direction. The second precharge circuit is physically disposed adjacent to the second portion along the first lateral direction.

[0005] In some embodiments, a memory device is provided, including a memory array, an input / output circuit, a first precharge circuit, a second precharge circuit, a third access line, and a fourth access line. The memory array includes a first portion and a second portion, wherein the first portion includes a plurality of first memory cells, and the second portion includes a plurality of second memory cells. The input / output circuit is physically disposed adjacent to the memory array along a first lateral direction, wherein the input / output circuit is coupled to the first portion and the second portion via the first access line and the second access line, respectively. The first precharge circuit is physically disposed opposite to the input / output circuit and the first portion along the first lateral direction. The second precharge circuit is physically disposed opposite to the first precharge circuit and the second portion along the first lateral direction. The third access line extends physically along the first lateral direction and is coupled to the first portion, the input / output circuit, and the first precharge circuit. The fourth access line extends physically along the first lateral direction and is coupled to the second portion, the input / output circuit, and the second precharge circuit. Attached Figure Description

[0006] The various aspects of one embodiment disclosed herein should be understood in light of the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 Block diagrams of memory devices according to various embodiments are illustrated;

[0008] Figure 2 This describes various embodiments of a circuit including a remote bit line pre-charge circuit. Figure 1 A block diagram of a memory device;

[0009] Figure 3 Description of various embodiments Figure 2 A schematic diagram of the first example of a far-end bitline pre-charge circuit;

[0010] Figure 4 Description of various embodiments Figure 2 A schematic diagram of the second example of the far-end bit line pre-charge circuit;

[0011] Figure 5 Description of various embodiments Figure 2 A schematic diagram of the third example of the far-end bit line pre-charge circuit;

[0012] Figure 6 Description of various embodiments Figure 2 A schematic diagram of the fourth example of the far-end bit line pre-charge circuit;

[0013] Figure 7Description of various embodiments Figure 2 A schematic diagram of the fifth example of the far-end bit line pre-charge circuit;

[0014] Figure 8 Description of various embodiments Figure 2 A schematic diagram of the sixth example of the far-end bit line pre-charge circuit;

[0015] Figure 9 The flowchart of an example method for forming a memory device according to some embodiments is described.

[0016] [Symbol Explanation]

[0017] 100: Memory Device

[0018] 105: Memory Controller

[0019] 107: Signal

[0020] 112:I / O circuit

[0021] 120: Memory Array

[0022] 200: Block Diagram

[0023] 202: Memory Group

[0024] 202A: First Memory Group

[0025] 202B: Second Memory Set

[0026] 204: Pre-charge circuit

[0027] 204A: First pre-charge circuit

[0028] 204B: Second pre-charge circuit

[0029] 206, 206A~D: Access lines

[0030] 208: Control Line

[0031] 210, 210A~B: Buffer

[0032] 212, 212A~B: Inverters

[0033] 300, 400, 500, 600, 700, 800: Schematic diagram

[0034] 302, 302A~C, 402, 702, 702A, 702B, 802, 802A~B, 804, 804A~B, CPBL, CPBLB, N1, N2, N3, N4, P1, P2: Transistors

[0035] 900: Method

[0036] 902, 904, 906, 908: Operation

[0037] BL, BL0, BL1, ..., BLK: Bit lines

[0038] BLB: Third Access Line

[0039] BLEQB: BL equalizer B

[0040] DC: Data Bus C

[0041] DT: Data Bus T

[0042] FBL: Flying Overbit Line

[0043] FBLB: Complementary FBL

[0044] FEBLEQ_CTRL: signal

[0045] FEBLPCH: Remote BL pre-charge circuit

[0046] GLB_BLEQ_BOT: Signal

[0047] GLB_BLEQ_TOP: Signal

[0048] PBL, PBLB: PMOS transistors

[0049] PEQ: Equalizer

[0050] PMCTRL: Power Management Control

[0051] VDD: Power supply

[0052] Vmin: Minimum voltage

[0053] VSS: Second voltage

[0054] WL, WL0, WL1, ..., WLJ: Character lines

[0055] YB[3:0]: Signal Detailed Implementation

[0056] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below to simplify one embodiment of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, one embodiment of this disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0057] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” and similar terms are used herein to describe the relationship between one component or feature and another illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0058] As integrated circuit technology advances, it may become necessary to optimize memory density to shrink to lower technology nodes. With static random access memory (SRAM) occupying a relatively large portion of the system-on-chip (SoC) area (e.g., around 70% in some systems or applications), circuits, architectures, or layouts can be designed to maintain or increase area efficiency. Focusing on area efficiency is particularly important in SRAM-dominated applications. Furthermore, achieving a smaller footprint, thereby further improving overall area efficiency, can contribute to a reduction in capacitance. Reduced capacitance, in turn, leads to lower dynamic power consumption. Therefore, these interrelated patterns highlight the complexity of semiconductor technology, as it concerns memory density, area efficiency, and power consumption at lower technology nodes.

[0059] In some cases, memory density can be increased by reducing the perimeter allocated to a given size of bit cell array. This approach optimizes the space utilization of the integrated circuit, thereby contributing to improved overall efficiency. In some cases, considering the Ion / Ioff ratio, the perimeter can be reduced by utilizing the maximum number of bits per bit line (BL) supported by the system. In some configurations, as discussed herein, extended density optimization paradigms may involve utilizing a fly-bit line (FBL) architecture.

[0060] For example, in some systems, the BL resistance in advanced technology nodes may increase significantly. This increase in BL resistance is particularly noteworthy when maximizing the number of columns per BL, such as in at least one of the actual BLs and in the FBL. The increased BL resistance, exacerbated by the increased number of cells per BL, can pose challenges for BL pre-charging. For instance, due to the relatively high BL resistance and the increased number of cells per BL, pre-charging the BL at the far end (e.g., the end of the BL opposite the input / output (I / O) circuitry) may take excessive time. In some cases, this excessive time spent pre-charging the BL at the far end can be exacerbated by the FBL architecture. Furthermore, any difference in pre-charge level between the BL and its complementary BL (e.g., bit line B (BLB)) due to the relatively long / wide voltage drop across the BL can introduce functional problems during certain memory operations (e.g., read operations) due to this differential effect. Therefore, semiconductor design and operation can be considered to improve the BL pre-charging process.

[0061] The systems and methods of the technical solutions provide various embodiments of memory devices for precharging the far ends of BLs (and FBLs). These systems and methods provide at least one precharge circuit (e.g., sometimes referred to as a (far-end) precharge circuit) for precharging the BLs at the far end to improve the rate of BL precharging and prevent leakage from inactive cells. The precharge circuit may include an equalizer for precharging the BLs and BLBs, thereby providing relatively equal precharges (e.g., voltages) to the BLs and BLBs (e.g., no precharge difference between the far-end BLs and BLBs), thus preventing potential read functionality problems. The precharge circuit can be applied to or used in various non-limiting technology nodes. In various cases, such as the number of bits supported by each BL by technical constraints, an increase in memory density can be achieved by using the precharge circuits of the technical solutions discussed herein, thereby minimizing or avoiding the impact on BL precharge time. The techniques disclosed in this article can be applied to various memory technologies, including SRAM, RRAM, MRAM, phase-change memory, NVM, NOR, NAND, electric fuses, OTP, and BEOL memory.

[0062] Figure 1 Block diagrams illustrating memory device 100 (or memory circuitry) according to various embodiments are provided. Memory device 100 includes memory array 120, memory controller 105, and input / output (I / O) circuitry 112. Although in Figure 1 Although not explicitly shown, memory device 100 may include other components (such as bit line controllers, word line controllers, etc.). Despite... Figure 1 Although not explicitly shown, the components of memory device 100 are operatively coupled to each other and to memory controller 105. For example, in some embodiments, a heater may be included, and the heater is at least thermally coupled to memory array 120, while memory controller 105, I / O circuitry 112, etc., may be electrically coupled to memory array 120. Although in Figure 1 In the illustrated examples, elements are shown as separate blocks for clarity, but in some other embodiments, Figure 1 Some or all of the components shown may be integrated together. For example, memory array 120 may include I / O circuitry 112 embedded therein.

[0063] Memory array 120 is embodied as a semiconductor memory device. Memory array 120 includes a plurality of memory circuits or memory cells. Memory array 120 includes word lines WL0, WL1, ..., WLJ (not shown) extending in a vertical direction (e.g., the Y direction) and bit lines BL0, BL1, ..., BLK (not shown) extending in a horizontal direction (e.g., the X direction). The word lines WL and bit lines BL may be conductive metal or conductive rails. In one configuration, each memory cell is coupled to a corresponding word line WL and a corresponding bit line BL and is operable according to a voltage or current passing through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes a bit line BL coupled to one or more memory cells in a group of memory cells arranged along a horizontal direction (e.g., the X direction). The bit line BL may receive and / or provide differential signals. Each memory cell may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, each memory cell is embodied as a static random access memory (SRAM) cell or other type of memory cell. In some configurations, WL and / or BL may extend in other directions, such as BL extending in the vertical direction (e.g., the Y direction), as at least in combination with Figure 2 As shown, WL extends in the horizontal direction (e.g., the X direction).

[0064] I / O circuitry 112 is a hardware element that can access (e.g., read, program) each of the memory cells in memory array 120 asserted by at least one decoder (such as a WL decoder or a BL decoder (not shown)). I / O circuitry 112 may be referred to as main I / O (MIO). For example, a plurality of switch / select transistors may form I / O circuitry 112. In some embodiments, memory array 120 may be formed in a first region of a substrate, while I / O circuitry 112 may be formed in a second region of the substrate. The second region may be configured as a closed loop or an open loop surrounding the first region. Although the second region is shown as horizontally adjacent to the first region (e.g., disposed relative to each other along a second lateral direction), in some configurations the second region may be vertically adjacent to the first region (e.g., disposed relative to each other along a first lateral direction), such as in combination, but not limited to... Figure 2 As shown. The areas of the substrate containing the memory array 120 and I / O circuitry 112 may be arranged in other directions relative to each other, wherein the I / O circuitry 112 may be operatively coupled to the memory array 120 via at least one access line or at least one connector (such as, but not limited to, BL, BLB, FBL, etc.), such as, but not limited to, combination. Figure 2 As shown.

[0065] The memory controller 105 is a hardware component that controls the operation of the memory array 120. For example... Figure 1 As shown, the memory controller 105 may be physically located adjacent to the I / O circuitry 112. In some configurations, the memory controller 105 may be physically located in other areas or portions of the memory device 100, such as adjacent to the memory array 120. The memory controller 105 includes and / or controls one or more elements of the I / O circuitry 112 and the memory array 120 (e.g., a pre-charge circuit for pre-charging at least one BL, such as at least combined with...). Figures 2 to 8 (As described herein). In some instances, I / O circuitry 112, precharge circuitry, etc., may be embodied as logic circuitry, analog circuitry, or a combination thereof. Memory controller 105 may provide (e.g., decoder) signals 107 to different memory cells, such as via different pairs of a first set and a second set of metal rails. In one configuration, memory controller 105 may control voltage supply circuitry included therein to provide voltage signals to I / O circuitry 112, precharge circuitry, etc. In some embodiments, this voltage supply circuitry is embodied as or includes a processor and a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform one or more functions of memory controller 105 as described herein. In some cases, memory controller 105 may send signal 107 to at least one element of memory array 120 (such as at least one precharge circuitry). For example, memory controller 105 may send signal 107 to initiate precharge of at least one of the memory blocks (BLs). In another instance, memory controller 105 may send signal 107 to terminate precharge of the BLs. In some embodiments, the memory controller 105 includes a ratio Figure 1 The components shown may include more components, fewer components, or components with... Figure 1 The components shown are different components.

[0066] Figure 2 This describes various embodiments of the pre-charge circuitry 204A-B (sometimes referred to as pre-charge circuitry 204) including the far-end bit line pre-charge circuitry 204. Figure 1 Block diagram 200 of memory device 100. As shown, at least a portion of memory device 100 is provided in block diagram 200, which includes at least memory controller 105, I / O circuit 112, memory array 120, etc.

[0067] Memory array 120 may include multiple portions, such as a first portion and a second portion. The first portion may include or be associated with a first memory group 202A (e.g., a bottom group). The second portion may include or be associated with a second memory group 202B (e.g., a top group). Memory groups 202A-B may be referred to as memory group 202. For example, in some configurations, memory array 120 may include a single portion having memory group 202 or multiple portions having additional memory groups 202. Although the first memory group 202A and the second memory group 202B are represented as a bottom group and a top group, in some cases, the memory groups may be configured in different ways, such as the first memory group 202A being the top group and the second memory group 202B being the bottom group.

[0068] Memory group 202 may be positioned or physically disposed along a first lateral direction (e.g., in this case, the vertical or Y direction). For the purpose of providing an example herein, I / O circuitry 112 may be disposed alongside memory array 120 along the first lateral direction, with the first memory group 202A closer to I / O circuitry 112 and inserted between the second memory group 202B and I / O circuitry 112.

[0069] Memory array 120 may include one or more precharge circuits 204. The precharge circuit 204 may be referred to as a far-end BL pre-charge circuit (FEBLPCH). For example, memory array 120 may include a first precharge circuit 204A and a second precharge circuit 204B. Depending on the configuration of memory device 100, there may be more or fewer precharge circuits 204. In some cases, the number of precharge circuits 204 may correspond to the number of memory groups 202 (or sets of BLs coupled to individual memory groups 202). The precharge circuits 204 may be disposed alongside / adjacent to individual memory groups 202 along a first lateral direction. The precharge circuits 204 may be disposed opposite to the portion of the entity containing the individual memory groups 202 from I / O circuit 112. For example, a first precharge circuit 204A may be disposed next to the first memory group 202A opposite to the I / O circuit 112 along a first lateral direction. A second precharge circuit 204B may be disposed next to the second memory group 202B opposite to the first precharge circuit 204A and / or the first memory group 202A along the opposite first lateral direction.

[0070] Memory device 100 may include one or more access lines 206A-D (sometimes referred to as access lines 206, for example). Access lines 206 may extend in a first lateral direction. Access lines 206 may include BL or FBL or corresponding to them. In some cases, each access line 206 may include a complementary access line 206. For example, BL may be paired with a complementary BL (e.g., BLB). FBL may be paired with a complementary FBL (e.g., FBLB). Each access line 206 may be coupled to I / O circuitry 112, individual memory groups 202, and individual precharge circuitry 204. In some embodiments, BL may be referred to as a first access line. FBL may be referred to as a second access line. BLB may be referred to as a third access line. FBLB may be referred to as a fourth access line. In some other embodiments, for example, any BL (e.g., BL, BLB, FBL, or FBLB) may be referred to as a first access line, a second access line, a third access line, etc.

[0071] For example, BL and BLB may be coupled to I / O circuit 112, first memory group 202A, and first precharge circuit 204A. FBL and FBLB may be coupled to I / O circuit 112, second memory group 202B, and second precharge circuit 204B. FBL may refer to or represent BL that spans at least a portion of memory array 120. In this case, FBL (and FBLB) may span the first memory group 202A and the first precharge circuit 204A to be coupled to the second memory group 202B and the second precharge circuit 204B. Since FBL and FBLB span the first memory group 202A and the first precharge circuit 204A, FBL and FBLB are not coupled to the first memory group 202A and the first precharge circuit 204A.

[0072] For example, the FBL (or FBLB) may include multiple segments disposed in different metallization layers. The BL and BLB may extend from the I / O circuit 112 to the first precharge circuit 204A and be disposed in the first metallization layer to be operatively coupled to the memory cells of the first memory group 202A and / or one or more elements of the first precharge circuit 204A. For example, the FBL and FBLB may include a first segment and a second segment extending from the I / O circuit 112 to the second precharge circuit 204B. The first segment may be disposed in a second metallization layer above the first metallization layer. The first segment may extend from the I / O circuit 112 across the first memory group 202A and the first precharge circuit 204A, such that the first segment of the FBL and FBLB is not coupled to the memory cells of the first memory group 202A and the elements of the first precharge circuit 204A. The second segment may extend from the first segment to the second precharge circuit 204B, wherein the second segment of FBL and FBLB is operatively coupled to at least one of the memory cells of the second group 202B and / or one or more elements of the second precharge circuit 204B. The memory device 100 may include an additional FBL spanning a portion of the memory array 120.

[0073] The memory controller 105 can write data to or read data from the memory group 202 based on electrical signals via access lines 206. For example, access lines 206 can be coupled to individual memory groups 202. Each memory cell in a memory group 202 can be coupled to an individual access line 206 (e.g., BL or, in some cases, WL). Access lines 206 can carry, receive, or transmit signals between the I / O circuitry 112 and one or more memory cells in the memory group 202. In some cases, access lines 206 may include a WL. Each memory cell can operate based on voltage or current passing through the corresponding bit line BL (or the corresponding word line WL).

[0074] Read and write operations can be performed via access line 206 (e.g., BL or FBL). In some scenarios, to write data to a memory cell, I / O circuitry 112 can apply a voltage or current corresponding to the data to be stored in the memory cell via access line 206 (e.g., BL) coupled to the memory cell. In this case, access line 206 can act as a conduit for data transmission, thereby allowing write interaction with the memory array.

[0075] In another scenario, to read data from a memory cell, data can be retrieved from the memory cell using at least one selected access line 206. For example, the state of an individual memory cell can be detected along the addressed access line 206 via a read-out mechanism. In this case, the I / O circuit 112 (or other elements of the memory device 100) can be used to read the voltage or current corresponding to the data stored in the memory cell via the access line 206 (e.g., corresponding to BL) coupled to the memory cell, thereby allowing the stored information to be retrieved from the memory cell (e.g., for subsequent processing). The read or write operation can be initiated by the memory controller 105. For example, the memory controller 105 can send a signal (e.g., signal 107) to the memory array 120 to cause the memory cell to output a corresponding voltage for detection by the I / O circuit 112. The memory controller 105 can send a signal to the I / O circuit 112 indicating a voltage or current corresponding to data, such that the I / O circuit 112 can apply a voltage or current for writing data to at least one (e.g., selected) memory cell.

[0076] Each access line 206 may be coupled to a separate precharge circuit 204. The precharge circuit 204 may be located at the distal end (e.g., the far end) of the access line 206 opposite to the proximal end of the access line 206 coupled to the I / O circuit 112. The precharge circuit 204 may be used to set the voltage at one or more access lines 206 to a predetermined voltage level. The precharge circuit 204 may be used to minimize the time required to precharge the BL at the far end (or improve the precharge efficiency at the far end of the BL), thereby preventing potential functional problems, such as those caused by the difference in precharge levels between the BL and BLB (or FBL and FBLB) during read operations. This may be combined with, but is not limited to, other methods. Figures 3 to 8 The operation or characteristics of the precharge circuit 204 are described using at least one of the following: For example, the precharge circuit 204 is a circuit or element that can set or precharge a voltage at one or more BL (or FBL) lines. In some embodiments, the precharge circuit 204 is implemented as one or more switches or one or more transistors, such as, but not limited to, combinations thereof. Figures 3 to 8 As described herein. In some embodiments, the precharge circuit 204 may be replaced by different elements capable of performing the functions of the precharge circuit 204 described herein.

[0077] In various configurations, the precharge circuit 204 can be controlled based on a precharge control signal (e.g., signal 107) or other signals from the memory controller 105 of the memory device 100 or other components. For example, in response to a signal 107 from the memory controller 105 having a first voltage (e.g., VDD or 1V), the precharge circuit 204 can be activated / enabled to set or precharge the voltage at BL to a predetermined voltage level (e.g., VDD or 1V). In another instance, the precharge circuit 204 can be disabled / deactivated such that the precharge circuit 204 can respond to a signal 107 from the memory controller 105 having a second voltage (e.g., VSS or 0V) without setting the voltage at BL or without precharging the voltage at BL.

[0078] In some configurations, the memory controller 105 may send a high signal (e.g., 1V) to the precharge circuit 204 to activate or begin precharging the BL coupled to the precharge circuit 204. In some other configurations, the memory controller 105 may send a low signal (or a stop signal) to the precharge circuit 204 to begin precharging the BL. In this case, the signal from the memory controller 105 may be inverted for the precharge circuit 204.

[0079] For example, such as Figure 2 As shown, the memory controller 105 may be coupled to the precharge circuit 204 via at least one control line 208. The control line 208 may include a first segment extending along a first lateral direction and a second segment extending along a second lateral direction (e.g., a horizontal direction in this case), wherein the second segment is coupled to the precharge circuit 204 for activating or deactivating the functionality of the precharge circuit 204. The control line 208 may include one or more buffers 210A-B (e.g., sometimes referred to as buffer 210) or one or more inverters 212A-B (e.g., sometimes referred to as inverter 212). The memory controller 105 may send a signal 107 via the buffers 210 and the inverters 212 for controlling the precharge circuit 204.

[0080] Buffer 210 can be used for signal conditioning (e.g., conditioning signal 107), amplification, isolation, timing control, etc. For example, buffer 210 can be used to improve or maintain the quality or integrity of signal 107 from memory controller 105 to precharge circuit 204. In this case, buffer 210 can be a signal integrity buffer. In some cases, control line 208 may not include buffer 210. Inverter 212 can be used to invert the signal from memory controller 105, such that a high signal (e.g., 1V) received from memory controller 105 can be inverted to a low signal (e.g., 0V), and vice versa. For the purpose of providing examples herein, control line 208 may include inverter 212 such that when a low signal (e.g., no signal or a second voltage) is sent, one or more switches or transistors of precharge circuit 204 can be activated, thereby initiating precharge of BL. In some implementations, the inverter 212 may not be included in the control line 208, allowing the memory controller 105 to initiate the operation of the precharge circuit 204 by sending a high signal (e.g., 1V or a first voltage).

[0081] In some configurations, when using the precharge circuit 204, read and / or write operations can be performed through multiple stages, such as a precharge stage and a read or write stage. For example, during the precharge stage, the memory controller 105 may generate a signal 107 (e.g., a precharge control signal) with a second voltage (e.g., 0V) to activate the precharge circuit 204. In some cases, generating the signal 107 with the second voltage may mean not sending the signal 107 to the precharge circuit 204 (or preventing the memory controller 105 from sending the signal 107). The second voltage can be inverted via the inverter 212, causing a predetermined voltage to be applied to the transistor or switch of the precharge circuit 204, thereby initiating the precharge operation. For example, the inverter 212 may be connected to a power line, such as VDD or a power supply. For example, when the second voltage is applied to the input of the inverter 212, the inverter 212 may output VDD (e.g., 1V), thereby activating the precharge circuit 204 to precharge BL and BLB. Activating the precharge circuit 204 can activate the equalizer (e.g., transistor 302) of the precharge circuit 204, such as, but not limited to, combinations thereof. Figures 3 to 8 As described in at least one of the above. An equalizer can be used to equalize the voltages of BL and BLB, or the voltage of at least one (far end) portion of BL and BLB. The precharge phase can transition to the read or write phase when I / O circuit 112 is ready for a read or write operation.

[0082] During the read or write phase, the memory controller 105 may generate a signal 107 having a first voltage (e.g., 1V). This first voltage can be inverted via inverter 212, such that no voltage is applied to the transistors or switches of the precharge circuit 204 (or a voltage below a voltage threshold is applied), thereby deactivating the precharge operation. The deactivation precharge circuit 204 may include a deactivation equalizer. The read or write operation may be performed simultaneously with or in response to the deactivation precharge circuit 204.

[0083] For example, in order to perform a read operation (e.g., during the read phase), if the memory cell stores a value "1", the voltage at the BLB (e.g., the complementary BL) can decrease and become lower than the voltage at the BL. If the memory cell stores a value "0", the voltage at the BL can decrease and become lower than the voltage at the BLB. The I / O circuitry 112 or other components of the memory device 100 can read the voltages at the BL and / or BLB during the read phase and determine the data stored in the memory cell based on the read voltages.

[0084] In another example, for a write operation (e.g., a write phase), I / O circuitry 112 may apply a data signal corresponding to the data to be written to BL and / or BLB. In some cases, I / O circuitry 112 may receive a signal 107 from memory controller 105 indicating data to be written to BL and / or BLB, allowing I / O circuitry 112 to apply a data signal. Alternatively, other elements of memory device 100 may send signals to I / O circuitry 112 to apply a data signal for writing data to at least one corresponding memory cell. In response to a read or write operation, memory controller 105 may send signal 107 to (re)activate precharge circuitry 204.

[0085] Similar operations can be performed to precharge at least a portion of the FBL and FBLB. For example, at least a portion of the FBL and FBLB can be precharged by a precharge circuit 204 (e.g., a second precharge circuit 204B) in response to receiving a signal 107 (or voltage) from the memory controller 105. The portion precharged by the precharge circuit 204 may include at least the distal or far-side portion of the FBL and FBLB opposite the I / O circuit 112. The FBL and FBLB can be precharged when no data is read from or written to the memory cell. The precharge circuit 204 can deactivate the precharge process of the FBL and FBLB during read or write operations on the memory cells of the memory group 202 (e.g., a second memory group 202B).

[0086] In some configurations, the precharge circuits 204 of BL, BLB, FBL, and FBLB can be activated and deactivated simultaneously. In other configurations, the precharge circuits 204 of BL, BLB, FBL, and FBLB can be activated and deactivated independently, so that the first memory group 202A can be activated when the second memory group 202B is deactivated, and vice versa.

[0087] In some configurations, memory device 100 may include a proximal precharge circuit at the proximal end of the BL. This proximal precharge circuit differs from precharge circuit 204. For example, the proximal precharge circuit may be part of I / O circuitry 112. In another example, the proximal precharge circuit may be positioned along a first lateral direction to intersect I / O circuitry 112 and memory array 120 (or memory group 202). The proximal precharge circuit may be operated by memory controller 105 to precharge the proximal end of the BL. The proximal end of the BL may refer to a portion of the BL adjacent to or close to I / O circuitry 112.

[0088] In some embodiments, memory device 100 may include multiple proximal precharge circuits. For example, similar to precharge circuit 204, memory array 120 may include separate proximal precharge circuits for each memory group 202. In such cases, a first proximal precharge circuit may be physically positioned opposite to the first memory group 202A in a first lateral direction from the first precharge circuit 204A. A second proximal precharge circuit may be physically positioned opposite to the second memory group 202B in the first lateral direction from the second precharge circuit 204B. For example, each of the other proximal precharge circuits may be coupled to memory controller 105 via a control line 208 extending in a second lateral direction. BL and BLB are operatively coupled to the first proximal precharge circuit. FBL and FBLB are operatively coupled to the second proximal precharge circuit. In some other cases, memory device 100 may not include proximal precharge circuits.

[0089] Figure 3 Description of various embodiments Figure 2A schematic diagram 300 of a first example of a far-end bit-line pre-charge circuit (e.g., pre-charge circuit 204A) is shown. Although the examples herein illustrate, for example, a schematic diagram of a pre-charge circuit 204A for pre-charging BL and BLB, the operations or features discussed herein can be applied to other pre-charge circuits 204, such as a pre-charge circuit 204B for pre-charging FBL and FBLB. As shown, schematic diagram 300 illustrates a pre-charge circuit 204 comprising a plurality of transistors 302A-C. Transistors 302A-C may sometimes be referred to as transistor 302 or switch 302. Transistor 302 can operate as a switch. As shown, control line 208 is operatively coupled to the gate (e.g., gate electrode) of transistor 302 for controlling or operating transistor 302.

[0090] Although at least in Figures 3 to 8 Not shown, but control line 208 may include at least an inverter 212 for converting signal 107 from memory controller 105 to precharge circuit 204 or inverting it. In this case, inverter 212 may convert signal 107 or voltage from memory controller 105 to gate of transistor 302. For example, schematic diagram 300 shows an example of precharge circuit 204 for a 4-to-1 multiplexer (MUX4), but precharge circuit 204 may be used for other types of MUXs not limited to MUX4, such as those at least combined with Figures 5 to 6 As described. A precharge circuit 204 can be used at the far end of the BL to increase the efficiency of precharging the BL, where the BL precharge time may be relatively long, depending on the BL resistor (e.g., a large or long metal structure), and to prevent leakage from inactive memory cells. For example, in some cases, the structure, components, or layout of the precharge circuit 204 may be similar to other precharge circuits, such as other far-end precharge circuits 204 or near-end precharge circuits.

[0091] The signal 107 from memory controller 105, after being inverted by inverter 212, can be represented by the BL equalizer B (BLEQB) signal. The BLEQB signal can be used to control transistor 302 to activate or deactivate precharge circuit 204. In one embodiment of this disclosure, transistor 302 is shown as having a specific type (e.g., in this case, a P-type or P-channel MOSFET, PMOS), but the embodiment is not limited thereto, and transistor 302 may be of other types, such as N-type, etc.

[0092] Before a read or write operation, the memory controller 105 can maintain BL and BLB in a predefined state (e.g., high or precharge state, depending on the configuration). To initiate precharge, the memory controller 105 can send a high signal, causing the BLEQB signal (or its inverted signal) to go low. The low BLEQB signal can correspond to a first voltage (e.g., 1V or VDD) applied to the gate electrode of transistor 302. When the first voltage is applied to the gate electrode, source electrode, and drain electrode of transistor 302, transistor 302 can allow current to flow from the source to the drain. Allowing current to flow through transistor 302 can correspond to turning on or activating transistor 302. For example, in response to applying a first voltage at transistors 302B and 302C, the precharge circuit 204 can begin precharging the corresponding BL and BLB. When transistors 302B and 302C are activated, the precharge circuit 204 can set BL and BLB to a predetermined voltage level (e.g., VDD). Transistor 302B can be represented as PBL (e.g., a PMOS transistor associated with BL). Transistor 302C can be represented as PBLB (e.g., a PMOS transistor associated with BLB).

[0093] The precharge circuit 204 may include an equalizer (e.g., denoted as PEQ, such as a PMOS transistor configured as an equalizer) corresponding to transistor 302A. Transistor 302A (e.g., the equalizer) can be used to equalize the voltage between BL and BLB. In some cases, the equalizer may be a circuit or other element used to selectively couple BL and BLB. For the purpose of providing examples herein, the equalizer is implemented as transistor 302A, but the equalizer may be implemented as one or more switches or one or more transistors. In some embodiments, the equalizer may be replaced by different elements capable of performing the functions of the equalizer described herein. In one configuration, the equalizer is coupled to BL and BLB. In some embodiments, similar to transistors 302B and 302C, the equalizer may be controlled according to a BLEQB signal.

[0094] For example, in response to a first voltage (e.g., VDD or 1V) applied to the gate electrode of transistor 302A via the BLEQB signal, an equalizer can be activated / enabled to electrically couple BL to BLB. In another instance, in response to receiving a second voltage (e.g., VSS or 0V) or applying a second voltage to the gate electrode of transistor 302A (or the absence of its voltage), the equalizer can be disabled to electrically decouple BL from BLB. In such cases, by coupling BL and BLB, the voltage between BL and BLB can be equalized to prevent potential malfunctions, such as during read or write operations of memory device 100.

[0095] To perform read or write operations, the precharge circuit 204 can be deactivated. The deactivation precharge circuit 204 may include a deactivation transistor 302 to prevent precharging of BL and BLB, for example, at the distal end of BL. For example, the BLEQB signal may include a second voltage (e.g., VSS or 0V) applied to the gate electrode of transistor 302. A second voltage applied to the gate electrode of transistor 302A decouples BL and BLB. Second voltages applied to the gate electrodes of transistors 302B and 302C disable current flow between the source and drain. Therefore, the precharge circuit 204 can terminate the precharging of BL and BLB, allowing appropriate read or write operations via BL and BLB, including, but not limited to, carrying signals from memory cells to I / O circuit 112 or carrying data signals to be stored in memory cells.

[0096] Figure 4 Description of various embodiments Figure 2 The second example is a schematic diagram 400 of the far-end bit line pre-charge circuit (e.g., pre-charge circuit 204). Figure 4 The pre-charge circuit 204 may include and Figure 3 The components shown may be similar to one or more components, including, but not limited to, transistor 302, a BLEQB signal inverted from signal 107 of the memory controller 105, BL, or a power line or supply (e.g., VDD) for precharging BL and BLB. In this case, the precharge circuit 204 may include power gate control features by adding a header to the precharge circuit 204. The header may include one or more transistors or one or more switches. For the purpose of providing an example, the header may include transistor 402 to provide power gate control features.

[0097] Transistor 402 can be controlled or operated by a control signal (e.g., a power management control (PMCTRL) signal). The PMCTRL signal can be sent by memory controller 105. The PMCTRL signal may be different from the BLEQB signal. Power gate control features can be used to reduce power consumption, improve energy efficiency, or selectively control power. For example, BL and BLB may not be precharged even when transistor 302 is activated or turned on until transistor 402 is activated. The precharge circuit 204 can initiate a precharge process when a first voltage (or a high voltage) is applied to transistors 302 and 402 to form a conductive path between the source and drain terminals and allow current to flow from the power line or power source (e.g., VDD) to BL and BLB. In some cases, the power source may be an internal power source, such as a battery, coupled to memory device 100 or one or more components of memory device 100.

[0098] In some implementations, power gate control features can be used to selectively activate or deactivate different precharge circuits 204. For example, memory controller 105 can send a first PMCTRL signal to first precharge circuit 204A and a second PMCTRL signal to second precharge circuit 204B. As an initial setting (e.g., a predefined state), memory controller 105 can set the first and second PMCTRL signals to a first voltage to activate transistor 402. As part of the predefined state, the BLEQB signal can be set to a first voltage. In this case, first precharge circuit 204A and second precharge circuit 204B can begin precharging individual BLs; for example, first precharge circuit 204A can precharge BL and BLB, while second precharge circuit 204B can precharge FBL and FBLB. In some cases, read or write operations can be performed on one of the memory groups 202 (such as first memory group 202A). In this case, the second PMCTRL signal and the BLEQB signal can be maintained at the first voltage, allowing FBL and FBLB to remain in a pre-charged state. The memory controller 105 can apply the first PMCTRL signal with a second voltage (e.g., 0V) to transistor 402 to turn off the conductive path between the source and drain terminals of transistor 402. Turning off transistor 402 disables current flow between the source and drain terminals of transistor 402, thereby preventing pre-charging of BL and BLB. In response to turning off transistor 402, the memory controller 105 and the I / O circuit 112 can perform read or write operations on the memory cells of the first memory group 202A, and FBL and FBLB can remain in a pre-charged state. Therefore, by utilizing the power gate control feature implemented using transistor 402, the memory device 100 can allow selective pre-charging of one or more BLs (or one or more sets of BLs).

[0099] It should be noted that Figure 4 MUX4 is provided as an example, and other types of MUXs or devices with similar characteristics can be used herein for the pre-charge circuit 204. For example, Figure 5 Description of various embodiments Figure 2 A schematic diagram 500 of a third example of a far-end bitline pre-charge circuit (e.g., pre-charge circuit 204). For example, Figure 5 The pre-charge circuit 204 includes and Figure 4 The pre-charge circuit 204 is similar to one or more components. As shown, an 8-to-1 MUX (MUX8) can be implemented as part of the pre-charge circuit 204. In another example, Figure 6 Description of various embodiments Figure 2 A schematic diagram 600 of the fourth example of a far-end bitline pre-charge circuit (e.g., pre-charge circuit 204). For example, Figure 6 The pre-charge circuit 204 includes and Figures 4 to 5 The precharge circuit 204 may contain one or more similar elements. As shown, a 16-to-1 MUX (MUX16) may be implemented as part of the precharge circuit 204. In various configurations, other elements or devices may be implemented as part of the precharge circuit 204 or the memory device 100 to precharge the far end of the BL.

[0100] Figure 7 Description of various embodiments Figure 2 A schematic diagram 700 of the fifth example of a far-end bitline pre-charge circuit (e.g., pre-charge circuit 204). For example, Figure 7 The pre-charge circuit 204 may include and Figures 2 to 6 The precharge circuit 204 may contain one or more similar elements. As shown, the precharge circuit 204 may include a control line 208 operatively coupled to the gate electrode of the transistor 302 to apply a BLEQB signal. In this case, a P-type crossover structure may be implemented for the precharge circuit 204.

[0101] For example, transistors 702A-B (sometimes referred to as transistor 702) can be implemented as part of a P-type crossover structure. Transistor 702A can be represented as CPBL (e.g., a transistor for a BL in a P-type crossover structure). Transistor 702B can be represented as CPBLB (e.g., a transistor for a BLB in a P-type crossover structure). Transistor 702 can be a P-type transistor, but other types of transistors, such as N-type transistors, may be used herein. The gate electrode of transistor 702A is operatively coupled to the BLB. The gate electrode of transistor 702B is operatively coupled to the BL. In this case, the P-type crossover structure can be used to counteract potential leakage from remaining bit cells (e.g., bit cells not effectively accessed) in the same row of memory array 120 or memory group 202, such as when bit cells store "0" on individual sides of memory array 120.

[0102] For example, before a valid operation (e.g., a read or write operation), the BLEQB signal may be at a first voltage, causing BL and BLB to be in a high-voltage state. During a valid operation, for example, when reading a value from at least one memory cell in a read operation, any unintentional leakage could affect the accuracy of the read via BL or BLB, such as when the stored value is "0". To counteract potential leakage, transistor 702 can be used to keep BL or BLB high (e.g., keeping BL and / or BLB at the first voltage or pre-charge voltage). Keeping BL or BLB at the pre-charge voltage counteracts leakage because the pre-charge voltage compensates for potential charge loss from the memory cell, thus reducing the likelihood of misreads during the data read process. In this case, during a read operation (or write operation), transistor 302 can be deactivated to stop pre-charging BL and BLB, and BL and BLB can be floating. In some cases, an unselected column of the memory cell can cause BL or BLB to discharge, resulting in a differential voltage between BL and BLB. For example, if the BLB is discharging against a voltage and the BL is at a high voltage, transistor 702B can be activated, allowing current to flow to the BLB and thus ensuring that the BLB remains at a high voltage (e.g., a first voltage). Similarly, when leakage from the BL exists and the BLB is at a high voltage, transistor 702A can be activated, allowing current to flow to the BL and thus ensuring that the BL remains at a high voltage. By ensuring that the BL or BLB remains at a high voltage, leakage from the BL or BLB can be counteracted.

[0103] In other instances, to counteract potential leakage and when reading a value "1" from at least one bit cell, the BL can be maintained in a high voltage state, and the BLB can begin to discharge. In this instance, because the BL is in a high voltage state, the CPBLB (e.g., transistor 702B) can be turned off. When the BLB begins to discharge, the CPBL (e.g., transistor 702A) can be turned on. In such cases, the CPBL helps to keep or maintain the BL in a high state to counteract potential leakage from other bit cells on the same row (e.g., those that may be storing a value "0").

[0104] Similar operations or features can be applied to other precharge circuits 204 and BL, such as the second precharge circuit 204B and the corresponding FBL and FBLB. Figure 7 The pre-charge circuit 204 provides a P-type crossover structure for the MUX4 implementation as an example. Other types of MUXs or devices, not limited to the MUX4, such as the MUX8, MUX16, etc., can be implemented.

[0105] Figure 8 Description of various embodiments Figure 2The sixth example is a schematic diagram of the far-end bit line pre-charge circuit, 800. For example, Figure 8 The pre-charge circuit 204 may include and Figures 2 to 7 The pre-charge circuit 204 of at least one of the components is similar to one or more other elements. In this case, another example of a P-type cross structure can be implemented for the pre-charge circuit 204. Figure 8 The P-type crossover structure can be used for write operations, for example, by implementing one or more data buses (e.g., data bus T (DT) and data bus C (DC)) and a row decoder. The data bus and row decoder can be used to control the operation of individual transistors (such as transistors 802A-B controlled by the data bus (e.g., sometimes referred to as transistor 802) and transistors 804A-B controlled by the row decoder (e.g., sometimes referred to as transistor 804)).

[0106] When WL is turned on before writing to the drive (not shown) (e.g., no write-ahead), Figure 8 The P-type crossover structure can keep BL or BLB high (e.g., at a first voltage), in which case virtual fetching may potentially occur. For example, during a write operation with a value of "0", data (e.g., the value "0") can be placed on or provided to BL. In this example, DT can be 0, and DC can be 1. Because DC is 1, transistor 802A can be turned off to allow BL to discharge from the write driver, such as in a main input / output (I / O). For example, setting DT to 0 helps to keep "1" on BLB. In various implementations, additionally or alternatively, Figure 8 The P-type crossover structure can be used with other remote write auxiliary circuitry systems implemented at the far ends of the BL and BLB to increase the minimum voltage (Vmin) for write operations. It can be implemented for other types of MUXs or devices, not limited to the MUX4. Figure 8 The P-shaped cross structure.

[0107] Figure 9 The flowchart of an example method 900 for manufacturing a memory device (e.g., 100) according to some embodiments is described. Method 900 can be performed to form any memory device or part thereof herein. For example, method 900 can be performed to form... Figures 1 to 8 This refers to any memory device or its elements. For example, at least one of the operations of method 900 can be performed to form a memory device (e.g., 100). Therefore, the following discussion of method 900 may be referenced. Figures 1 to 8 Some of the reference numerals used in the drawings are non-limiting examples. Furthermore, method 900 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that... Figure 9Additional operations are provided before, during, and after Method 900, and only a few of these additional operations may be briefly described herein. Method 900 can be performed simultaneously and / or by deleting... Figure 9 Perform in any order other than the order described herein.

[0108] Method 900 may begin with operation 902, which forms a memory array (e.g., 120) in a region of a substrate. The substrate may be a wafer (such as a silicon wafer) or a silicon-on-insulator (SOI) substrate. In some cases, the SOI substrate may include a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on the substrate (typically a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0109] The memory array comprises multiple memory cells. In some instances, each of the memory cells may be implemented as a six-transistor (6T) static random access memory (SRAM) cell consisting of six transistors (e.g., N1, N2, N3, N4, P1, and P2). However, it should be understood that the first through fourth memory cells may be implemented as other types of SRAM configurations besides 6T, such as eight-transistor (8T) or ten-transistor (10T) configurations. In some instances, alternatively or additionally, the memory cells may be implemented as other types of memory cells, such as (e.g.) dynamic random access memory (DRAM) cells, resistive random access memory (RRAM) cells, phase-change random access memory (PCRAM) cells, or magnetoresistive random access memory (MRAM) cells. In various embodiments, memory cells may be formed along the main (e.g., front) surface of the substrate. The fabrication of these memory cells (and corresponding memory arrays) is sometimes referred to as front-end-of-line (FEOL) processing.

[0110] In some configurations, a memory array may comprise multiple portions of memory cells, such as a first portion and a second portion. The first portion of the memory array may comprise multiple first memory cells. The second portion of the memory array may comprise multiple second memory cells. The first portion may correspond to a first memory group (e.g., 202A), while the second portion may correspond to a second memory group (e.g., 202B).

[0111] In operation 904, method 900 may include forming I / O circuitry (e.g., 112). The I / O circuitry may be along a first lateral direction (e.g., as in combination). Figure 2 The described vertical direction or as combined Figure 1 The described horizontally oriented entity is positioned adjacent to the memory array. I / O circuitry may be operatively coupled to a first portion (e.g., a first memory bank) via / by means of a first access line. I / O circuitry may be operatively coupled to a second portion (e.g., a second memory bank) via a second access line. In this case, the first access line may refer to BL (e.g., 206A), and the second access line may refer to FBL (e.g., 206C).

[0112] Each memory cell from a portion of the memory array may be coupled to each other via separate access lines. For example, a plurality of first memory cells may be coupled to each other via first access lines. A plurality of second memory cells may be coupled to each other via second access lines. In some configurations, additional access lines may be present to couple I / O circuitry to the respective portions of the memory array. For example, in addition to the first access lines, a third access line (e.g., 206B, refer to BLB) may be formed, which physically extends along a first lateral direction and is operatively coupled to the first portion, the I / O circuitry, and the first precharge circuitry. In addition to the second access lines, a fourth access line (e.g., 206D, refer to FBLB) may be formed, which physically extends along the first lateral direction and is operatively coupled to the second portion, the I / O circuitry, and the second precharge circuitry. The first and third access lines may operate as a pair of BLs for performing read or write operations on the plurality of first memory cells. Similarly, the second and fourth access lines can operate as a pair of BLs for performing read or write operations on multiple second memory cells.

[0113] The I / O circuitry may include one or more hardware elements for accessing one or more memory cells of a memory array via a first access line, a second access line, or at least one of other access lines. The I / O circuitry may access the memory cells to perform read or write operations, for example, based on signals from a memory controller (e.g., 105). For instance, the I / O circuitry may send a signal corresponding to data for writing to at least one memory cell. In another example, the I / O circuitry may be used to read a voltage or current corresponding to data stored in a memory cell via at least one of the first or second access lines. The I / O circuitry may perform similar operations using third and fourth access lines, respectively, for accessing memory cells in a first and a second portion.

[0114] In operation 906, method 900 may include forming a first precharge circuit (e.g., 204A). The first precharge circuit may be disposed opposite to the I / O circuitry and the first portion of the entity along a first lateral direction. The first precharge circuit may be used to charge a first access line (and a third access line) to a supply voltage before accessing a first memory cell.

[0115] In operation 908, method 900 may include forming a second precharge circuit. The second precharge circuit may include elements or features similar to those of the first precharge circuit. In some cases, the second precharge circuit may include elements or features different from those of the first precharge circuit, such as additional or alternative elements (e.g., transistors, switches, or functionalities). The second precharge circuit may be disposed opposite to the first precharge circuit and the second portion of the entity along a first lateral direction. The second precharge circuit can be used to charge at least a portion of the second access lines (and fourth access lines) to a supply voltage before accessing a plurality of second memory cells. For example, a portion of the second access lines (and fourth access lines) may include a distal portion or segment opposite to the proximal end of the second access line coupled to I / O circuitry.

[0116] In some configurations, a precharge circuit (e.g., a first precharge circuit and / or a second precharge circuit) may include one or more transistors (e.g., 302B, 302C) that operate as switches for charging individual access lines (e.g., initiating precharge of individual access lines). For example, a first precharge circuit may include a transistor (e.g., 302B, sometimes referred to as the first transistor) comprising a first source / drain (S / D) electrode, a second S / D electrode, and a gate electrode. The first S / D electrode is operatively coupled to a first access line. The second S / D electrode is operatively coupled to a power supply (e.g., VDD or 1V). The gate electrode may be coupled to a control line (e.g., 208) (or multiple control lines) for transmitting signals (e.g., high or low voltage). By applying a high voltage at the gate electrode, the transistor can be turned on, thereby allowing the first access line to be precharged to a supply voltage (e.g., a predefined voltage level) according to the voltage applied at the gate electrode (e.g., the gate voltage).

[0117] Similar operation can be applied to a second pre-charge circuit. For example, the second pre-charge circuit may include a transistor (e.g., 302C, sometimes referred to as the second transistor) that operates as a switch for, for example, pre-charging the second access line to the supply voltage based on the gate voltage. In some configurations, the transistor may be a P-channel MOSFET (PMOS) transistor, but other types of transistors, such as N-type transistors, can be implemented, but not limited to PMOS transistors.

[0118] In some implementations, a control line (e.g., 208) is operatively coupled to a memory controller or other means capable of sending signals to initiate or terminate precharging of the access line. The control line may be in a second lateral direction (e.g., as in conjunction with...) Figure 2 The described horizontal direction or as combined Figure 1The control line extends partially in the described vertical direction and is operatively coupled to at least one of a first precharge circuit or a second precharge circuit. For example, the memory device may include a first control line extending in a second lateral direction perpendicular to the first lateral direction and operatively coupled to the first precharge circuit. The memory device may include a second control line extending in the second lateral direction and operatively coupled to the second precharge circuit. The first and second control lines may be operatively coupled to each other via a third control line extending in the first lateral direction. In some cases, the first, second, or third control line may refer to a portion or segment of a single control line (e.g., 208).

[0119] Signals transmitted via control lines can be used to initiate or terminate the (pre)charging of at least one of the first or second access lines to the supply voltage. In some cases, the control lines may include buffers and inverters. For example, referring to different portions of control lines (e.g., a first control line operatively coupled to a first pre-charging circuit and a second control line operatively coupled to a second pre-charging circuit), each of the first and second control lines may include a separate buffer and inverter. The first control line may include a first buffer and a first inverter disposed thereon. The second control line may include a second buffer and a second inverter disposed thereon. In such cases, transmitting a low signal (e.g., VSS or 0V) via the control lines can initiate the (pre)charging of at least one of the first or second access lines to the supply voltage.

[0120] In some configurations, the pre-charge circuit may include an equalizer. The equalizer may include or correspond to at least one transistor (e.g., 302A) or switch for equalizing the charge between a pair of access lines to the supply voltage, such as equalizing the voltage across BL. The equalizer may be included together with other switches (e.g., transistors 302B, 302C) for activating or deactivating the pre-charge of the access lines.

[0121] For example, each precharge circuit may include three transistors, such as a first transistor (e.g., 302B), a second transistor (e.g., 302C), and a third transistor (e.g., 302A). Taking the first precharge circuit as an example, although similar components may be used in the second precharge circuit, the first, second, and third transistors are operatively coupled between at least one of a control line (e.g., 208), a supply voltage (e.g., VDD, sometimes referred to as a power supply or power line), and / or an access line. The first transistor may include a first S / D electrode operatively coupled to a first access line, a second S / D electrode operatively coupled to the supply voltage, and a first gate electrode operatively coupled to the control line. The second transistor may include a third S / D electrode operatively coupled to a third access line, a fourth S / D electrode operatively coupled to the supply voltage, and a second gate electrode operatively coupled to the control line. The third transistor may include a fifth S / D electrode operably coupled to the first access line, a sixth S / D electrode operably coupled to the third access line, and a third gate electrode operably coupled to a control line. The third transistor may operate as an equalizer, while the first and second transistors may operate as switches for activating or deactivating precharge. The second precharge circuit may include similar elements configured to precharge the second and fourth access lines.

[0122] In some configurations, the memory device may include a control transistor (e.g., 402) as part of each precharge circuit. The control transistor can be used to control the power supply (e.g., from an internal power source (e.g., VDD)) to one or more components of the precharge circuit. For example, the control transistor is operatively coupled between the supply voltage and each pair of transistors (e.g., 302B, 302C), each pair of transistors being used to charge a first access line and a third access line or a second access line and a fourth access line to the supply voltage. The control transistor may include a first S / D electrode, a second S / D electrode, and a gate electrode. The first S / D electrode may be coupled to one or more switches (e.g., 302B, 302C). The second S / D electrode may be coupled to a power source (e.g., VDD). The gate electrode may be coupled to a signal line, which may be different from, for example, control line 208. For example, the control transistor may include or be configured with a power gate control feature to allow or prevent the access lines from being precharged to the supply voltage. An internal power supply can be used to (pre-)charge at least one of the access lines to the supply voltage, depending at least on the state of the transistor. For example, if the control transistor is in an active state (e.g., activated), the pair of access lines can be pre-charged to the supply voltage, for example, based on the BLEQB signal of a switch (e.g., 302B, 302C). In another example, if the control transistor is in an inactive state (e.g., deactivated), the pair of access lines may not be pre-charged. For example, the control transistor can be controlled via a signal from the memory controller. The signal used to control the control transistor (e.g., 402) may be different from the signal used to control the switches and / or equalizers (e.g., 302A-C).

[0123] In some embodiments, the first precharge circuit (or second precharge circuit) may include a first transistor (e.g., 702A) and a second transistor (e.g., 702B). Each transistor may include a first S / D electrode, a second S / D electrode, and a gate electrode. For example, the first S / D electrode of the first transistor is coupled to a first access line. The second S / D electrode of the first transistor is coupled to a power supply (e.g., VDD). The gate electrode of the first transistor is coupled to a third access line (e.g., BLB). Additionally, the first S / D electrode of the second transistor is coupled to a third access line. The second source / drain electrode of the second transistor is coupled to a power supply. The gate electrode of the second transistor is coupled to the first access line. For example, the transistors provided herein may serve as part of a P-type crossover structure. In various configurations, the memory device discussed herein may include additional or alternative elements, not limited to those discussed herein for operation with the remote precharge circuit.

[0124] One embodiment of this disclosure discloses a memory circuit. The memory circuit includes a memory array comprising a first portion and a second portion, wherein the first portion includes a plurality of first memory cells, and the second portion includes a plurality of second memory cells. The memory circuit includes input / output (I / O) circuitry physically disposed adjacent to the memory array along a first lateral direction, wherein the I / O circuitry is coupled to the first portion and the second portion via first access lines and second access lines, respectively. The memory circuit includes a first precharge circuitry physically disposed opposite the I / O circuitry to the first portion along the first lateral direction, and for charging the first access lines to a supply voltage before accessing the plurality of first memory cells. The memory circuit includes a second precharge circuitry physically disposed opposite the second portion along the first lateral direction, and for charging at least a portion of the second access lines to the supply voltage before accessing the plurality of second memory cells.

[0125] In some embodiments, the memory circuitry includes a memory array comprising a first portion and a second portion, wherein the first portion includes a plurality of first memory cells, and the second portion includes a plurality of second memory cells. The memory circuitry includes input / output circuitry physically disposed adjacent to the memory array along a first lateral direction, wherein the input / output circuitry is coupled to the first portion and the second portion via a first access line and a second access line, respectively. The memory circuitry includes a first precharge circuitry physically disposed opposite to the first portion along the first lateral direction from the I / O circuitry. The memory circuitry includes a second precharge circuitry physically disposed opposite to the second portion along the first lateral direction from the first precharge circuitry.

[0126] In some embodiments, the memory circuitry includes a first control line and a second control line. The first control line extends in a second lateral direction perpendicular to the first lateral direction and is coupled to a first precharge circuit. The second control line extends in the second lateral direction and is coupled to a second precharge circuit, wherein the first control line is coupled to the second control line via a third control line extending in the first lateral direction.

[0127] In some embodiments, the memory circuit further includes a first buffer, a first inverter, a second buffer, and a second inverter. The first buffer is disposed in a first control line. The first inverter is disposed in a first control line. The second buffer is disposed in a second control line.

[0128] In some embodiments, the first precharge circuit includes a first transistor that operates as a switch for charging a first access line to a supply voltage according to a gate voltage; and / or the second precharge circuit includes a second transistor that operates as a switch for charging a second access line to a supply voltage according to a gate voltage.

[0129] In some embodiments, the first transistor and the second transistor are each P-channel MOSFET transistors.

[0130] In some embodiments, the input / output circuitry is coupled to the first portion via a first access line and a third access line, and wherein the input / output circuitry is coupled to the second portion via a second access line and a fourth access line.

[0131] In some embodiments, a first pre-charge circuit includes a first transistor, a second transistor, and a third transistor; and / or a second pre-charge circuit includes a first transistor, a second transistor, and a third transistor. The first transistor in the first pre-charge circuit includes a first source / drain electrode coupled to a first access line, a second source / drain electrode coupled to a supply voltage, and a first gate electrode coupled to a control line. The second transistor in the first pre-charge circuit includes a third source / drain electrode coupled to a third access line, a fourth source / drain electrode coupled to a supply voltage, and a second gate electrode coupled to a control line. The third transistor in the first pre-charge circuit includes a fifth source / drain electrode coupled to a first access line, a sixth source / drain electrode coupled to a third access line, and a third gate electrode coupled to a control line. The first transistor in the second pre-charge circuit includes a first source / drain electrode coupled to a second access line, a second source / drain electrode coupled to a supply voltage, and a first gate electrode coupled to a control line. The second transistor in the second pre-charge circuit includes a third source / drain electrode coupled to a fourth access line, a fourth source / drain electrode coupled to a supply voltage, and a second gate electrode coupled to a control line. The second precharge circuit includes a third transistor comprising a fifth source / drain electrode coupled to a second access line, a sixth source / drain electrode coupled to a fourth access line, and a third gate electrode coupled to a control line.

[0132] In some embodiments, the memory circuitry further includes control transistors coupled between a supply voltage and each pair of transistors, each pair of transistors being configured to charge the first access line and the third access line or the second access line and the fourth access line to the supply voltage.

[0133] In some embodiments, the first access line extends from the input / output circuit to the first precharge circuit and is disposed in the first metallization layer, while the second access line extends from the input / output circuit to the second precharge circuit and includes a first segment and a second segment, wherein the first segment is disposed in the second metallization layer and the second segment is disposed in the first metallization layer.

[0134] In some embodiments, the second metallization layer is disposed above the first metallization layer.

[0135] In some embodiments, the first pre-charge circuit includes a first transistor and a second transistor. The first source / drain electrode of the first transistor is coupled to a first access line, the second source / drain electrode of the first transistor is coupled to a power supply, and the gate electrode of the first transistor is coupled to a third access line. The second source / drain electrode of the second transistor is coupled to the third access line, the second source / drain electrode of the second transistor is coupled to a power supply, and the gate electrode of the second transistor is coupled to the first access line.

[0136] In another embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes a memory array comprising a first portion and a second portion, wherein the first portion includes a plurality of first memory cells coupled to each other via first bit lines, and the second portion includes a plurality of second memory cells coupled to each other via second bit lines, wherein the first bit lines extend along a first lateral direction, and the second bit lines include at least a portion extending along the first lateral direction. The memory circuit includes a first precharge circuit physically disposed adjacent to the first portion along the first lateral direction, wherein the first precharge circuit is used to charge the first bit lines to a logic high state before accessing the plurality of first memory cells. The memory circuit includes a second precharge circuit physically disposed adjacent to the second portion along the first lateral direction, wherein the second precharge circuit is used to charge the second bit lines to a logic high state before accessing the plurality of second memory cells.

[0137] In some embodiments, the memory circuit includes a memory array comprising a first portion and a second portion, wherein the first portion includes a plurality of first memory cells coupled to each other via first bit lines, and the second portion includes a plurality of second memory cells coupled to each other via second bit lines, wherein the first bit lines extend along a first lateral direction, and the second bit lines include at least a portion extending along the first lateral direction. The memory circuit includes a first precharge circuit physically disposed adjacent to the first portion along the first lateral direction. The memory circuit includes a second precharge circuit physically disposed adjacent to the second portion along the first lateral direction.

[0138] In some embodiments, the first bit line extends to the first pre-charge circuit and is disposed in the first metallization layer, while the second bit line extends to the second pre-charge circuit and includes a first segment and a second segment, wherein the first segment is disposed in the second metallization layer and the second segment is disposed in the first metallization layer.

[0139] In some embodiments, the second metallization layer is disposed above the first metallization layer.

[0140] In some embodiments, the memory circuitry includes a first control line and a second control line. The first control line extends in a second lateral direction perpendicular to the first lateral direction and is coupled to a first precharge circuit. The second control line extends in the second lateral direction and is coupled to a second precharge circuit, wherein the first control line is coupled to the second control line via a third control line extending in the first lateral direction.

[0141] In some embodiments, the memory circuit further includes a first buffer, a first inverter, a second buffer, and a second inverter. The first buffer is disposed in a first control line. The first inverter is disposed in a first control line. The second buffer is disposed in a second control line. The second inverter is disposed in a second control line.

[0142] In some embodiments, the first precharge circuit includes a first transistor that operates as a switch for charging a first bit line to the logic high state according to a gate voltage; and / or the second precharge circuit includes a second transistor that operates as a switch for charging a second bit line to the logic high state according to a gate voltage.

[0143] In another embodiment of this disclosure, a method for forming a memory device is disclosed. The method includes: forming a memory array including a first portion and a second portion, wherein the first portion includes a plurality of first memory cells, and the second portion includes a plurality of second memory cells. The method includes: forming input / output (I / O) circuitry physically disposed adjacent to the memory array along a first lateral direction, wherein the I / O circuitry is coupled to the first portion and the second portion via first access lines and second access lines, respectively. The method includes: forming a first precharge circuitry physically disposed opposite the I / O circuitry and the first portion along the first lateral direction, and for charging the first access lines to a supply voltage before accessing the plurality of first memory cells. The method includes: forming a second precharge circuitry physically disposed opposite the second portion along the first lateral direction, and for charging at least a portion of the second access lines to a supply voltage before accessing the plurality of second memory cells.

[0144] In some embodiments, the method includes the following steps: forming a third access line that physically extends along a first lateral direction and is coupled to a first portion, an input / output circuit, and a first precharge circuit; and forming a fourth access line that physically extends along the first lateral direction and is coupled to a second portion, an input / output circuit, and a second precharge circuit.

[0145] In another embodiment of this disclosure, a memory device is disclosed. The memory device includes a memory array, input / output (I / O) circuitry, a first precharge circuit, a second precharge circuit, a third access line, and a fourth access line. The memory array includes a first portion and a second portion, wherein the first portion includes a plurality of first memory cells, and the second portion includes a plurality of second memory cells. Input / output circuitry, physically disposed adjacent to the memory array along a first lateral direction, is coupled to the first portion and the second portion via the first access line and the second access line, respectively. The first precharge circuitry is physically disposed opposite to the I / O circuitry and the first portion along the first lateral direction. The second precharge circuitry is physically disposed opposite to the second portion along the first lateral direction. The third access line extends physically along the first lateral direction and is coupled to the first portion, the input / output circuitry, and the first precharge circuitry. The fourth access line extends physically along the first lateral direction and is coupled to the second portion, the input / output circuitry, and the second precharge circuitry.

[0146] In some embodiments, a first pre-charge circuit includes a first transistor, a second transistor, and a third transistor; and / or a second pre-charge circuit includes a first transistor, a second transistor, and a third transistor. The first transistor in the first pre-charge circuit includes a first source / drain electrode coupled to a first access line, a second source / drain electrode coupled to a supply voltage, and a first gate electrode coupled to a control line. The second transistor in the first pre-charge circuit includes a third source / drain electrode coupled to a third access line, a fourth source / drain electrode coupled to a supply voltage, and a second gate electrode coupled to a control line. The third transistor in the first pre-charge circuit includes a fifth source / drain electrode coupled to a first access line, a sixth source / drain electrode coupled to a third access line, and a third gate electrode coupled to a control line. The first transistor in the second pre-charge circuit includes a first source / drain electrode coupled to a second access line, a second source / drain electrode coupled to a supply voltage, and a first gate electrode coupled to a control line. The second transistor in the second pre-charge circuit includes a third source / drain electrode coupled to a fourth access line, a fourth source / drain electrode coupled to a supply voltage, and a second gate electrode coupled to a control line. The second precharge circuit includes a third transistor comprising a fifth source / drain electrode coupled to a second access line, a sixth source / drain electrode coupled to a fourth access line, and a third gate electrode coupled to a control line.

[0147] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of this subject. Based on a particular technology node, the term “about” may indicate the value of a given quantity that varies, for example, within 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0148] As used herein, the terms “about” and “approximately” generally indicate the value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of this subject. Based on a particular technology node, the term “about” may indicate the value of a given quantity that varies, for example, within 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0149] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of an embodiment disclosed herein. Those skilled in the art will understand that they can readily use an embodiment disclosed herein as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of an embodiment disclosed herein, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of an embodiment disclosed herein.

Claims

1. A memory circuit, characterized in that, include: A memory array includes a first part and a second part, wherein the first part includes a plurality of first memory cells and the second part includes a plurality of second memory cells; An input / output circuit is physically disposed next to the memory array along a first lateral direction, wherein the input / output circuit is coupled to the first portion and the second portion via a first access line and a second access line, respectively. A first pre-charge circuit is disposed along the first lateral direction opposite to the input / output circuit and the first part of the entity; and A second pre-charge circuit is disposed opposite to the first pre-charge circuit and the second part of the entity along the first lateral direction.

2. The memory circuit as described in claim 1, characterized in that, include: A first control line extends in a second lateral direction perpendicular to the first lateral direction and is coupled to the first pre-charge circuit. A second control line extends in the second lateral direction and is coupled to the second pre-charge circuit. The first control line is coupled to the second control line via a third control line extending in the first lateral direction; A first buffer is provided in the first control line; A first inverter is provided in the first control line; A second buffer is disposed in the second control line; and A second inverter is provided in the second control line.

3. The memory circuit as described in claim 1, characterized in that, At least one of the following: The first pre-charge circuit includes a first transistor; or The second precharge circuit includes a second transistor, wherein the first transistor and the second transistor are each a P-channel MOSFET transistor.

4. The memory circuit as described in claim 1, characterized in that, The input / output circuit is coupled to the first part via the first access line and a third access line, and the input / output circuit is coupled to the second part via the second access line and a fourth access line.

5. The memory circuit as described in claim 4, characterized in that, At least one of the following: The first pre-charge circuit includes: A first transistor includes a first source / drain electrode coupled to the first access line, a second source / drain electrode coupled to a supply voltage, and a first gate electrode coupled to a control line; A second transistor includes a third source / drain electrode coupled to the third access line, a fourth source / drain electrode coupled to the supply voltage, and a second gate electrode coupled to the control line; and A third transistor includes a fifth source / drain electrode coupled to the first access line, a sixth source / drain electrode coupled to the third access line, and a third gate electrode coupled to the control line; or The second pre-charge circuit includes: A first transistor includes a first source / drain electrode coupled to the second access line, a second source / drain electrode coupled to the supply voltage, and a first gate electrode coupled to a control line; A second transistor includes a third source / drain electrode coupled to the fourth access line, a fourth source / drain electrode coupled to the supply voltage, and a second gate electrode coupled to the control line; and A third transistor includes a fifth source / drain electrode coupled to the second access line, a sixth source / drain electrode coupled to the fourth access line, and a third gate electrode coupled to the control line. The memory circuit further includes a control transistor coupled between the supply voltage and each pair of transistors, each pair of transistors being used to charge the first access line and the third access line or the second access line and the fourth access line to the supply voltage.

6. The memory circuit as described in claim 1, characterized in that, The first access line extends from the input / output circuit to the first precharge circuit and is disposed in a first metallization layer, while the second access line extends from the input / output circuit to the second precharge circuit and includes a first segment and a second segment, wherein the first segment is disposed in a second metallization layer and the second segment is disposed in the first metallization layer, and wherein the second metallization layer is disposed above the first metallization layer.

7. The memory circuit as described in claim 1, characterized in that, The first pre-charge circuit includes a first transistor and a second transistor. The first transistor has a first source / drain electrode coupled to the first access line, a second source / drain electrode coupled to a power supply, and a gate electrode coupled to a third access line. The second transistor has a first source / drain electrode coupled to the third access line, a second source / drain electrode coupled to the power supply, and a gate electrode coupled to the first access line.

8. A memory circuit, characterized in that, include: A memory array includes a first portion and a second portion, wherein the first portion includes a plurality of first memory cells coupled to each other via a first bit line, and the second portion includes a plurality of second memory cells coupled to each other via a second bit line, wherein the first bit line extends along a first lateral direction, and the second bit line includes at least a portion extending along the first lateral direction. A first pre-charging circuit is physically disposed alongside the first portion along the first lateral direction; and A second pre-charging circuit is physically disposed next to the second portion along the first lateral direction.

9. The memory circuit as described in claim 8, characterized in that, The first bit line extends to the first pre-charge circuit and is disposed in a first metallization layer, while the second bit line extends to the second pre-charge circuit and includes a first segment and a second segment, wherein the first segment is disposed in a second metallization layer, and the second segment is disposed in the first metallization layer, and wherein the second metallization layer is disposed above the first metallization layer.

10. A memory device, characterized in that, include: A memory array includes a first part and a second part, wherein the first part includes a plurality of first memory cells and the second part includes a plurality of second memory cells; An input / output circuit is physically disposed next to the memory array along a first lateral direction, wherein the input / output circuit is coupled to the first portion and the second portion via a first access line and a second access line, respectively. A first pre-charge circuit is disposed along the first lateral direction opposite to the input / output circuit and the first portion of the entity; A second pre-charge circuit is disposed along the first lateral direction opposite to the first pre-charge circuit and the second part of the entity; A third access line extends substantially along the first lateral direction and is coupled to the first portion, the input / output circuit and the first precharge circuit; and A fourth access line extends substantially along the first lateral direction and is coupled to the second portion, the input / output circuit, and the second precharge circuit.

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