Multi-channel analog signal high-precision synchronous sampling device

Abstract

The utility model provides a multi-channel analog signal high-precision synchronous sampling device, which comprises an acquisition module and a control communication module, the acquisition module comprises a plurality of multi-channel synchronous sampling ADCs, and the control communication module comprises an FPGA master controller; one of the multiple multi-channel synchronous sampling ADCs is a master ADC, the other multi-channel synchronous sampling ADCs are slave ADCs, the master ADC is configured to be in an internal reference voltage output mode, the slave ADCs are configured to be in an external reference mode, and reference voltage of the master ADC is led out from a REFOUT pin of the master ADC and connected to a REFIN pin of each slave ADC; the plurality of multi-channel synchronous sampling ADCs work in a parallel interface mode, data buses of the plurality of multi-channel synchronous sampling ADCs are connected with the FPGA master controller in a parallel mode, and bus arbitration is carried out through CS signals. According to the technical scheme, the technical problems that in the prior art, an existing multi-channel sampling device is large in sampling time error, a channel switching circuit is complex, and the matching degree between channels is poor are solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to data processing technical field especially relates to a kind of multi-channel analog signal high-precision synchronous sampling device. BACKGROUND

[0002] Multi-channel analog signal sampling system can transmit a large number of sampling data to central processing unit or storage unit in real time for analysis and storage, and is widely used in industrial field. For example, in aircraft flight test, multiple channels and multiple sensors need to be collected in real time. These signals may include acceleration, pressure, temperature, strain and vibration. The collected multi-dimensional data not only requires high precision and low delay, but also needs to ensure the time synchronization between channels. Small time deviation may cause phase shift between high-speed signals, leading to signal distortion or misjudgment. With the increasing demand for high-precision measurement, how to balance the number of sampling channels and synchronous sampling performance, and reduce the sampling error between channels under the premise of ensuring high precision is a great challenge in the field of sensor testing.

[0003] Traditional multi-channel / multi-chip analog sampling system is based on two architectures: one part of the system uses a single-chip ADC chip plus a switch array to simulate a real multi-channel sampling system; another part of the system uses multiple ADC chips and cascades / parallels them using SPI / IIC bus protocol to realize multi-channel sampling.

[0004] Patent CN202411016966.4 proposes a multi-channel sampling device using "switch matrix + single-chip ADC" signal processing architecture, i.e. using single-chip ADC for multi-channel signal acquisition. Several input signals are connected to ADC input channels through switch matrix in sequence, and ADC performs multi-channel acquisition in sequence. The sampling system using this method has a sampling interval of only ADC hold time + conversion time between adjacent two channels in ideal case. However, in actual situation, multi-channel analog switch switching takes several microseconds to several milliseconds, and there is a large deviation in sampling time of each channel. In actual equipment, ADC sampling rate needs to be increased, and high oversampling is used to reduce ADC conversion time and conversion delay between channels. Due to the existence of transmission line distributed capacitance and distributed inductance, signal path is in transient state for a period of time after switching, which may cause overshoot, glitch and other phenomena, seriously affecting sampling accuracy. In actual circuit, RC absorption and impedance matching circuit need to be designed for the signals to be sampled. This kind of circuit has poor universality, difficult to debug, and causes many inconveniences to circuit design.

[0005] A multi-channel analog signal sampling method is proposed in patent CN202010115520.2. Low-speed ADC chips based on standard communication interfaces such as SPI / IIC usually do not have a separate sampling trigger pin, but send a sampling start command to them through the data bus. Since the traditional single-chip microcomputer instructions are executed sequentially, the sampling start command can only be sent to multiple ADCs in succession, which seriously affects the sampling synchronization between the ADCs.

[0006] In addition, although such analog sampling systems containing multiple ADC chips can achieve true multi-channel sampling and eliminate time errors and signal distortion caused by channel switching, the reference source mismatch problem exists in such systems due to the presence of multiple independent ADC chips. The difference in reference sources between multiple ADCs directly affects the data matching between channels. There are usually two ways to configure the reference source of the ADC chip in such sampling systems: one is the independent reference source mode, that is, each ADC uses an independent built-in / external reference source. In this way, due to the physical differences of the reference source chips, the reference voltages used by each ADC are different, and the matching between the chips is poor. For sensor sampling systems, the sampling error caused by the poor matching must be compensated by post-correction, which challenges the system software design and increases the complexity of the system operation. The other way to handle the reference source is the external unified reference source mode, that is, a piece of external reference source chip provides reference voltage for multiple ADCs synchronously. In this way, each ADC can obtain a more accurate and consistent reference voltage, but the external reference source chip is required to be high in this method. If a common reference chip is used, its output voltage accuracy is lower than that of the ADC built-in reference, which reduces the system sampling accuracy. To achieve high-precision and high-matching sampling, expensive high-precision reference source chips are required, which puts great cost pressure on the design. Practical new type content

[0007] The utility model provides a kind of multi-channel analog signal high-precision synchronous sampling device, can solve the technical problems of large sampling time error, channel switching circuit complex and poor matching between channels in prior art multi-channel sampling device.

[0008] According to an aspect of the utility model, a kind of multi-channel analog signal high-precision synchronous sampling device is provided, device includes acquisition module and control communication module, acquisition module includes multiple multi-channel synchronous sampling ADC, control communication module includes FPGA master control;

[0009] One of the multiple pieces of the multi-channel synchronous sampling ADC is a master ADC, and the rest of the multi-channel synchronous sampling ADCs are slave ADCs, the master ADC is configured in an internal reference voltage output mode, and the slave ADCs are configured in an external reference mode, the reference voltage of the master ADC is led out from a self-REFOUT pin and connected to a REFIN pin of each slave ADC;

[0010] The multiple pieces of the multi-channel synchronous sampling ADCs all work in a parallel interface mode, a data bus of the multiple pieces of the multi-channel synchronous sampling ADCs is connected to an FPGA master in parallel, and bus arbitration is performed through a CS signal.

[0011] Further, each piece of the multi-channel synchronous sampling ADC includes a control unit, multiple independent analog front ends, multiple independent T / H components, a CONVST signal pin, a MUX and a SARADC, the multiple analog front ends are connected to the multiple T / H components one by one, the T / H components are connected to the CONVST signal pin, the control unit is connected to the CONVST signal pin, the MUX and the SARADC respectively, and the MUX is connected to the T / H components and the SARADC respectively.

[0012] Further, the CONVST signal pins of all the multi-channel synchronous sampling ADCs are connected together and connected to the FPGA master, and all the CONVST signal pins are driven by a global trigger signal generated by the FPGA master.

[0013] Further, the length, wiring mode and impedance of the signal lines between the CONVST signal pin of each piece of the multi-channel synchronous sampling ADC and the FPGA master are consistent.

[0014] Further, the signal lines include an FPGA internal delay line and an FPGA external control line.

[0015] Further, the multiple pieces of the multi-channel synchronous sampling ADCs and the FPGA master adopt a symmetrical layout.

[0016] Further, each piece of the multi-channel synchronous sampling ADC is correspondingly provided with an independent board card.

[0017] The technical scheme of the utility model provides a kind of multi-channel analog signal high-precision synchronous sampling device, the device uses multiple pieces of built-in on-chip synchronous sampling function ADC, one piece is used as main ADC, the rest is used as slave ADC, through series connection multiple reference sources, utilize main ADC internal reference drive multiple slave ADC external reference, can realize good matching between channel and reduce cost, by connecting the data bus of multiple multi-channel synchronous sampling ADC in parallel with the FPGA master control, and through CS signal bus arbitration, cascade bus is realized, and then high time precision synchronous sampling of multi-channel analog signal direct connection ADC can be realized, improve the synchronism of multi-channel sampling, and enhance the scalability of system. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings included to provide a further understanding of the embodiments of the utility model, constitute part of the specification, for illustrating the embodiments of the utility model, and with the text description to explain the principle of the utility model. Obviously, the drawings in the following description only some embodiments of the utility model, for those skilled in the art, without creative effort, according to these drawings, other drawings can also be obtained.

[0019] Figure 1 The equipment composition block diagram of multi-channel analog signal high-precision synchronous sampling device provided according to the specific embodiment of the utility model is shown;

[0020] Figure 2 The reference voltage connection schematic diagram provided according to the specific embodiment of the utility model is shown;

[0021] Figure 3 The internal structure schematic diagram of multi-channel synchronous sampling ADC provided according to the specific embodiment of the utility model is shown;

[0022] Figure 4 The connection relationship schematic diagram of ADC and FPGA provided according to the specific embodiment of the utility model is shown. DETAILED DESCRIPTION

[0023] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other in the case of no conflict. The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The description of the at least one exemplary embodiment is actually only illustrative, but not as any limitation on the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0024] It should be noted that the terms used herein are only intended to describe specific embodiments, and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and it should also be understood that when the terms "comprise" and / or "include" are used in the specification, there is a feature, step, operation, device, component and / or combination thereof.

[0025] Unless specifically stated otherwise, the relative arrangement of components and steps, numerical expressions, and numerical values set forth in the embodiments are not meant to limit the scope of the present application. At the same time, it should be understood that the sizes of the various parts shown in the drawings are not drawn in accordance with the actual proportion relationship. The technology, method and equipment known to those skilled in the art can not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as part of the authorized specification. In all examples shown and discussed herein, any specific value should be interpreted as merely exemplary, and not as a limitation. Therefore, other examples of exemplary embodiments can have different values. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0026] As Figure 1 and Figure 2 According to the specific embodiments of the present application, a multi-channel analog signal high-precision synchronous sampling device is provided, which comprises a collection module and a control communication module. The collection module comprises a plurality of multi-channel synchronous sampling ADCs, and the control communication module comprises an FPGA master control.

[0027] In a multi-channel synchronous sampling ADC, one of the chips is the master ADC, and the other multi-channel synchronous sampling ADCs are slave ADCs. The master ADC is configured with internal reference voltage output mode, and the slave ADCs are configured with external reference mode. The reference voltage of the master ADC is led out from its own REFOUT pin and connected to the REFIN pin of each slave ADC.

[0028] All multi-chip, multi-channel synchronous sampling ADCs operate in parallel interface mode. The data buses of the multi-chip, multi-channel synchronous sampling ADCs are connected to the FPGA main controller in parallel and bus arbitration is performed through the CS signal.

[0029] This configuration provides a high-precision synchronous sampling device for multi-channel analog signals. The device employs multiple ADCs with built-in on-chip synchronous sampling capabilities, using one as the master ADC and the rest as slave ADCs. By cascading multiple reference sources and utilizing the master ADC's internal reference to drive the external references of the slave ADCs, good channel matching can be achieved, reducing costs. By connecting the data buses of the multiple multi-channel synchronous sampling ADCs in parallel to the FPGA master controller and using the CS signal for bus arbitration, a cascaded bus is implemented. This enables high-time-precision synchronous sampling of multi-channel analog signals directly connected to the ADC, improving the synchronization of multi-channel sampling and enhancing system scalability. Compared with existing technologies, this invention solves the technical problems of large sampling time errors, complex channel switching circuits, and poor matching between channels in existing multi-channel sampling devices.

[0030] Furthermore, such as Figure 3 As shown in the present invention, each multi-channel synchronous sampling ADC includes a control unit, multiple independent analog front-ends, multiple independent T / H components, a CONVST signal pin, a MUX, and a SAR ADC. The multiple analog front-ends are connected to the multiple T / H components one by one, the T / H components are connected to the CONVST signal pin, the control unit is connected to the CONVST signal pin, the MUX, and the SAR ADC, and the MUX is connected to the T / H components and the SAR ADC.

[0031] Based on the above embodiments, in this embodiment of the invention, the CONVST signal pins of all multi-channel synchronous sampling ADCs are connected together and then connected to the FPGA main controller. All CONVST signal pins are driven uniformly by a global trigger signal generated by the FPGA main controller. This configuration method enables sampling to be triggered by a single signal, improving the time synchronization accuracy between each ADC.

[0032] Furthermore, besides the ADC, other "asynchronous factors" exist. For example, inconsistent propagation paths of trigger signals can cause deviations in sampling start times. Factors such as the signal line length, routing method, and impedance of each channel can lead to phase deviations in highly phase-sensitive multiphase signals (such as multiphase AC signals) during sampling, thus affecting the normal operation of the sampling control system. To address these asynchronous factors, in this embodiment, the length, routing method, and impedance of the signal lines between the CONVST signal pin of each multi-channel synchronous sampling ADC and the FPGA main controller are kept consistent. Specifically, the signal lines include internal delay lines within the FPGA and external control lines. In addition, the multiple multi-channel synchronous sampling ADCs and the FPGA main controller are arranged symmetrically.

[0033] Furthermore, to facilitate the expansion of the number of channels, in this embodiment of the invention, each multi-channel synchronous sampling ADC is provided with an independent board. With this configuration, the number of sampling channels can be expanded simply by stacking the boards.

[0034] To gain a further understanding of this utility model, the following is in conjunction with... Figures 1 to 4 This invention provides a detailed description of the multi-channel analog signal high-precision synchronous sampling device.

[0035] According to a specific embodiment of this utility model, a high-precision synchronous sampling device for multi-channel analog signals is provided, including an acquisition module and a control and communication module, as shown in the overall block diagram below. Figure 1 As shown, the acquisition module consists of four 8-channel synchronous sampling ADCs forming a 32-channel multi-channel synchronous data sampling device, primarily responsible for acquiring the sensor's output signals. The control and communication module uses an FPGA as its control core. The FPGA, as the core unit of the data acquisition, processing, and control system, possesses powerful parallel processing capabilities and combines real-time performance with high flexibility. This invention addresses the problems of large sampling time errors and low sampling accuracy in existing synchronous sampling devices through the following design:

[0036] This invention uses an ADC with built-in multi-channel sampling function to form a synchronous sampling system, the internal architecture of which is as follows: Figure 3 As shown, this architecture includes independent analog front-ends and corresponding T / H components. All T / H components are controlled by a unified signal CONVST, and sampling is performed on the rising edge of the CONVST signal. The signals are then sequentially fed into a SAR-type ADC for conversion via a MUX. Although this architecture uses the same ADC core to convert all signals sequentially, the T / H circuits sample the signals simultaneously. The sampling time error across multiple channels is only a few nanoseconds, which can be considered ideal synchronous sampling at a 1MHz sampling rate.

[0037] In this invention, synchronizing multiple ADCs is achieved by using a common conversion start signal. That is, the sampling start signals CONVST of all chips are connected together, and an FPGA is used to generate a global trigger signal to drive the CONVST pins of all ADCs. After each sampling, data is read sequentially from multiple ADC devices. This technique eliminates the need for external switching circuitry, significantly improving the sampling synchronization of multi-channel systems.

[0038] To address the mismatch issue of built-in reference sources in existing synchronous sampling systems for each ADC chip, this invention employs a series-connected multi-reference-source approach to process the reference voltage signals of multiple ADCs. Specifically, as shown... Figure 2 As shown: One ADC is selected as the master ADC (master device) and configured in internal reference voltage output mode. The other three are slave ADCs (slave devices) and configured in external reference mode. The reference voltage is led out from the REFOUT pin of the master device and connected to the REFIN pin of the slave devices as a reference voltage source, realizing the internal reference of a single ADC driving the external references of multiple ADCs. In this mode, all ADCs share a single reference voltage source, which can achieve good matching and consistency across multiple channels. While ensuring the system's sampling accuracy, it reduces the need for multiple high-precision external reference sources, thereby reducing design complexity and cost.

[0039] In multi-channel sampling systems, besides the ADC, other "asynchronous factors" exist. For example, inconsistent propagation paths of trigger signals can cause deviations in sampling start times. Factors such as signal line length, routing, and impedance for each channel can lead to phase deviations in highly phase-sensitive multiphase signals (such as multiphase AC signals) during sampling, thus affecting the normal operation of the sampling control system. Therefore, this invention incorporates targeted hardware design in its system design. Specifically, the signal line length, routing, and impedance of the CONVST signal are kept consistent to ensure consistent delays in the arrival of trigger signals at each device. Furthermore, all components are arranged symmetrically to balance parasitic parameters, improve system performance, and ensure good matching between channels.

[0040] Furthermore, to improve data throughput, the ADC is designed to operate in parallel interface mode, employing a 16-bit data bus for communication with the FPGA. Simultaneously, to address the communication interface issue across multiple ADCs, a scalable bus interface mode is designed, with connection methods as follows: Figure 4 As shown, all ADC data buses are connected in parallel, greatly reducing the number of I / Os used. Multiple ADCs use the CS signal for bus arbitration to achieve time-division communication. This communication architecture has strong scalability; the ADC chips are designed as independent boards, and the number of sampling channels can be expanded simply by stacking the boards.

[0041] This device differs from existing multi-channel sampling equipment and has the following advantages:

[0042] (1) The device contains 32 analog sampling channels, each with a sampling rate of up to 1 MSa / s. The device also has high scalability, with all ADCs using a modular multiplexing design and serial communication, which can be flexibly expanded to more than 64 input channels.

[0043] (2) All sampling channels are in direct sampling mode. The input signal is directly connected to the ADC sampling channel after signal conditioning, without the need for external channel switching circuits, and there is no signal overshoot problem caused by channel switching. Under this architecture, all channels are in time-synchronized sampling mode, and the sampling time error between channels is at the nanosecond level, which significantly improves the synchronization performance.

[0044] (3) The sampling system has high matching between multiple ADC chips, which effectively reduces the channel error caused by the quality of the ADC chip and the reference source, and further improves the time accuracy and absolute sampling accuracy of synchronous sampling.

[0045] In summary, this invention provides a high-precision synchronous sampling device for multi-channel analog signals. This device employs multiple ADCs with built-in on-chip synchronous sampling capabilities, using one as the master ADC and the rest as slave ADCs. By cascading multiple reference sources and utilizing the internal reference of the master ADC to drive the external references of the slave ADCs, good channel matching can be achieved and costs reduced. By connecting the data buses of the multiple multi-channel synchronous sampling ADCs in parallel to the FPGA master controller and using the CS signal for bus arbitration, a cascaded bus is realized. This enables high-time-precision synchronous sampling of multi-channel analog signals directly connected to the ADC, improving the synchronization of multi-channel sampling and enhancing the system's scalability. Compared with existing technologies, the technical solution of this invention can solve the technical problems of large sampling time errors, complex channel switching circuits, and poor matching between channels in existing multi-channel sampling devices.

[0046] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0047] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be construed as limiting the scope of protection of this utility model.

[0048] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A high-precision synchronous sampling device for multi-channel analog signals, characterized in that, The device includes a data acquisition module and a control and communication module. The data acquisition module includes multiple multi-channel synchronous sampling ADCs, and the control and communication module includes an FPGA main controller. In the multi-channel synchronous sampling ADC, one of the chips is the master ADC, and the other multi-channel synchronous sampling ADCs are slave ADCs. The master ADC is configured in internal reference voltage output mode, and the slave ADCs are configured in external reference mode. The reference voltage of the master ADC is led out from its own REFOUT pin and connected to the REFIN pin of each slave ADC. All of the multi-channel synchronous sampling ADCs described herein operate in parallel interface mode. The data buses of the multi-channel synchronous sampling ADCs described herein are connected to the FPGA main controller in parallel and are arbitrated via the CS signal.

2. The apparatus according to claim 1, characterized in that, Each of the aforementioned multi-channel synchronous sampling ADCs includes a control unit, multiple independent analog front-ends, multiple independent T / H components, a CONVST signal pin, a MUX, and a SARADC. The multiple analog front-ends are connected one-to-one with the multiple T / H components. The T / H components are connected to the CONVST signal pin. The control unit is connected to the CONVST signal pin, the MUX, and the SARADC, respectively. The MUX is connected to the T / H components and the SARADC, respectively.

3. The apparatus according to claim 2, characterized in that, After the CONVST signal pins of all multi-channel synchronous sampling ADCs are connected together, they are connected to the FPGA main controller, and all CONVST signal pins are uniformly driven by the global trigger signal generated by the FPGA main controller.

4. The apparatus according to claim 3, characterized in that, The length, routing method, and impedance of the CONVST signal pin of each multi-channel synchronous sampling ADC and the signal line between them and the FPGA main controller are kept consistent.

5. The apparatus according to claim 4, characterized in that, The signal lines include internal delay lines of the FPGA and external control lines of the FPGA.

6. The apparatus according to any one of claims 1 to 5, characterized in that, The multi-channel synchronous sampling ADC and the FPGA main controller are arranged symmetrically.

7. The apparatus according to claim 6, characterized in that, Each of the aforementioned multi-channel synchronous sampling ADCs is assigned to a separate board.

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