Network security mainboard

Abstract

The utility model provides a network security mainboard which is applied to the technical field of mainboards, and the network security mainboard comprises an ARM (Advanced RISC Machines) processor; the first data processing module comprises a plurality of first network card chips and a plurality of first network ports, one end of each first network card chip is connected with the ARM processor, and the other end of each first network card chip is connected with the corresponding first network port; the second data processing module comprises a plurality of second network card chips and a plurality of network port pairs, one ends of the second network card chips are connected with the ARM processor, and the other ends of the second network card chips are connected with the network port pairs; the third data processing module comprises a plurality of third network card chips, a plurality of SFP optical ports and a plurality of second network ports, one ends of the third network card chips are connected with the ARM processor, and the other ends of the third network card chips are connected with the second network ports and the SFP optical ports. The utility model aims to give consideration to the performance and security of the network security mainboard through domestic hardware.

Description

Technical Field

[0001] This utility model relates to the field of motherboard technology, and in particular to a network security motherboard. Background Technology

[0002] With the significant increase in communication transmission speeds and the rapid development of network informatization, users have increasingly higher requirements for the security, stability, and performance of network security motherboards. As devices that process network data at high speeds for extended periods, network security motherboards need to meet the requirements of stable operation over long periods and also need to react quickly to network data anomalies to ensure network service stability and system security.

[0003] However, the low level of localization of network security motherboards has made it difficult for traditional network security motherboards to balance performance and security. Therefore, how to balance the performance and security of network security motherboards is a problem that needs to be solved by those skilled in the art. Utility Model Content

[0004] This application proposes a network security motherboard that aims to balance the performance and security of a network security motherboard.

[0005] To achieve the above objectives, this application proposes a network security motherboard, which includes:

[0006] ARM processor;

[0007] A first data processing module, the first data processing module includes a plurality of first network interface cards (NICs) and a plurality of first network ports, one end of the first NIC is connected to the ARM processor, and the other end of the first NIC is connected to the first network port;

[0008] The second data processing module includes multiple second network interface card (NIC) chips and multiple network port pairs. One end of the second NIC chip is connected to the ARM processor, and the other end of the second NIC chip is connected to the network port pair. The network port pair includes multiple network ports interconnected by a bypass circuit.

[0009] The third data processing module includes multiple third network interface cards (NICs), multiple SFP optical ports, and multiple second network ports. One end of the third NIC is connected to the ARM processor, and the other end of the third NIC is connected to the second network ports and the SFP optical ports.

[0010] In one embodiment, the network security motherboard further includes:

[0011] A signal conversion chip, one end of which is connected to the ARM processor;

[0012] The VGA interface is connected to the other end of the signal conversion chip.

[0013] In one embodiment, the network security motherboard further includes:

[0014] A PCIe 8x slot, which is connected to the ARM processor;

[0015] A memory interface, which is connected to the ARM processor.

[0016] In one embodiment, the network security motherboard further includes:

[0017] SATA interface, which is connected to the ARM processor;

[0018] The M.2 KEY-B interface is connected to the ARM processor.

[0019] In one embodiment, the network security motherboard further includes:

[0020] An SMBUS interface is connected to the ARM processor.

[0021] A GPIO interface is provided, which is connected to the ARM processor.

[0022] In one embodiment, the network security motherboard further includes:

[0023] An EMMC chip is connected to the ARM processor;

[0024] In one embodiment, the network security motherboard further includes:

[0025] The Mini-PCIe interface is connected to the ARM processor.

[0026] A SIM card slot is connected to the Mini-PCIe interface.

[0027] In one embodiment, the network security motherboard further includes:

[0028] A USB 2.0 interface, which is connected to the ARM processor;

[0029] USB 2.0 connector, which is connected to the ARM processor;

[0030] The TCM interface is connected to the ARM processor.

[0031] In one embodiment, the network security motherboard further includes:

[0032] The RJ45 serial port is connected to the ARM processor.

[0033] A serial port pin is connected to the ARM processor.

[0034] In one embodiment, the network security motherboard further includes:

[0035] The TAG interface is connected to the ARM processor.

[0036] A fan interface is provided, which is connected to the ARM processor.

[0037] The network security motherboard proposed in this application includes: an ARM processor; a first data processing module, the first data processing module including multiple first network interface card (NIC) chips and multiple first network ports, one end of the first NIC chip being connected to the ARM processor, and the other end of the first NIC chip being connected to the first network port; a second data processing module, the second data processing module including multiple second NIC chips and multiple network port pairs, one end of the second NIC chip being connected to the ARM processor, and the other end of the second NIC chip being connected to the network port pair, wherein the network port pair includes multiple network ports interconnected through bypass circuits; and a third data processing module, the third data processing module including multiple third NIC chips, multiple SFP optical ports, and multiple second network ports, one end of the third NIC chip being connected to the ARM processor, and the other end of the third NIC chip being connected to the second network port and the SFP optical port.

[0038] The network security motherboard proposed in this application uses an ARM architecture processor with a base frequency of up to 2.0GHz and a thermal design power of only 11W, enabling the network security motherboard to combine high performance with low power consumption. Furthermore, the domestically produced network card chip and bypass circuitry used in this application ensure information security and guarantee the stability of signal transmission in the event of a network security motherboard malfunction. Therefore, the network security motherboard proposed in this application achieves a balance between security and high performance through a domestically produced ARM processor, a domestically produced network card chip, and a domestically produced BYPASS circuitry. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the module connections in the first embodiment of the network security motherboard of this application;

[0041] Figure 2 This is a schematic diagram of module connections for a second embodiment of the network security motherboard of this application.

[0042] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0043] Explanation of icon numbers:

[0044] 10. ARM processor; 20. First data processing module; 201. First network card chip; 202. Multiple first network ports; 30. Second data processing module; 301. Multiple second network card chips; 302. Multiple network port pairs; 40. Third data processing module; 401. Multiple third network card chips; 402. Multiple SFP optical ports; 403. Multiple second network ports; 50. Signal conversion chip; 60. VGA interface; 70. PCIe 8x slot; 80. Memory interface; 90. SATA interface; 100. M.2 Key-B interface; 110. SMBUS interface; 120. GPIO interface; 130. eMMC chip; 140. mini-PCIe interface; 150. SIM card slot; 160. USB 2.0 Interfaces: 170, USB 2.0 pin; 180, TCM interface; 190, RJ45 serial port; 200, serial port pin; 210, TAG interface; 220, fan interface. Detailed Implementation

[0045] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. If the embodiments of the present utility model involve descriptions such as "first" or "second", such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of such features.

[0046] This application proposes a network security motherboard that aims to balance the performance and security of a network security motherboard.

[0047] Please refer to Figure 1 , Figure 1 This is a schematic diagram of module connections for a first embodiment of the network security motherboard of this application. In this embodiment, the network security motherboard proposed in this application includes:

[0048] ARM processor 10;

[0049] The first data processing module 20 includes a plurality of first network interface card chips 201 and a plurality of first network ports 202. One end of the first network interface card chip 201 is connected to the ARM processor 10, and the other end of the first network interface card chip 201 is connected to the first network port 202.

[0050] The second data processing module 30 includes a plurality of second network card chips 301 and a plurality of network port pairs 302. One end of the second network card chip 301 is connected to the ARM processor 10, and the other end of the second network card chip 301 is connected to the network port pair 302. The network port pair 302 includes a plurality of network ports interconnected by a bypass circuit.

[0051] The third data processing module 40 includes multiple third network interface card (NIC) chips 401, multiple SFP optical ports 402, and multiple second network ports 403. One end of the third NIC chip 401 is connected to the ARM processor 10, and the other end of the third NIC chip 401 is connected to the second network port 403 and the SFP optical port 402.

[0052] In this embodiment, the domestically produced ARM processor 10 adopts a reduced instruction set, has a main frequency of up to 2.0 GHz, and a thermal design power as low as 11W, combining performance and stability. Furthermore, this ARM processor 10 has abundant resources and can be used for various expansion needs, thus it can be adapted to network security motherboards with multiple gigabit network interfaces.

[0053] In one feasible implementation, the second network interface card (NIC) chip 301 can be a WX1860A4. Specifically, the WX1860A4 supports the RGMII protocol and can simultaneously process up to four gigabit network signals. It also supports network protocol acceleration, Wake-on-LAN, sideband management protocol, remote network boot protocol, flow control, and tunneling protocol. Therefore, compared to Intel gigabit NICs in traditional network security motherboards, the WX1860A4 has lower power consumption and better compatibility with domestic operating systems.

[0054] In one feasible implementation, the third network interface card (NIC) chip 401 can be a YT8521SC. Specifically, the YT8521SC supports the GMII and RGMII protocols and can handle SFP optical port 402 and gigabit network data. Furthermore, the digital signal processing and analog front-end technologies employed by the YT8521SC can support various network signal processing functions, such as automatic calibration, polarity calibration, and adaptive balancing, thereby further enhancing the operating efficiency of the network security motherboard.

[0055] It should be noted that in this embodiment, the first network card chip 201 only needs to process data from a single network port, therefore this application does not limit the model of the first network card chip 201.

[0056] Furthermore, the network security motherboard proposed in this application employs a third-generation BYPASS circuit, introducing an MCU for out-of-band management. This enables the network security motherboard to maintain stable data processing during power-on and power-off processes, effectively avoiding packet loss and improving its stability. Additionally, the BYPASS circuit uses a fully latching relay, which maintains its state even when power is off. This allows the BYPASS circuit to maintain various states during power-off, making its power-on and power-off states controllable and further enhancing the stability of the network security motherboard. Specifically, when one network port pair 302 includes Gigabit Ethernet ports 3 and 4, and another network port pair 302 includes Gigabit Ethernet ports 5 and 6, if Gigabit Ethernet ports 3 and 4, and 5 and 6 support third-generation BYPASS (bypass circuit), the BYPASS circuit can, in the event of a network security motherboard malfunction, switch via a relay to directly connect the two network ports. This allows network data to be transmitted directly without processing by the network security motherboard, maintaining uninterrupted network connectivity.

[0057] The network security motherboard proposed in this application uses an ARM architecture processor with a base frequency of up to 2.0GHz and a thermal design power of only 11W, enabling the network security motherboard to combine high performance with low power consumption. Furthermore, the domestically produced network card chip and bypass circuitry used in this application ensure information security and guarantee the stability of signal transmission in the event of a network security motherboard malfunction. Therefore, the network security motherboard proposed in this application achieves a balance between security and high performance through a domestically produced ARM processor, a domestically produced network card chip, and a domestically produced BYPASS circuitry.

[0058] Please refer to Figure 2 , Figure 2 This is a schematic diagram of module connections for a second embodiment of the network security motherboard of this application.

[0059] It should be noted that, in Figure 2 The network security motherboard is equipped with eight Gigabit Ethernet ports and two SFP optical ports 402. Gigabit Ethernet ports 7 and 8 are multiplexed with SFP optical ports 1 and 2, providing strong expandability to meet the needs of various network security scenarios. Furthermore, network interface card (NIC) chips 1 and 2 form the first NIC chip 201, used to process network data uploaded from the Gigabit Ethernet ports and send the processed data to the ARM processor 10; simultaneously, it processes data received from the ARM processor 10 and sends the processed data to the Ethernet ports.

[0060] Specifically, the first network interface card (NIC) chip 201 communicates with the ARM processor 10 via the SGMII protocol. This protocol uses two pairs of serial differential signals to achieve full-duplex data transmission and includes a data management signal. The NIC chip converts the SGMII signal into a gigabit network signal and then transmits it to the interface. The gigabit network signal consists of four pairs of differential signals. Simultaneously, the NIC chip can also convert the gigabit network signal received at the interface back into an SGMII signal before transmitting it to the ARM processor 10.

[0061] Furthermore, network interface card (NIC) chips 1 and 2 can be domestically produced NIC chips of the same model, thus enabling them to process a set of gigabit network signals respectively. NIC chips 1 and 2 are connected to gigabit network ports 1 and 2 respectively.

[0062] The network interface card (NIC) chip 3 is a second NIC chip 301, which can communicate with the ARM processor 10 via the PCIe bus. The ARM processor 10 allocates two PCIe 1x resources to it, and the second NIC chip 301 outputs four gigabit network signals to the interface. Similarly, the above process is reversible.

[0063] In one embodiment, the network card chip 3 is a domestically produced network card chip, and its output of four gigabit network signals is transmitted to gigabit network ports 3, 4, 5, and 6 respectively.

[0064] In addition, network interface card (NIC) chips 4 and 5 are third NIC chips 401. NIC chips 4 and 5 can use the same type of domestically produced NIC chip, and can each process a set of gigabit network signals. NIC chips 4 and 5 are connected to gigabit Ethernet ports 7 and 8 or SFP optical ports 4021 and 2, respectively.

[0065] Specifically, network interface card (NIC) chips 4 and 5 communicate with the ARM processor 10 via the RGMII protocol, meaning they transmit four bits of data in full-duplex parallel transmission with the ARM processor 10. Simultaneously, NIC chips 4 and 5 each output a gigabit network signal, which is transmitted to gigabit ports 7 and 8 respectively. Similarly, the above process is reversible.

[0066] For example, network interface card chips 4 and 5 can each output one SFP signal to SFP optical ports 4021 and 2 respectively. SFP optical ports 4021 and 2 are multiplexed with Gigabit Ethernet ports 7 and 8 on RGMII resources, thereby selectively outputting Gigabit network signals or SFP signals.

[0067] In a second embodiment of this application, the network security motherboard further includes:

[0068] A signal conversion chip 50, one end of which is connected to the ARM processor 10;

[0069] VGA interface 60, which is connected to the other end of the signal conversion chip 50.

[0070] In this embodiment, the network security motherboard is equipped with a VGA interface 60. The VGA display signal output by the VGA interface 60 is obtained by converting the DP signal output by the ARM processor 10 through a signal conversion chip 50. In this embodiment, the VGA interface 60 supports a maximum resolution of 1920×1200 and a refresh rate of 60Hz.

[0071] In one embodiment, the network security motherboard further includes:

[0072] PCIe 8x slot 70, which is connected to the ARM processor 10;

[0073] Memory interface 80 is connected to the ARM processor 10.

[0074] In this embodiment, the memory interface 80 supports SO-DIMM DDR4 memory, with a maximum support of 2400MHz and a maximum capacity of 16GB; the PCIE 8x slot 70 includes two PCIE 1x signals for connecting various expansion devices.

[0075] In one embodiment, the network security motherboard further includes:

[0076] A SATA interface 90 is connected to the ARM processor 10.

[0077] M.2 KEY-B interface 100, which is connected to the ARM processor 10.

[0078] In this embodiment, the SATA interface 90 and the M.2 KEY-B interface 100 share a set of SATA Gen3 signals, wherein the SATA Gen3 signals originate from the ARM processor 10. In this embodiment, the SATA interface 90 and the M.2 KEY-B interface 100 are used to connect high-capacity storage devices. In a feasible implementation, the two interface types can also be switched to improve the scenario adaptability of the network security motherboard.

[0079] In one embodiment, the network security motherboard further includes:

[0080] SMBUS interface 110, which is connected to the ARM processor 10;

[0081] GPIO interface 120 is connected to the ARM processor 10.

[0082] In this embodiment, the SMBUS interface 110 can not only be used to connect various low-speed devices, such as temperature sensors, voltage monitors, and fan controllers, to obtain information about the motherboard's operating status (such as temperature, voltage, and fan speed), but also for firmware updates and management. The GPIO interface 120 is a pin-type interface, and the ARM processor 10 will allocate 8 GPIO resources to the GPIO interface 120, configured by software as 4 GPIOs and 4 GPIOs.

[0083] In one embodiment, the network security motherboard further includes:

[0084] EMMC chip 130, which is connected to the ARM processor 10;

[0085] In this embodiment, the eMMC is a surface-mount storage chip with a capacity of 32GB. It communicates with the ARM processor 10 via an 8-bit parallel port for high-speed data transmission and data storage.

[0086] In one embodiment, the network security motherboard further includes:

[0087] mini-PCIe interface 140, which is connected to the ARM processor 10;

[0088] SIM card slot 150, which is connected to mini-PCIE interface 140.

[0089] In this embodiment, the mini-PCIE interface 140 is used to connect the wireless network transceiver module. The ARM processor 10 allocates a set of PCIE 1x resources and a set of USB 2.0 resources to it. At the same time, the SIM card slot 150 outputs a set of UIM signals to the mini-PCIE interface 140 to realize the integration of wireless network communication and SIM card function.

[0090] In one embodiment, the network security motherboard further includes:

[0091] USB 2.0 interface 160, which is connected to the ARM processor 10;

[0092] USB 2.0 connector 170, which is connected to the ARM processor 10;

[0093] TCM interface 180 (Trusted Cryptography Module), which is connected to the ARM processor 10;

[0094] In this embodiment, the USB interface includes two USB 2.0 ports and two USB 2.0 pins 170. The four USB 2.0 resources used are directly connected to the ARM processor 10. The USB 2.0 resources on the USB 2.0 pins 1701 are multiplexed with the TCM. Furthermore, the ARM processor 10 allocates a set of USB 2.0 resources to the TCM interface 180, which are multiplexed with the USB 2.0 resources on the USB 2.0 pins 1701. Either the TCM or the USB 2.0 pins 1701 can be used selectively. Specifically, when the TCM interface 180 is used, it can effectively protect the PC and prevent unauthorized access.

[0095] In one embodiment, the network security motherboard further includes:

[0096] RJ45 serial port 190, which is connected to the ARM processor 10;

[0097] A serial port pin 200 is connected to the ARM processor 10.

[0098] In this embodiment, the serial port pin 200 can be used to connect various external modules, such as sensors, displays, modems, etc. Through the serial port pin 200, the ARM processor 10 can communicate with the connected external devices to realize data transmission; the RJ45 serial port 190 can be used to realize network access for devices, supporting high-speed data transmission and network communication.

[0099] In one embodiment, the network security motherboard further includes:

[0100] TAG interface 210, which is connected to the ARM processor 10;

[0101] Fan interface 220 is connected to the ARM processor 10.

[0102] In this embodiment, the TAG interface 210 is also used to connect various low-speed devices. Thus, through the TAG interface 210, the ARM processor 10 can receive the status of external devices in real time to ensure stable operation. The fan interface 220 is used to connect a fan, so that signals can be transmitted to the fan.

[0103] The above are merely optional embodiments of this utility model and do not limit the patent scope of this utility model. All equivalent structural transformations made based on the contents of this utility model specification and drawings under the utility model concept, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this utility model.

Claims

1. A network security motherboard, characterized in that, The network security motherboard includes: ARM processor; A first data processing module, the first data processing module includes a plurality of first network interface cards (NICs) and a plurality of first network ports, one end of the first NIC is connected to the ARM processor, and the other end of the first NIC is connected to the first network port; The second data processing module includes multiple second network interface card (NIC) chips and multiple network port pairs. One end of the second NIC chip is connected to the ARM processor, and the other end of the second NIC chip is connected to the network port pair. The network port pair includes multiple network ports interconnected by a bypass circuit. The third data processing module includes multiple third network interface cards (NICs), multiple SFP optical ports, and multiple second network ports. One end of the third NIC is connected to the ARM processor, and the other end of the third NIC is connected to the second network ports and the SFP optical ports.

2. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: A signal conversion chip, one end of which is connected to the ARM processor; The VGA interface is connected to the other end of the signal conversion chip.

3. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: A PCIe 8x slot, which is connected to the ARM processor; A memory interface, which is connected to the ARM processor.

4. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: SATA interface, which is connected to the ARM processor; The M.2 KEY-B interface is connected to the ARM processor.

5. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: An SMBUS interface is connected to the ARM processor. A GPIO interface is provided, which is connected to the ARM processor.

6. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: An EMMC chip, which is connected to the ARM processor.

7. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: The Mini-PCIe interface is connected to the ARM processor. A SIM card slot is connected to the Mini-PCIe interface.

8. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: A USB 2.0 interface, which is connected to the ARM processor; USB 2.0 connector, which is connected to the ARM processor; The TCM interface is connected to the ARM processor.

9. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: The RJ45 serial port is connected to the ARM processor. A serial port pin is connected to the ARM processor.

10. The network security motherboard as described in claim 1, characterized in that, The network security motherboard also includes: The TAG interface is connected to the ARM processor. A fan interface is provided, which is connected to the ARM processor.

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