Image sensor
By optimizing the driving unit and timing design in the CMOS image sensor and extending gain control to the clamping row, the problems of adjacent row readout limitation and frame rate limit are solved, realizing a compact image sensor with high frame rate.
Patent Information
- Application Number
- CN202520580268.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2035-03-28
AI Technical Summary
As the pixel array of existing CMOS image sensors increases, the area of the photosensitive region also increases. However, the readout limitations of adjacent rows and the horizontal drive signal affect the upper limit of the frame rate, making it difficult to effectively drive and improve the frame rate.
By employing pixel circuit and driver circuit design, and through driver unit and related timing optimization, gain control is extended to clamp lines, shortening inter-line time and increasing the frame rate ceiling.
By optimizing the driving unit and timing design, the interline time is significantly shortened, the frame rate limit of the image sensor is increased, and a high frame rate compact image sensor structure is realized.
Smart Images
Figure CN223942778U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of image sensor technology, and in particular to an image sensor. Background Technology
[0002] In CMOS image sensors, as the pixel array increases, to increase the photosensitive area within the same area, some pixel control transistors often use a shared connection. However, this shared connection increases the limitation on adjacent row readouts. Furthermore, the establishment of the lateral drive signal significantly affects the upper frame rate limit of the image sensor. Therefore, how to effectively drive pixels and how to increase the upper frame rate limit of the image sensor have become pressing technical problems that those skilled in the art urgently need to solve.
[0003] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this utility model and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this utility model. Utility Model Content
[0004] In view of the shortcomings of the prior art described above, the purpose of this utility model is to provide an image sensor to solve the problems of existing image sensors being difficult to drive effectively and having a low frame rate limit.
[0005] To achieve the above and other related objectives, this utility model provides an image sensor, comprising:
[0006] A pixel circuit includes several pixel units, each pixel unit is arranged in M rows and N columns, where M is a natural number greater than or equal to 3 and N is a natural number greater than or equal to 1;
[0007] The driving circuit includes M driving units, each corresponding to a pixel unit in M rows, and is used to generate a gain control signal for the current row based on the control word signal of the current row under the control of the address signal of the current row and the address signal of the previous row.
[0008] Optionally, the driving unit is further configured to operate under the control of the address signal of the next row, wherein the driving unit is configured to generate a gain control signal for the current row based on the control word signal of the current row under the control of the address signal of the current row, the address signal of the previous row, and the address signal of the next row.
[0009] Optionally, the driving circuit includes several driving unit groups arranged in an array, wherein each driving unit group corresponds to the pixel units of the current row and the previous row.
[0010] Optionally, the pixel unit includes a reset transistor, wherein the pixel unit in the current row and the pixel unit in the previous row share the same reset transistor; or, the pixel unit further includes a selection transistor, wherein the pixel unit in the current row and the pixel unit in the next row share the same selection transistor.
[0011] Optionally, when the pixel unit includes a reset transistor, the pixel units in the current row and the pixel units in the previous row are located in the same column; when the pixel unit further includes a selection transistor, the pixel units in the current row, the pixel units in the previous row, and the pixel units in the next row are located in the same column.
[0012] Optionally, the pixel unit further includes a photosensitive element, a transmission transistor, a gain transistor, and a source follower transistor, wherein: the control terminal of the transmission transistor receives a transmission control signal, the first terminal of the transmission transistor is connected to a floating diffusion node, the second terminal of the transmission transistor is connected to ground voltage or a negative voltage via the photosensitive element, the control terminal of the reset transistor receives a reset control signal, the first terminal of the reset transistor is connected to a reset voltage, the second terminal of the reset transistor is connected to the first terminal of the gain transistor, the control terminal of the gain transistor receives a gain control signal, the second terminal of the gain transistor is connected to the floating diffusion node, the control terminal of the source follower transistor is connected to the floating diffusion node, the first terminal of the source follower transistor is connected to a variable voltage, and the second terminal of the source follower transistor is connected to a column line; or, the second terminal of the source follower transistor is connected to the first terminal of the selection transistor, the control terminal of the selection transistor receives a selection control signal, and the second terminal of the selection transistor is connected to a column line.
[0013] Optionally, the driving unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein: the gates of the first PMOS transistor and the second PMOS transistor respectively receive the inverted signals of the address signal of the previous row and the address signal of the current row; the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage; the drains of the first PMOS transistor and the second PMOS transistor are connected to the source of the third PMOS transistor; the gate of the third PMOS transistor receives the inverted signal of the control word signal of the current row; the drain of the third PMOS transistor is connected to the drain of the first NMOS transistor and serves as the output terminal of the driving unit; the gate of the first NMOS transistor receives the inverted signal of the control word signal of the current row. The control word signal of the row is inverted. The source of the first NMOS transistor is connected to the drain of the second and third NMOS transistors. The gates of the second and third NMOS transistors respectively receive the address signal of the previous row and the address signal of the current row. The sources of the second and third NMOS transistors are connected to ground. Alternatively, the driving unit further includes a fourth PMOS transistor and a fifth PMOS transistor, wherein: the gates of the fourth and fifth PMOS transistors respectively receive the address signal of the previous row and the address signal of the current row. The source of the fourth PMOS transistor is connected to the power supply voltage. The drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor. The drain of the fifth PMOS transistor is connected to the output terminal of the driving unit.
[0014] Optionally, the driving unit includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, wherein: the gates of the sixth, seventh, and eighth PMOS transistors respectively receive the inverted signals of the address signals of the previous row, the current row, and the next row; the sources of the sixth, seventh, and eighth PMOS transistors are connected to the power supply voltage; and the drains of the sixth, seventh, and eighth PMOS transistors are connected to the source of the ninth PMOS transistor. The gate of the ninth PMOS transistor receives the inverted signal of the control word signal of the current row. The drain of the ninth PMOS transistor is connected to the drain of the fourth NMOS transistor and serves as the output terminal of the driving unit. The gate of the fourth NMOS transistor receives the inverted signal of the control word signal of the current row. The source of the fourth NMOS transistor is connected to the drain of the fifth, sixth, and seventh NMOS transistors. The gates of the fifth, sixth, and seventh NMOS transistors respectively receive the address signal of the previous row, the address signal of the current row, and the address signal of the next row. The sources of the fifth, sixth, and seventh NMOS transistors are connected to ground.
[0015] Optionally, the driving unit further includes a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor, wherein: the gates of the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor respectively receive the address signal of the previous row, the address signal of the current row, and the address signal of the next row; the source of the tenth PMOS transistor is connected to the power supply voltage; the drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor; the drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor; and the drain of the twelfth PMOS transistor is connected to the output terminal of the driving unit.
[0016] As described above, the image sensor of this utility model relates to a high frame rate compact image sensor structure. By designing the driving unit and related timing, the gain control is extended to the clamping line, which can significantly shorten the inter-line time (HB), thereby increasing the frame rate limit of the image sensor. Attached Figure Description
[0017] Figure 1 The diagram shown is a structural schematic of the image sensor in an embodiment of this utility model.
[0018] Figure 2 The diagram shown is a schematic representation of the pixel circuit in an embodiment of this utility model.
[0019] Figure 3 The diagram shown is a schematic representation of the structure of a drive circuit in the prior art.
[0020] Figure 4 Displayed as Figure 3 The waveform diagram of the control word signal in the driving circuit shown.
[0021] Figure 5 Displayed as by Figure 3 The waveform diagram of the relevant signals in the image sensor constructed by the driving circuit shown.
[0022] Figure 6 The diagram shown is a schematic diagram of the drive circuit in an embodiment of this utility model.
[0023] Figure 7 Displayed as Figure 6 The waveform diagram of the control word signal in the driving circuit shown.
[0024] Figure 8 Displayed as by Figure 6 The waveform diagram of the relevant signals in the image sensor constructed by the driving circuit shown.
[0025] Component designation explanation
[0026] 100 Image Sensor
[0027] 110 pixel circuit
[0028] 111 pixel unit
[0029] 120 drive circuit
[0030] 121 Drive Unit Detailed Implementation
[0031] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.
[0032] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this utility model. Therefore, the illustrations only show the components related to this utility model and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0033] like Figure 1As shown, this embodiment provides an image sensor 100, including a pixel circuit 110 and a driving circuit 120.
[0034] The pixel circuit 110 includes a plurality of pixel units 111, each pixel unit 111 being arranged in M rows and N columns, where M is a natural number greater than or equal to 3 and N is a natural number greater than or equal to 1; optionally, the pixel units 111 generate image signals based on the photoelectric effect, wherein the image signals typically include pixel signals and reset signals.
[0035] In one implementation, such as Figure 2 As shown, pixel unit 111 includes a reset transistor M2, and further includes a selection transistor M5; even further, it includes a photosensitive element PD, a transmission transistor M1, a gain transistor M3, and a source follower transistor M4. In practical applications, to save area, different pixel units 111 can share transistors. For example, adjacent pixel units 111 can share transistors, wherein adjacent pixel units 111 can be located in the same column or in different columns. In a specific example, the pixel unit 111 of the current row and the pixel unit 111 of the previous row share the same reset transistor M2. In one alternative, the pixel unit 111 of the current row and the pixel unit 111 of the previous row are located in the same column. Further, the pixel unit 111 of the current row and the pixel unit 111 of the next row share the same selection transistor M5. In one alternative, the pixel unit 111 of the current row, the pixel unit 111 of the previous row, and the pixel unit 111 of the next row are located in the same column. In this embodiment, the current row is denoted as row i, the previous row as row (i-1), and the next row as row (i+1). The transistor sharing is specifically as follows: Figure 2 As shown, i is greater than 1 and less than M.
[0036] It should be noted that the terms "current row," "previous row," and "next row" described in this utility model are used to illustrate the operational relationship between them. The current row does not necessarily refer to a single row; it can also be two or more rows. Similarly, the previous row and the next row do not necessarily refer to a single row; they can also be two or more rows, depending on the actual readout requirements. In addition, the previous row and the next row can be adjacent to the current row or can be shared pixel unit rows that are spaced apart.
[0037] When pixel unit 111 includes a photosensitive element PD, a transmission transistor M1, a reset transistor M2, a gain transistor M3, and a source follower transistor M4, the specific circuit connection is as follows: the control terminal of the transmission transistor M1 receives a transmission control signal (e.g., tx). The first terminal of the transmission transistor M1 is connected to the floating diffusion node (e.g., fd). The second terminal of the transmission transistor M1 is connected to ground voltage or negative voltage via the photosensitive element PD, and the control terminal of the reset transistor M2 receives a reset control signal (e.g., rst). <i-1>The first terminal of the reset transistor M2 is connected to the reset voltage (e.g., rstd). <i-1>The second terminal of the reset transistor M2 is connected to the first terminal of the gain transistor M3, and the control terminal of the gain transistor M3 receives a gain control signal (e.g., dcg). The second terminal of the gain transistor M3 is connected to the floating diffusion node (e.g., fd). The source follower transistor M4's control terminal is connected to the floating diffusion node (e.g., fd). The first terminal of the source follower transistor M4 is connected to a variable voltage, and the second terminal of the source follower transistor M4 is connected to the column bitline. When the pixel unit 111 also includes a selection transistor M5, the second terminal of the source follower transistor M4 is no longer connected to the column bitline, but is instead connected to the first terminal of the selection transistor M5. The control terminal of the selection transistor M5 receives a selection control signal (e.g., rs). <i-1>The second terminal of transistor M5 is connected to the column line bitline.
[0038] When designing pixel unit 111 using the above devices, the transmission transistor M1, reset transistor M2, gain transistor M3, source follower transistor M4, and select transistor M5 are typically implemented using NMOS transistors. In this case, the control terminal is the gate, the first terminal is the drain, and the second terminal is the source. Of course, it is also feasible to implement each transistor using PMOS transistors. The photosensitive element PD is typically implemented using a photodiode. Of course, it is also feasible to implement the photosensitive element using a grating or photoconductor. In addition, in pixel unit 111, the transmission transistor M1 and the photosensitive element PD are in one-to-one correspondence. The number of them can be one or more, without much restriction.
[0039] The driving circuit 120 includes M driving units 121, each corresponding to a row of pixel units 111. Each driving unit 121 provides a gain control signal to the pixel units 111 in each row.
[0040] In one example, the driving unit 121 is used to generate a gain control signal for the current row based on the control word signal of the current row, under the control of the address signal of the current row and the address signal of the previous row. Specifically, pixel units 111 that reuse the same reset transistor M2 are defined as a pixel group, and the two rows corresponding to this pixel group are defined as the first row and the second row, respectively. Then, the two corresponding driving units 121, under the control of the first row address signal and the second row address signal, generate the gain control signal of their respective rows according to the control word signal of their respective rows. For example, if the pixel unit 111 in the i-th row and the pixel unit 111 in the (i-1)-th row reuse the same reset transistor M2, then the driving unit 121 corresponding to the pixel unit 111 in the i-th row, under the control of the address signal of the i-th row and the address signal of the (i-1)-th row, generates the gain control signal of the i-th row according to the control word signal of the i-th row. The driving unit 121 corresponding to the pixel unit 111 in the (i-1)-th row, under the control of the address signal of the i-th row and the address signal of the (i-1)-th row, generates the gain control signal of the (i-1)-th row according to the control word signal of the (i-1)-th row.
[0041] In one implementation, such as Figure 3 As shown, the driving unit 121 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 respectively receive the inverted signal of the address signal of the previous row (e.g., rp_addb_i-1) and the inverted signal of the address signal of the current row (e.g., rp_addb_i). The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the power supply voltage AVDD. The drains of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the source of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 receives the inverted signal of the control word signal of the current row (e.g., rp_dcg_b). <1> The drain of the third PMOS transistor MP3 is connected to the drain of the first NMOS transistor MN1 and serves as the output of the drive unit 121 to generate the gain control signal (e.g., dcg) for the current row. The gate of the first NMOS transistor MN1 receives the inverted signal of the control word signal for the current row (e.g., rp_dcg_b). <1> The first NMOS transistor MN1 has its source connected to the drain of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3. The gates of the second NMOS transistor MN2 and the third NMOS transistor MN3 receive the address signal of the previous row (e.g., rp_add_i-1) and the address signal of the current row (e.g., rp_add_i), respectively. The sources of the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected to ground voltage AGND. Furthermore, the driving unit 121 also includes a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5, wherein: the gates of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 receive the address signal of the previous row (e.g., rp_add_i-1) and the address signal of the current row (e.g., rp_add_i), respectively. The source of the fourth PMOS transistor MP4 is connected to the power supply voltage AVDD, the drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5, and the drain of the fifth PMOS transistor MP5 is connected to the output terminal of the driving unit 121.
[0042] In the image sensor 100 described above, the pixel circuit 110 adopts a transistor structure, such as an inter-row shared transistor structure. That is, in three rows (which can be three consecutive rows) of pixel units 111 in the same column, the first two rows of pixel units 111 share the reset transistor M2, and the last two rows of pixel units 111 share the selection transistor M5. In this case, the first two rows of pixel units 111 also share a low conversion gain node. Although this shared structure can save area, it has inter-row readout limitations, specifically as follows:
[0043] Taking three consecutive rows of pixel units 111 corresponding to the (i-1)th, i-th, and (i+1)th rows respectively as an example, when performing a readout operation on the pixel unit 111 in the i-th row under low conversion gain, the gain control signal dcg corresponding to the pixel unit 111 in the i-th row is... Valid, the gain control signal dcg corresponding to pixel unit 111 in row (i-1) is valid. <i-1>Invalid, for example, dcg High potential, dcg <i-1>To keep the potential low so that the floating diffusion node fd The equivalent capacitance is the sum of its own capacitance and the capacitance of the low conversion gain node. Additionally, the reset voltage rstd corresponding to pixel unit 111 in the (i+1)th row... It should be at a low potential to prevent floating diffusion node fd<i+1> The potential is too high, thus clamping the readout signal of the i-th row.
[0044] In this process, the driving unit 121 drives and controls the pixel unit 111. The two driving units 121 corresponding to the pixel unit 111 in the i-th row and the pixel unit 111 in the (i-1)-th row share the address signal of the i-th row and the address signal of the (i-1)-th row, as shown below. Figure 3 As shown, the control word signals are different and are rp_dcg respectively. <0> and rp_dcg <1> See also Figure 4 As shown in the fourth segment of the signal waveform, when the i-th row pixel unit 111 performs a readout operation under low conversion gain, the gain transistor M3 in the i-th row pixel unit 111 is turned on, and the gain transistor M3 in the (i-1)-th row pixel unit 111 is turned off.
[0045] As mentioned above, when performing a readout operation at low conversion gain on pixel unit 111 in row i, the reset voltage rstd corresponding to pixel unit 111 in row (i+1) is... It is at a low potential, and when the readout ends, the reset voltage rstd corresponding to pixel unit 111 in the (i+1)th row is... A high voltage is needed to facilitate the reading of row (i+1). However, due to the reset voltage rstd... The corresponding node is overloaded, and the reset voltage rstd The pull-up operation has a distinct rising edge, while the read from row (i+1) requires a reset voltage rstd. This process can only proceed after the voltage stabilizes at a high level; therefore, the reset voltage rstd... The pull-up operation consumes interline time (HB), thereby reducing the frame rate limit of the image sensor, such as... Figure 5 As shown.
[0046] To address timing waste and increase the frame rate limit of the image sensor, this embodiment further improves the driving unit 121 and designs related timing, extending gain control to the clamping line, thereby significantly shortening the inter-line time (HB) and increasing the frame rate limit of the image sensor.
[0047] In another example, the driving unit 121 is used to generate a gain control signal for the current row based on the control word signal of the current row under the control of the address signal of the current row, the address signal of the previous row, and the address signal of the next row; for example, the i-th driving unit 121 generates a gain control signal for the i-th row based on the control word signal of the i-th row under the control of the address signal of the i-th row, the address signal of the (i-1)-th row, and the address signal of the (i+1)-th row.
[0048] In one implementation, such as Figure 6 As shown, the driving unit 121 includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7. The gates of the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8 respectively receive the inverted signal of the address signal of the previous row (e.g., rp_addb_i-1), the inverted signal of the address signal of the current row (e.g., rp_addb_i-1), and the inverted signal of the address signal of the current row (e.g., rp_addb_i-1). For example, the inverted signal of the address signal of the next line (e.g., rp_addb_i) and the source of the sixth PMOS transistor MP6, the source of the seventh PMOS transistor MP7, and the source of the eighth PMOS transistor MP8 are connected to the power supply voltage AVDD. The drains of the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, and the eighth PMOS transistor MP8 are all connected to the source of the ninth PMOS transistor MP9. The gate of the ninth PMOS transistor MP9 receives the inverted signal of the control word signal of the current line (e.g., rp_dcg_b). <1> The drain of the ninth PMOS transistor MP9 is connected to the drain of the fourth NMOS transistor MN4 and serves as the output of the drive unit 121 to generate the gain control signal (e.g., dcg) for the current row. The gate of the fourth NMOS transistor MN4 receives the inverted signal of the control word signal for the current row (e.g., rp_dcg_b). <1> The source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5, the drain of the sixth NMOS transistor MN6, and the drain of the seventh NMOS transistor MN7. The gates of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7 receive the address signal of the previous row (e.g., rp_add_i-1), the address signal of the current row (e.g., rp_add_i), and the address signal of the next row (e.g., rp_add_i+1), respectively. The sources of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the seventh NMOS transistor MN7 are all connected to the ground voltage AGND. Furthermore, it also includes a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, and a twelfth PMOS transistor MP12, wherein: the gate of the tenth PMOS transistor MP10, the gate of the eleventh PMOS transistor MP11, and the gate of the twelfth PMOS transistor MP12 respectively receive the address signal of the previous row (e.g., rp_add_i-1), the address signal of the current row (e.g., rp_add_i), and the address signal of the next row (e.g., rp_add_i+1), the source of the tenth PMOS transistor MP10 is connected to the power supply voltage AVDD, the drain of the tenth PMOS transistor MP10 is connected to the source of the eleventh PMOS transistor MP11, the drain of the eleventh PMOS transistor MP11 is connected to the source of the twelfth PMOS transistor MP12, and the drain of the twelfth PMOS transistor MP12 is connected to the output terminal of the drive unit 121.
[0049] In this embodiment, the driving circuit 120 includes several driving unit groups arranged in an array. Each driving unit group corresponds to the pixel unit 111 in the current row and the pixel unit 111 in the previous row. For example, each driving unit group includes two driving units 121, corresponding to the pixel unit 111 in the current row and the pixel unit 111 in the previous row, respectively, and providing gain control signals to the pixel unit 111 in the current row and the pixel unit 111 in the previous row, respectively. In addition, in the actual physical structure, the two driving units 121 in each driving unit group share the same power line and the same ground line.
[0050] like Figures 2 to 8 As shown, this embodiment also provides a control method for an image sensor 100, including the following steps; wherein the image sensor 100 is implemented using the structure described above.
[0051] The specific control method includes: controlling the address signal of the current row, the address signal of the previous row, and the control word signal of the current row; performing a low-conversion-gain readout operation on the pixel unit 111 of the current row. This can be a low-conversion-gain pixel signal readout operation or a low-conversion-gain reset signal readout operation, without much restriction; wherein, the gain control signal corresponding to the pixel unit 111 of the current row (e.g., dcg) ) is valid during the readout phase, and the gain control signal (e.g., dcg) corresponding to the previous row pixel unit 111 is valid. <i-1>This is invalid during the readout phase. Furthermore, the specific control method also includes: controlling the address signal of the next row so that when performing a low-conversion-gain readout operation on the pixel unit 111 of the current row, the gain control signal (e.g., dcg) corresponding to the pixel unit 111 of the next row is...<i+1> During the readout phase, it is valid initially and then invalid.
[0052] As an example, during the readout phase described above, the reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is also controlled. The image is in a high state; furthermore, the reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is controlled. First pull it low, then pull it high. In a specific example, the gain control signal (e.g., dcg) corresponding to the next row pixel unit 111 is controlled.<i+1> The reset voltage (e.g., rstd) corresponding to the next row of pixel units. Pulling down before raising has no effect, such as... Figure 8 As shown. In practical applications, during the readout phase, the reset control signals (e.g., rst) corresponding to the current row pixel unit 111 and the previous row pixel unit 111 are... <i-1>Invalid, the reset control signal (e.g., rst) corresponding to the next row pixel unit 111 is invalid. ) Valid. It should be noted that the low conversion gain here can be any gain other than the high conversion gain formed by the floating diffusion nodes themselves. For example, it can be the gain formed by sharing the gain nodes of the previous row, or it can be other gains acquired, such as a lower gain formed by further sharing the high gain nodes of the previous row.
[0053] Taking the example of the corresponding driving unit providing gain control signals to pixel units 111 in rows i, (i-1), and (i+1), and row i being a read row: the address signal rp_add_i of row i is high, and the inverted signal rp_addb_i of row i is low; the address signal rp_add_i-1 of row (i-1) is low, and the inverted signal rp_addb_i-1 of row (i-1) is high; the address signal rp_add_i+1 of row (i+1) is low, and the inverted signal rp_addb_i+1 of row (i+1) is high; in addition, the control word signal rp_dcg of row i... <1> The high potential represents the inverted signal rp_dcg_b of the control word signal in the i-th row. <1> The control word signal rp_dcg in row (i-1) is at a low potential. <0> The inverted signal rp_dcg_b of the control word signal in row (i-1) is at a low potential. <0> The control word signal rp_dcg in row (i+1) is at a high potential. <2> First high, then low, the inverted signal rp_dcg_b of the control word signal in row (i+1). <2> First a low potential, then a high potential, such as Figure 7 As shown in the waveform of the fourth segment, the gain control signal dcg in the i-th row is... It is at a high potential, that is, the gain control signal dcg in the i-th row. Valid, the gain control signal dcg in row (i-1) <i-1>The voltage is low, that is, the gain control signal dcg in row (i-1). <i-1>Invalid, the gain control signal dcg in row (i+1)<i+1> The signal is initially high and then low, i.e., the gain control signal dcg in row (i+1).<i+1> It is effective at first, then ineffective.
[0054] The start time of the readout phase is denoted as the first time T1. The gain control signal (e.g., dcg) corresponding to the previous row pixel unit 111 is... <i-1>The invalid time of ) is recorded as the second time T2, and the reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is set. The pull-down time of ) is recorded as the third time T3. The reset control signals (e.g., rst) corresponding to the current row pixel unit 111 and the previous row pixel unit 111 are set. <i-1>The invalid time of ) is denoted as the fourth time T4. Then: the first time T1 precedes the second time T2, the second time T2 precedes the third time T3, and the third time T3 precedes the fourth time T4. The reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is set. The moment when the voltage stabilizes at a low level is recorded as the fifth moment T5. The gain control signal (e.g., dcg) corresponding to the next row pixel unit 111 is then used.<i+1> The invalid time of ) is recorded as the sixth time T6, and the reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is set. If the pull-up time is denoted as the seventh time T7, then: the fifth time T5 precedes the sixth time T6, and the sixth time T6 precedes the seventh time T7. In fact, the fifth time T5 is later than the fourth time T4; the reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is... First pull it low, then pull it high. Once it stabilizes at a low potential, turn off the gain transistor M3 in the next row pixel unit 111. At this time, the floating diffusion node (e.g., fd) of the next row pixel unit 111...<i+1> Maintaining a low potential avoids clamping the readout signal of the current row. Additionally, since the gain transistor M3 in the next row pixel unit 111 has been turned off, the reset voltage rstd corresponding to the next row pixel unit 111 can be applied. The pull-up operation is performed, and during the readout phase, the reset voltage corresponding to the next row pixel unit 111 is applied (e.g., rstd). The pull-up operation helps to shorten the interline time (HB) and increase the frame rate limit of the image sensor.
[0055] During the readout phase, the reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is applied. During the pull-up operation of ), the reset voltage (e.g., rstd) The time when the voltage stabilizes at a high potential can be during or after the readout phase, depending on the specific requirements; when this reset voltage (e.g., rstd) is stable... When the reset voltage is stabilized at a high potential during the readout phase, the interline time (HB) can be minimized; when the reset voltage (e.g., rstd) is stable during the readout phase, the interline time (HB) can be minimized. When the voltage stabilizes at a high level after the readout phase, although the reduction in inter-line time (HB) is limited, it is more driver-friendly and can reduce jitter interference. In this embodiment, the reset voltage (e.g., rstd) When the voltage stabilizes at a high level, it is in the readout phase. At this time, the reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is set. The moment when the voltage stabilizes at a high potential is denoted as the eighth moment T8, and the end time of the readout phase is denoted as the ninth moment T9. Therefore: the eighth moment T8 precedes the ninth moment T9, or the eighth moment T8 and the ninth moment T9 are the same moment. In fact, the eighth moment T8 is later than the seventh moment T7. During the readout phase, the reset voltage (e.g., rstd) corresponding to the next row of pixel unit 111 is completed. The pull-up operation, that is, when the current row pixel unit 111 is read out, the reset voltage (e.g., rstd) corresponding to the next row pixel unit 111 is set. The voltage has stabilized at a high level, so after the current row is read out, the next row can be read out directly, which can significantly shorten the inter-row time (HB) and help to further increase the frame rate limit of the image sensor.
[0056] In summary, this invention relates to a high frame rate compact image sensor structure. By designing the driving unit and related timing, gain control is extended to the clamping line, which can significantly shorten the inter-line time (HB), thereby increasing the upper limit of the image sensor's frame rate. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0057] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.
Claims
1. An image sensor, characterized in that, include: A pixel circuit includes several pixel units, each pixel unit is arranged in M rows and N columns, where M is a natural number greater than or equal to 3 and N is a natural number greater than or equal to 1; The driving circuit includes M driving units, each corresponding to a pixel unit in M rows, and is used to generate a gain control signal for the current row based on the control word signal of the current row under the control of the address signal of the current row and the address signal of the previous row.
2. The image sensor according to claim 1, characterized in that, The driving unit is also configured to operate under the control of the address signal of the next row, wherein the driving unit is configured to generate a gain control signal for the current row based on the control word signal of the current row under the control of the address signal of the current row, the address signal of the previous row, and the address signal of the next row.
3. The image sensor according to claim 2, characterized in that, The driving circuit includes several driving unit groups arranged in an array, wherein each driving unit group corresponds to the pixel units of the current row and the previous row.
4. The image sensor according to claim 1, characterized in that, The pixel unit includes a reset transistor, wherein the pixel unit in the current row and the pixel unit in the previous row share the same reset transistor; or, the pixel unit further includes a selection transistor, wherein the pixel unit in the current row and the pixel unit in the next row share the same selection transistor.
5. The image sensor according to claim 4, characterized in that, When the pixel unit includes a reset transistor, the pixel units in the current row and the pixel units in the previous row are located in the same column; when the pixel unit also includes a selection transistor, the pixel units in the current row, the pixel units in the previous row, and the pixel units in the next row are located in the same column.
6. The image sensor according to claim 4, characterized in that, The pixel unit further includes a photosensitive element, a transmission transistor, a gain transistor, and a source follower transistor, wherein: the control terminal of the transmission transistor receives a transmission control signal; the first terminal of the transmission transistor is connected to a floating diffusion node; the second terminal of the transmission transistor is connected to ground voltage or a negative voltage via the photosensitive element; the control terminal of the reset transistor receives a reset control signal; the first terminal of the reset transistor is connected to a reset voltage; the second terminal of the reset transistor is connected to the first terminal of the gain transistor; the control terminal of the gain transistor receives a gain control signal; the second terminal of the gain transistor is connected to the floating diffusion node; the control terminal of the source follower transistor is connected to the floating diffusion node; the first terminal of the source follower transistor is connected to a variable voltage; and the second terminal of the source follower transistor is connected to a column line; or, the second terminal of the source follower transistor is connected to the first terminal of the selection transistor; the control terminal of the selection transistor receives a selection control signal; and the second terminal of the selection transistor is connected to a column line.
7. The image sensor according to claim 1, characterized in that, The driving unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The gates of the first and second PMOS transistors respectively receive the inverted signals of the previous row's address signal and the current row's address signal. The sources of the first and second PMOS transistors are connected to the power supply voltage. The drains of the first and second PMOS transistors are connected to the source of the third PMOS transistor. The gate of the third PMOS transistor receives the inverted signal of the current row's control word signal. The drain of the third PMOS transistor is connected to the drain of the first NMOS transistor and serves as the output terminal of the driving unit. The gate of the first NMOS transistor receives the inverted signal of the current row's control word signal. The control word signal is an inverted signal. The source of the first NMOS transistor is connected to the drain of the second and third NMOS transistors. The gates of the second and third NMOS transistors respectively receive the address signal of the previous row and the address signal of the current row. The sources of the second and third NMOS transistors are connected to ground. Alternatively, the driving unit further includes a fourth PMOS transistor and a fifth PMOS transistor, wherein: the gates of the fourth and fifth PMOS transistors respectively receive the address signal of the previous row and the address signal of the current row. The source of the fourth PMOS transistor is connected to the power supply voltage. The drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor. The drain of the fifth PMOS transistor is connected to the output terminal of the driving unit.
8. The image sensor according to any one of claims 2 to 6, characterized in that, The driving unit includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The gates of the sixth, seventh, and eighth PMOS transistors respectively receive the inverted signals of the previous row's address signal, the current row's address signal, and the next row's address signal. The sources of the sixth, seventh, and eighth PMOS transistors are connected to the power supply voltage. The drains of the sixth, seventh, and eighth PMOS transistors are connected to the source of the ninth PMOS transistor. The gate of the ninth PMOS transistor receives the inverted signal of the control word signal of the current row. The drain of the ninth PMOS transistor is connected to the drain of the fourth NMOS transistor and serves as the output terminal of the driving unit. The gate of the fourth NMOS transistor receives the inverted signal of the control word signal of the current row. The source of the fourth NMOS transistor is connected to the drain of the fifth, sixth, and seventh NMOS transistors. The gates of the fifth, sixth, and seventh NMOS transistors respectively receive the address signal of the previous row, the address signal of the current row, and the address signal of the next row. The sources of the fifth, sixth, and seventh NMOS transistors are connected to ground.
9. The image sensor according to claim 8, characterized in that, The driving unit further includes a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor, wherein: the gates of the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor respectively receive the address signal of the previous row, the address signal of the current row, and the address signal of the next row; the source of the tenth PMOS transistor is connected to the power supply voltage; the drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor; the drain of the eleventh PMOS transistor is connected to the source of the twelfth PMOS transistor; and the drain of the twelfth PMOS transistor is connected to the output terminal of the driving unit.