Display device

Abstract

The utility model relates to a display device. The display device includes a first insulating layer; a first electrode disposed on the first insulating layer and including a lower surface contacting an upper surface of the first insulating layer, an upper surface opposite to the lower surface, and a side surface connecting the upper surface and the lower surface; a second insulating layer disposed on the first electrode, overlapping an upper surface and a side surface of the first electrode, and including an inorganic insulating material; and a third insulating layer disposed on the second insulating layer, in which a first portion and a second portion of an upper surface of the second insulating layer face each other, with a gap around a line in which an upper surface of the first insulating layer and a side surface of the first electrode intersect each other, and a portion of the third insulating layer is disposed in the gap.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0011726, filed on January 25, 2024, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more embodiments relate to display devices, and more specifically, to display devices including, for example, light-emitting diodes. Background Technology

[0004] A display device is a device for visually displaying image data. A display device may include a substrate divided into a display area and a non-display area. The display area may include multiple sub-pixels. Additionally, the display area may include a thin-film transistor corresponding to each of the sub-pixels and a sub-pixel electrode electrically connected to the thin-film transistor. Furthermore, the display area may include an emitter layer corresponding to each of the sub-pixel electrodes. Additionally, a counter electrode corresponding to the sub-pixel may be included in the display area. The non-display area may include various wires, drivers, controllers, etc., for transmitting electrical signals to the display area. Recently, display devices have been widely used in various fields. Accordingly, various designs are being explored to improve the quality of display devices. Summary of the Invention

[0005] In display devices, the thickness of the gate electrode of a thin-film transistor can be increased to reduce its resistance. In this case, a gap can be formed in the portion of the inorganic insulating layer covering the gate electrode due to the step between the insulating layer beneath the gate electrode and the upper surface of the gate electrode.

[0006] In embodiments of this disclosure, an additional insulating layer may be provided to mitigate the impact of the step.

[0007] According to one or more embodiments, the display device includes a first insulating layer; a first electrode disposed on the first insulating layer and including a lower surface contacting an upper surface of the first insulating layer, an upper surface opposite to the lower surface, and a side surface connecting the upper and lower surfaces; a second insulating layer disposed on the first electrode, overlapping the upper surface and side surface of the first electrode, and comprising an inorganic insulating material; and a third insulating layer disposed on the second insulating layer, wherein a first portion and a second portion of the upper surface of the second insulating layer face each other, wherein a gap is present around a line where the upper surface of the first insulating layer and the side surface of the first electrode intersect each other, and a portion of the third insulating layer is disposed in the gap.

[0008] In an embodiment, the third insulating layer may include an organic insulating material comprising silicon, oxygen, and carbon, and the ratio of the number of carbon atoms to the number of silicon atoms in the third insulating layer may be about 0.6 or less.

[0009] In an embodiment, the ratio of the number of carbon atoms to the number of silicon atoms in the third insulating layer can be in the range of about 0.1 to about 0.6.

[0010] In an embodiment, the ratio of the number of oxygen atoms to the number of silicon atoms in the third insulating layer can be in the range of about 1.5 to about 2.5.

[0011] In an embodiment, the thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode may be less than the thickness of the portion of the second insulating layer that overlaps with the upper surface of the first electrode.

[0012] In an embodiment, the thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode may be less than the thickness of the portion of the third insulating layer that overlaps with the side surface of the first electrode.

[0013] In an embodiment, the thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode may be equal to or less than about 1000 angstroms.

[0014] In an implementation, the thickness of the first electrode can be in the range of about 3,500 angstroms to about 6,000 angstroms.

[0015] In an embodiment, the first tilt angle formed by the side surface of the first electrode relative to the upper surface of the first insulating layer may be greater than the second tilt angle formed by the upper surface of the portion of the third insulating layer that overlaps with the side surface of the first electrode and the upper surface of the first insulating layer.

[0016] In an implementation, the second tilt angle can be in the range of about 50 degrees to about 60 degrees.

[0017] According to one or more embodiments, a display device includes a first insulating layer; a first electrode disposed on the first insulating layer and including a lower surface contacting an upper surface of the first insulating layer, an upper surface opposite to the lower surface, and a side surface connecting the upper and lower surfaces; a third insulating layer disposed on the first electrode, overlapping the upper and side surfaces of the first electrode, and comprising an organic insulating material; and a second insulating layer disposed on the third insulating layer and comprising an inorganic insulating material, wherein a first tilt angle formed by the side surface of the first electrode relative to the upper surface of the first insulating layer is greater than a second tilt angle formed by the upper surface of the portion of the third insulating layer overlapping the side surface of the first electrode relative to the upper surface of the first insulating layer, and the third insulating layer directly contacts the upper and side surfaces of the first electrode.

[0018] In an embodiment, the third insulating layer may include an organic insulating material comprising silicon, oxygen, and carbon, and the ratio of the number of carbon atoms to the number of silicon atoms in the third insulating layer may be about 0.6 or less.

[0019] In an embodiment, the ratio of the number of carbon atoms to the number of silicon atoms in the third insulating layer can be in the range of about 0.1 to about 0.6.

[0020] In an embodiment, the ratio of the number of oxygen atoms to the number of silicon atoms in the third insulating layer can be in the range of about 1.5 to about 2.5.

[0021] In an embodiment, the thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode may be less than the thickness of the portion of the second insulating layer that overlaps with the upper surface of the first electrode.

[0022] In an embodiment, the thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode may be less than the thickness of the portion of the third insulating layer that overlaps with the side surface of the first electrode.

[0023] In an embodiment, the thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode may be equal to or less than about 1000 angstroms.

[0024] In an implementation, the thickness of the first electrode can be in the range of about 3,500 angstroms to about 6,000 angstroms.

[0025] In this embodiment, the maximum thickness of the third insulating layer may be less than the thickness of the first electrode.

[0026] In an implementation, the second tilt angle can be in the range of about 50 degrees to about 60 degrees. Attached Figure Description

[0027] The above and other features of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 A perspective view illustrating a display device according to an embodiment;

[0029] Figure 2 The equivalent circuit diagram of the sub-pixels of the display device according to the embodiment is shown in the illustration.

[0030] Figure 3 This is a cross-sectional view of a display device according to an embodiment;

[0031] Figure 4 This is an enlarged cross-sectional view of the display device according to the embodiment;

[0032] Figure 5A , Figure 5B and Figure 5C A cross-sectional view illustrating the operation of the manufacturing process of the display device according to the embodiment;

[0033] Figure 6 This is a cross-sectional view of a display device according to another embodiment;

[0034] Figure 7 This is an enlarged cross-sectional view of a display device according to another embodiment; and

[0035] Figure 8A , Figure 8B and Figure 8C A cross-sectional view illustrating the operation of the manufacturing process of a display device according to another embodiment. Detailed Implementation

[0036] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0037] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be illustrated in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, and the ways in which they are achieved, will become apparent from reference to the embodiments described in detail later with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below, but can be embodied in various forms.

[0038] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings of this document, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second area, second layer, or second part.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the terms “a,” “an,” “the,” and “at least one” as used herein do not indicate a limitation of quantity and are intended to include both the singular and the plural. Thus, reference to “a” element followed by “the” element in the claims includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” is not construed as limited to “a” or “an.”

[0040] It will be further understood that, when used in this specification, the terms “comprises” and / or “comprising” or “includes” and / or “including” indicate the presence of the described features, areas, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components and / or groups thereof.

[0041] In the following embodiments, it will be understood that when a portion (e.g., a layer, region, or element) is referred to as being "on" or "above" another portion (e.g., a layer, region, or element), it may be directly on or above the other portion (e.g., a layer, region, or element), or there may be an intervening portion (e.g., a layer, region, or element). In contrast, when an element (e.g., a layer, region, or element) is referred to as being "directly on" another element (e.g., a layer, region, or element), there is no intervening element (e.g., a layer, region, or element).

[0042] Furthermore, the dimensions of the components may be enlarged or reduced in the accompanying drawings for ease of description. For example, since the dimensions (e.g., thickness) of the components in the drawings have been arbitrarily interpreted for ease of explanation, the following embodiments are not limited thereto.

[0043] When the implementation is carried out in another manner, the predetermined process sequence may differ from the described process sequence. For example, two processes described consecutively may be performed substantially simultaneously, or they may be performed in the reverse order of the description.

[0044] In this document, “or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the related enumerated items. Furthermore, “at least one of A and B” or “selected from at least one of A and B” may indicate only A, only B, or both A and B. Throughout this disclosure, the expressions “at least one of a, b, and c” or “selected from at least one of a, b, and c” indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0045] In the following embodiments, when a layer, area, or element is described as connecting to other layers, this indicates a case where layers, areas, and elements are directly connected or / or where layers, areas, or elements are indirectly connected with other layers, areas, and elements in between. For example, here, when a layer, area, or element is described as an electrical connection, this indicates a case where layers, areas, and elements are directly electrically connected and / or where layers, areas, and elements are indirectly electrically connected with other layers, areas, and elements in between.

[0046] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” are used herein to describe the relationship between one element and another as illustrated in a figure. It will be understood that relative terms are intended to encompass different orientations of a device beyond those depicted in the figure. For example, if a device in a figure is flipped, an element described as being “down” of another element will then be oriented “up” of that element. Therefore, the term “down” can encompass both “down” and “up” orientations, depending on the specific orientation of the figure. Similarly, if a device in a figure is flipped, an element described as being “below” or “under” another element will then be oriented “above” of that element. Therefore, the term “below” or “under” can encompass both “up” and “down” orientations.

[0047] The x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system, but can be interpreted as including these axes. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can indicate different directions that are not perpendicular to each other.

[0048] As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation for a particular value, determined by consideration of the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system) by a person skilled in the art. For example, “about” may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] The embodiments are described herein with reference to illustrative cross-sectional illustrations as preferred embodiments. Therefore, variations in the shape of the illustrated area should be anticipated due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to a specific shape of the area as illustrated herein, but rather include deviations in shape due to factors such as manufacturing. For example, an illustrated or described flat area may generally have rough and / or non-linear characteristics. Furthermore, the sharp corners of the illustrated area may be rounded. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the area and are not intended to limit the scope of the claims.

[0051] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements, and any repeated detailed descriptions will be omitted or simplified.

[0052] Figure 1 A perspective view illustrating a display device according to an embodiment.

[0053] refer to Figure 1 The implementation of display device 1 may include a display area DA and a non-display area NDA located outside the display area DA. The display area DA can display an image through sub-pixels P arranged in the display area DA. The non-display area NDA is arranged outside the display area DA, is an area where no image is displayed, and may completely surround the display area DA. A driver for supplying electrical signals or power to the display area DA may be arranged in the non-display area NDA. Pads that serve as areas for electrically connecting electronic components or printed circuit boards may be arranged in the non-display area NDA.

[0054] In the implementation method, such as Figure 1 As illustrated, the display area DA may have a polygonal shape (e.g., a rectangle) in which the length of the display area DA in the x-direction (i.e., the x-axis) is less than the length of the display area DA in the y-direction (i.e., the y-axis). However, in another embodiment, the display area DA may have a polygonal shape (e.g., a rectangle) in which the length of the display area DA in the y-direction is less than the length of the display area DA in the x-direction. Figure 1 This disclosure describes an implementation where the display area DA is rectangular, but it is not limited thereto. In another implementation, for example, the display area DA may have various shapes, such as an N-sided polygon (N is a natural number of 3 or greater), a circle, or an ellipse. Figure 1 An embodiment in which the corners of the display area DA have a shape including vertices where straight lines intersect. However, in another embodiment, the display area DA may be a polygon with curved corners. In this description, the z-direction (i.e., the z-axis) is perpendicular to the plane formed by the x-direction and the y-direction.

[0055] For ease of description, the following will describe an embodiment in which the display device 1 is an electronic device (e.g., a smartphone), but the display device 1 of this disclosure is not limited thereto. The display device 1 can be used not only in portable electronic devices (e.g., mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, portable multimedia players (PMPs), navigation devices, and ultra-large mobile PCs (UMPCs)), but also in various products (e.g., televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices). Furthermore, the display device 1 according to the embodiments can be applied to wearable devices (e.g., smartwatches, watch phones, glasses-type displays, and head-mounted displays (HMDs)). In addition, the display device 1 according to the embodiments can be used as a central information display (CID) arranged on the instrument panel, center console, or dashboard of a vehicle, as a mirror display replacing the side mirrors of a vehicle, and as a display arranged on the back of the front seats as an entertainment device for the rear seats of a vehicle.

[0056] Figure 2 The equivalent circuit diagram of a sub-pixel of a display device according to an embodiment is shown for illustrative purposes.

[0057] Display device 1 ( Figure 1 ) may include arrangements in the display area DA ( Figure 1 Sub-pixel P in ).

[0058] In one embodiment, subpixel P may include subpixel circuit PC and display element DPE connected to subpixel circuit PC. Subpixel circuit PC may include driving thin-film transistor T1, switching thin-film transistor T2, and storage capacitor Cst. Subpixel P may emit light of certain colors through display element DPE. In one embodiment, for example, subpixel P may emit red, green, or blue light through display element DPE, or it may emit red, green, blue, or white light.

[0059] The switching thin-film transistor T2 is connected to the scan line SL and the data line DL, and can transmit the scan voltage input from the scan line SL or the data voltage or data signal Dm input from the data line DL to the driving thin-film transistor T1 according to the scan signal Sn.

[0060] The storage capacitor Cst can be connected to the switching thin-film transistor T2 and the drive voltage line PL, and can store the voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the first power supply voltage ELVDD supplied to the drive voltage line PL.

[0061] A driving thin-film transistor T1 is connected to a driving voltage line PL and a storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL through the display element DPE in response to the voltage value stored in the storage capacitor Cst. The display element DPE can emit light with a specific brightness corresponding to the driving current. The counter electrode (e.g., cathode) of the display element DPE can receive a second power supply voltage ELVSS.

[0062] In the implementation method, such as Figure 2 As shown, the subpixel circuit PC may include two thin-film transistors and a storage capacitor, but this disclosure is not limited thereto, and optionally, the subpixel circuit PC may include three or more thin-film transistors.

[0063] Figure 3 This is a cross-sectional view of a display device according to an embodiment.

[0064] refer to Figure 3 In an implementation of a display device, a light-emitting diode (LED) can be used as a component corresponding to a sub-pixel P( Figure 1 The display element is disposed on the substrate 100. The light-emitting diode (LED) can be electrically connected to the thin-film transistor (TFT).

[0065] A buffer layer 101 may be disposed on the substrate 100. The buffer layer 101 may planarize and protect the upper surface of the substrate 100. The buffer layer 101 may include an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and / or silicon oxynitrides (SiO2) x N y It may have a single-layer or multi-layer structure, each layer comprising at least one material selected from the above-mentioned materials. Although not explicitly stated... Figure 3 As explained in the text, however, an isolation layer (not shown) may be additionally located between the substrate 100 and the buffer layer 101.

[0066] A thin-film transistor (TFT) may be disposed on the buffer layer 101. The TFT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The TFT may be connected to and drive a light-emitting diode (LED). In some embodiments, the TFT may correspond to a reference. Figure 2 The described driving thin-film transistor T1 ( Figure 2 Although not in Figure 3 The explanation is in the text, but the switching thin-film transistor T2 ( Figure 2 It can also be set on the buffer layer 101.

[0067] The active layer ACT may be disposed on the buffer layer 101 and may include a drain region overlapping with the drain electrode DE, a source region overlapping with the source electrode SE, and a channel region disposed between the drain region and the source region. The drain region and the source region may be regions doped with impurities. The impurities doped in the drain region and the source region may be different from each other.

[0068] A first insulating layer 103 may be disposed on the active layer ACT. The first insulating layer 103 may comprise an inorganic material comprising oxides or nitrides. In an embodiment, for example, the first insulating layer 103 may comprise a material selected from silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y It may contain at least one of the following: aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), and may have a single-layer structure or a multi-layer structure, wherein each layer includes at least one material selected from the above materials.

[0069] A gate electrode GE may be disposed on the first insulating layer 103. The gate electrode GE may at least partially overlap with the active layer ACT. In an embodiment, for example, the gate electrode GE may overlap with the channel region of the active layer ACT. The gate electrode GE may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure, each layer comprising at least one material selected from the above.

[0070] The second insulating layer 105 may be configured to cover the gate electrode GE. The second insulating layer 105 may include an inorganic material comprising oxides or nitrides. In an embodiment, for example, the second insulating layer 105 may include materials selected from silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y It may contain at least one of the following: aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), and may have a single-layer structure or a multi-layer structure, wherein each layer includes at least one material selected from the above materials.

[0071] The second insulating layer 105 may include a gap in the area around or near the line where the side surface of the gate electrode GE and the upper surface of the first insulating layer 103 intersect each other. This will be described in more detail below.

[0072] A third insulating layer 106 may be disposed on the second insulating layer 105. The third insulating layer 106 may cover the second insulating layer 105, and a portion of the third insulating layer 106 may be disposed in the gaps of the second insulating layer 105. The third insulating layer 106 may include an organic insulating material. In an embodiment, for example, the third insulating layer 106 may include hexamethyldisiloxane.

[0073] The storage capacitor Cst may include a first electrode layer CE1 and a second electrode layer CE2. In one embodiment, the storage capacitor Cst may be arranged to overlap with the thin-film transistor (TFT). In this embodiment, the gate electrode GE can function not only as the gate electrode of the TFT but also as the first electrode layer CE1 of the storage capacitor Cst. That is, the gate electrode GE of the TFT and the first electrode layer CE1 of the storage capacitor Cst may be formed as a single unit. The second electrode layer CE2 may overlap with either the first electrode layer CE1 or the gate electrode GE. In another embodiment, the storage capacitor Cst does not overlap with the TFT and may be located separately. In this embodiment, the first electrode layer CE1 of the storage capacitor Cst and the gate electrode GE of the TFT may be formed as separate elements.

[0074] The fourth insulating layer 107 may be configured to cover the second electrode layer CE2. The fourth insulating layer 107 may comprise an inorganic material containing oxides or nitrides. In an embodiment, for example, the fourth insulating layer 107 may comprise a material selected from silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y It may contain at least one of the following: aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2), and may have a single-layer structure or a multi-layer structure, wherein each layer includes at least one material selected from the above materials.

[0075] The first insulating layer 103, the second insulating layer 105, the third insulating layer 106, and the fourth insulating layer 107 may include contact holes that overlap with the source and drain regions of the active layer ACT. In an embodiment, for example, the first insulating layer 103, the second insulating layer 105, the third insulating layer 106, and the fourth insulating layer 107 may each be provided with an opening that overlaps with and is defined through each layer, and the openings may overlap and connect with each other to form contact holes.

[0076] The source electrode SE and the drain electrode DE may be disposed on the fourth insulating layer 107. The source electrode SE may be configured to overlap with the source region of the active layer ACT, and the drain electrode DE may be configured to overlap with the drain region of the active layer ACT. The source electrode SE and the drain electrode DE may each be connected to the active layer ACT through contact holes defined or formed in the first insulating layer 103, the second insulating layer 105, the third insulating layer 106, and the fourth insulating layer 107.

[0077] The via layer 109 may be disposed on the source electrode SE and the drain electrode DE. The via layer 109 may include a first via layer 1109, a second via layer 2109 and a third via layer 3109.

[0078] The first via layer 1109 may be configured to cover the source electrode SE and the drain electrode DE. The first via layer 1109 may have openings overlapping the drain electrode DE. The first via layer 1109 may include a general polymer (e.g., benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, or a vinyl alcohol polymer, etc., and may have a single-layer structure or a multi-layer structure, each layer comprising at least one material selected from the above materials.

[0079] A connecting metal may be disposed on the first via layer 1109. A portion of the connecting metal may be disposed in an opening in the first via layer 1109. The connecting metal may be connected to the drain electrode DE through the opening in the first via layer 1109. The connecting metal may include aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure, each layer comprising at least one material selected from the above.

[0080] The second via layer 2109 may be configured to cover the first via layer 1109. The second via layer 2109 may include openings that overlap with the connecting metal disposed on the first via layer 1109. The second via layer 2109 may include general polymers (e.g., benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, or vinyl alcohol polymers, etc., and may have a single-layer structure or a multi-layer structure, each layer comprising at least one material selected from the above.

[0081] A connecting metal may be disposed on the second via layer 2109. A portion of the connecting metal may be disposed in an opening in the second via layer 2109. The connecting metal can be connected to a connecting metal disposed on the first via layer 1109 through the opening in the second via layer 2109. The connecting metal may include aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure, each layer comprising at least one material selected from the above.

[0082] The third via layer 3109 may be arranged to cover the second via layer 2109. The third via layer 3109 may have openings that overlap with the connecting metal disposed on the second via layer 2109. The third via layer 3109 may include a general polymer (e.g., benzocyclobutene, polyimide, hexamethyldisiloxane, polymethyl methacrylate, or polystyrene), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, or a vinyl alcohol polymer, etc., and may have a single-layer structure or a multi-layer structure, each layer comprising at least one material selected from the above materials.

[0083] Figure 3 An embodiment including two connecting metals and three via layers (e.g., a first via layer 1109, a second via layer 2109, and a third via layer 3109) has been described, but this disclosure is not limited thereto. In another embodiment, the via layer 109 may be a single layer, and the connecting metals may be omitted. Optionally, the via layer 109 may include two layers and may include one connecting metal.

[0084] The sub-pixel electrode 210 may be disposed on the third via layer 3109. The sub-pixel electrode 210 may be connected to the connection metal through an opening formed in the third via layer 3109. Accordingly, the sub-pixel electrode 210 may be electrically connected to the thin-film transistor TFT and receive voltage through the connection metal and the drain electrode DE.

[0085] The sub-pixel electrode 210 may include a conductive oxide (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO)). In another embodiment, the sub-pixel electrode 210 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. The composition and materials of the sub-pixel electrode 210 are not limited thereto and various modifications are possible.

[0086] A barrier layer 111 may be disposed on the third via layer 3109. The barrier layer 111 may cover the edge (or edge region) of the sub-pixel electrode 210. In other words, the barrier layer 111 may be perforated to expose the central portion of the sub-pixel electrode 210. The size and shape of the light-emitting area of ​​the light-emitting diode (LED) may be determined by the perforation of the barrier layer 111.

[0087] An intermediate layer 220 may be disposed on the sub-pixel electrode 210. The intermediate layer 220 may include a first common layer 221 and a second common layer 223 disposed on the retaining layer 111, and an emission layer 222 disposed in an opening in the retaining layer 111. In some embodiments, the first common layer 221 may be disposed on the retaining layer 111, the emission layer 222 may be disposed on the first common layer 221 in an opening in the retaining layer 111, and the second common layer 223 may be disposed on the first common layer 221 to cover the emission layer 222. In other words, the emission layer 222 may be disposed in an opening in the retaining layer 111 and between the first common layer 221 and the second common layer 223.

[0088] The emitter layer 222 may include an organic emitter layer comprising a low-molecular-weight material or a polymeric material. The first common layer 221 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second common layer 223 may include a hole transport layer (HTL) and / or a hole injection layer (HIL). In some embodiments, the first common layer 221 or the second common layer 223 may be omitted. In some embodiments, the position of the first common layer 221 may change depending on the position of the second common layer 223.

[0089] The counter electrode 230 may be disposed on the intermediate layer 220. In an embodiment, for example, the counter electrode 230 may be disposed on the second common layer 223. The counter electrode 230 may be arranged to completely cover the intermediate layer 220. The counter electrode 230 may include a conductive material having a low work function. In an embodiment, for example, the counter electrode 230 may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. Optionally, the counter electrode 230 may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer comprising the above-mentioned materials.

[0090] An encapsulation layer 300 may be disposed on the counter electrode 230. The encapsulation layer 300 may include at least one inorganic layer and at least one organic layer. In an embodiment, the encapsulation layer 300 may include a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material, such as silicon oxide (SiO2). x), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The materials used may be aluminum oxide (Al₂O₃), titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), or zinc oxide (ZnO₂). The organic encapsulation layer 320 may include a polymeric material. The polymeric material may include at least one selected from silicone resins, acrylic resins, epoxy resins, polyimide, and polyethylene.

[0091] Figure 4 This is an enlarged cross-sectional view of a display device according to an embodiment. In particular, Figure 4 for Figure 3 An enlarged cross-sectional view of region IV.

[0092] refer to Figure 4 In an embodiment of the display device, the gate electrode GE (or the first electrode layer CE1) may be disposed on the first insulating layer 103. The second insulating layer 105, the third insulating layer 106, and the fourth insulating layer 107 may be disposed sequentially on the gate electrode GE.

[0093] The gate electrode GE1 may include a first layer GE-1 and a second layer GE-2. The first layer GE-1 may be disposed on the upper surface of the first insulating layer 103. The first layer GE-1 and the second layer GE-2 may each comprise different materials. In an embodiment, for example, the first layer GE-1 may comprise aluminum (Al), and the second layer GE-2 may comprise titanium (Ti).

[0094] The gate electrode GE may include a lower surface contacting the first insulating layer 103, an upper surface opposite to the lower surface, and a side surface connecting the lower surface and the upper surface. In an embodiment, the lower surface of the gate electrode GE may be the lower surface of the first layer GE-1. In an embodiment, the upper surface of the gate electrode GE may be the upper surface of the second layer GE-2. In an embodiment, the gate electrode GE may have a trapezoidal cross-section. In other words, the side surface of the gate electrode GE may be inclined relative to the upper surface of the first insulating layer 103. In this embodiment, the angle formed by the side surface of the gate electrode GE and the upper surface of the first insulating layer 103 may be defined as a first angle θ1. In an embodiment, the first angle θ1 may be in the range of about 60 degrees to about 70 degrees. In an embodiment, the gate electrode GE may have a specific thickness. The thickness of the gate electrode GE may be the sum of the thickness of the first layer GE-1 and the thickness of the second layer GE-2. The thickness of the gate electrode GE may be defined as a zero thickness TH0. In an embodiment, the thickness of the gate electrode GE or the zero thickness TH0 may be approximately to approximately Within this range. In other words, the 0th thickness TH0 can range from about 0.35 micrometers (μm) to about 0.6 μm.

[0095] The second insulating layer 105 may cover the gate electrode GE. A portion of the second insulating layer 105 may overlap with the upper surface of the gate electrode GE. The thickness of the portion of the second insulating layer 105 overlapping with the upper surface of the gate electrode GE may be defined as a fourth thickness TH4. Another portion of the second insulating layer 105 may overlap with the side surface of the gate electrode GE. The thickness of the portion of the second insulating layer 105 overlapping with the side surface of the gate electrode GE may be defined as a fifth thickness TH5. Another portion of the second insulating layer 105 may overlap with the upper surface of the first insulating layer 103. The thickness of the portion of the second insulating layer 105 overlapping with the upper surface of the first insulating layer 103 may be defined as a sixth thickness TH6. In an embodiment, the fourth thickness TH4, the fifth thickness TH5, and the sixth thickness TH6 may be substantially equal to each other. In an embodiment, the fourth thickness TH4, the fifth thickness TH5, and the sixth thickness TH6 may be less than the zeroth thickness TH0.

[0096] The second insulating layer 105 may include gaps 105-1 defined in the region around or near the line where the upper surface of the first insulating layer 103 and the side surface of the gate electrode GE intersect each other. In an embodiment, a plurality of gaps 105-1 may be located in the region around or near the opposite side of the gate electrode GE. A portion of the second insulating layer 105 overlapping the upper surface of the first insulating layer 103 (e.g., a first portion) and another portion of the second insulating layer 105 overlapping the side surface of the gate electrode GE (e.g., a second portion) may face each other, with gaps 105-1 between them. During the process of covering the gate electrode GE and the first insulating layer 103 with the second insulating layer 105, gaps 105-1 of the second insulating layer 105 may be formed due to a step between the upper surface of the first insulating layer 103 and the upper surface of the gate electrode GE. In an embodiment, for example, as the zeroth thickness TH0 of the gate electrode GE increases, the probability of forming gaps 105-1 and / or the size of gaps 105-1 may be increased.

[0097] A third insulating layer 106 may be disposed on the second insulating layer 105. The third insulating layer 106 may cover the second insulating layer 105. A portion of the third insulating layer 106 may overlap with the upper surface of the gate electrode GE. The thickness of the portion of the third insulating layer 106 overlapping with the upper surface of the gate electrode GE may be defined as a first thickness TH1. The portion of the third insulating layer 106 having the first thickness TH1 may overlap with a portion of the second insulating layer 105 having a fourth thickness TH4. Another portion of the third insulating layer 106 may overlap with the side surface of the gate electrode GE. The thickness of the portion of the third insulating layer 106 overlapping with the side surface of the gate electrode GE may be defined as a second thickness TH2. The portion of the third insulating layer 106 having the second thickness TH2 may overlap with a portion of the second insulating layer 105 having a fifth thickness TH5. Another portion of the third insulating layer 106 may overlap with the upper surface of the first insulating layer 103. The thickness of the portion of the third insulating layer 106 overlapping with the upper surface of the first insulating layer 103 may be defined as a third thickness TH3. The portion of the third insulating layer 106 having a third thickness TH3 may overlap with the portion of the second insulating layer 105 having a sixth thickness TH6.

[0098] In one embodiment, the first thickness TH1 may be less than the fourth thickness TH4. In one embodiment, the second thickness TH2 may be less than the fifth thickness TH5. In one embodiment, the third thickness TH3 may be less than the sixth thickness TH6. In one embodiment, the first thickness TH1 may be less than both the second thickness TH2 and the third thickness TH3. In one embodiment, the second thickness TH2 may be substantially the same as the third thickness TH3. In one embodiment, the second thickness TH2 may be less than the third thickness TH3. In one embodiment, the first thickness TH1 may be approximately... Or even smaller. In other words, the first thickness TH1 can be about 0.1 micrometers or less. As mentioned above, the thickness of that portion of the third insulating layer 106 can be varied depending on its location.

[0099] The upper surface of the portion of the third insulating layer 106 that overlaps with the side surface of the gate electrode GE may be inclined relative to the upper surface of the first insulating layer 103. In an embodiment, for example, if a tangent is drawn to contact the upper surface of the portion of the third insulating layer 106 that overlaps with the side surface of the gate electrode GE, the tangent may form a second angle θ2 with the upper surface of the first insulating layer 103. The second angle θ2 may indicate the degree of inclination of the portion of the third insulating layer 106 that overlaps with the side surface of the gate electrode GE. In an embodiment, the second angle θ2 may be smaller than the first angle θ1. In an embodiment, the second angle θ2 may be in the range of about 50 degrees to about 60 degrees. In an embodiment, the second angle θ2 may be about 50 degrees or less. As described above, the third insulating layer 106 may mitigate the inclination of the second insulating layer 105 and the inclination of the side surface of the gate electrode GE caused by the gate electrode GE having a thickness TH0.

[0100] In the region around or near the line where the upper surface of the first insulating layer 103 and the side surface of the gate electrode GE intersect each other, a portion of the third insulating layer 106 may be located within the gap 105-1 of the second insulating layer 105. Figure 4 In the embodiment illustrated, the third insulating layer 106 may fill a portion of the gap 105-1 in the second insulating layer 105. In another embodiment, with Figure 4 According to the different interpretations, the third insulating layer 106 can completely fill the gap 105-1 of the second insulating layer 105.

[0101] The third insulating layer 106 may include an organic insulating material. In an embodiment, for example, the third insulating layer 106 may include an organic insulating material having high flowability or high reflowability. Accordingly, a portion of the third insulating layer 106 may flow into and be disposed in the gap 105-1. Additionally, a portion of the third insulating layer 106 may flow such that the second angle θ2 may be smaller than the first angle θ1. In other words, the high flowability (i.e., high fluidity characteristic) of the third insulating layer 106 allows the inclination of the portion of the third insulating layer 106 overlapping the side surface of the gate electrode GE to be gentle, i.e., smaller than the inclination of the side surface of the gate electrode GE.

[0102] In an embodiment, the third insulating layer 106 may include hexamethyldisiloxane (SiO2). x C y In an embodiment, the ratio of carbon atoms to silicon atoms in the third insulating layer 106 may be about 0.6 or less. In an embodiment, the ratio of carbon atoms to silicon atoms in the third insulating layer 106 may be in the range of about 0.1 to about 0.6. As the ratio of carbon atoms to silicon atoms in the third insulating layer 106 decreases, the light transmittance of the third insulating layer 106 can be increased. In an embodiment, the ratio of oxygen atoms to silicon atoms in the third insulating layer 106 may be in the range of about 1.5 to about 2.5. With the atomic composition of the third insulating layer 106 as described above, the atomic composition of the hexamethyldisiloxane included in the third insulating layer 106 can be substantially close to that of silicon oxide (SiO₂). x Furthermore, the fluidity of the third insulating layer 106 can be maximized.

[0103] The second electrode layer CE2 may be disposed on the third insulating layer 106. The first electrode layer CE1 (or gate electrode GE) and the second electrode layer CE2 may form a storage capacitor CST. Accordingly, the first electrode layer CE1 and the second electrode layer CE2 may overlap each other. By reducing the distance between the first electrode layer CE1 and the second electrode layer CE2 (i.e., the first distance D1), the capacitance of the storage capacitor CST can be increased. In an embodiment, the first distance D1 may be the sum of the first thickness TH1 and the fourth thickness TH4. Accordingly, as the first thickness TH1 and / or the fourth thickness TH4 are reduced, the first distance D1 can be reduced, and the capacitance of the storage capacitor CST can be increased.

[0104] The fourth insulating layer 107 and the through-hole layer 109 can be sequentially disposed on the second electrode layer CE2.

[0105] Figure 5A , Figure 5B and Figure 5C A cross-sectional view illustrating the operation of the manufacturing process of the display device according to an embodiment. In particular, Figure 5A , Figure 5B and Figure 5C Can be explained Figure 4 A cross-sectional view of the operation in the manufacturing process of the implementation method described in the text.

[0106] refer to Figure 5A A gate electrode GE may be provided or formed on the first insulating layer 103. The gate electrode GE may include a first layer GE-1 and a second layer GE-2, and may have a thickness TH0. The gate electrode GE may include a lower surface contacting the first insulating layer 103, an upper surface opposite to the lower surface, and a side surface connecting the lower surface and the upper surface. The side surface of the gate electrode GE may form a first angle θ1 with the upper surface of the first insulating layer 103.

[0107] refer to Figure 5B A second insulating layer 105 may be provided or formed on the first insulating layer 103 and the gate electrode GE. The second insulating layer 105 may cover the gate electrode GE. A gap 105-1 may be formed in the region around or near the line where the upper surface of the first insulating layer 103 and the side surface of the gate electrode GE intersect each other. The gap 105-1 may be caused by a step between the upper surface of the first insulating layer 103 and the upper surface of the gate electrode GE. In other words, the gap 105-1 may be caused by a 0th thickness TH0 and a first angle θ1. In another embodiment, if the 0th thickness TH0 and / or the first angle θ1 is reduced, the gap 105-1 may not be formed.

[0108] refer to Figure 5CAn organic layer 106' may be provided or formed on the second insulating layer 105. The organic layer 106' may cover the second insulating layer 105. A portion of the organic layer 106' may overlap with the upper surface of the gate electrode GE. The thickness of the portion of the organic layer 106' overlapping with the upper surface of the gate electrode GE may be defined as a first initial thickness TH1'. Another portion of the organic layer 106' may overlap with the side surface of the gate electrode GE. The thickness of the portion of the organic layer 106' overlapping with the side surface of the gate electrode GE may be defined as a second initial thickness TH2'. Another portion of the organic layer 106' may overlap with the upper surface of the first insulating layer 103. The thickness of the portion of the organic layer 106' overlapping with the upper surface of the first insulating layer 103 may be defined as a third initial thickness TH3'. In an embodiment, the first initial thickness TH1', the second initial thickness TH2', and the third initial thickness TH3' may be substantially the same as each other. In an embodiment, the first initial thickness TH1', the second initial thickness TH2', and the third initial thickness TH3' may be less than the zero thickness TH0.

[0109] In this embodiment, the organic layer 106' can be formed by chemical vapor deposition (CVD). At this stage of the process, the thickness of the entire organic layer 106' can be substantially constant. Therefore, in the initial stage of the process, the tilt angle formed by the portion of the organic layer 106' overlapping with the side surface of the gate electrode GE relative to the upper surface of the first insulating layer 103 can be substantially equal to the tilt angle formed by the side surface of the gate electrode GE relative to the upper surface of the first insulating layer 103 and the tilt angle formed by the portion of the second insulating layer 105 overlapping with the side surface of the gate electrode GE relative to the upper surface of the first insulating layer 103. In this embodiment, for example, the upper surface of the portion of the organic layer 106' overlapping with the side surface of the gate electrode GE can form a third angle θ3 with the upper surface of the first insulating layer 103. In this embodiment, the first angle θ1 can be substantially the same as the third angle θ3.

[0110] In an embodiment, the organic layer 106' may include the third insulating layer 106 ( Figure 4 The material is the same as that used for the organic layer 106'. Accordingly, the organic layer 106' can have high fluidity.

[0111] refer to Figure 5C In the initial stage, the first initial thickness TH1', the second initial thickness TH2', and the third initial thickness TH3' of the organic layer 106' are substantially the same, and the organic layer 106' is not located in the gap 105-1. Furthermore, in Figure 5CIn this embodiment, the third angle θ3 is shown as substantially equal to the first angle θ1. However, the organic layer 106' is flowable and, for example, can change its shape after a certain period of time under the influence of gravity. In one embodiment, a portion of the organic layer 106' overlapping the upper surface of the gate electrode GE can flow to the region overlapping the side surface of the gate electrode GE. Accordingly, the first initial thickness TH1' can become smaller than the second initial thickness TH2' and the third initial thickness TH3'. In another embodiment, a portion of the organic layer 106' can flow into and be disposed in the gap 105-1. In this case, a portion of the organic layer 106' can fill a portion or the entire gap 105-1. In another embodiment, a portion of the organic layer 106' is flowable and can increase the thickness of the portion overlapping the side surface of the gate electrode GE (i.e., the second thickness TH2') and the thickness of the portion overlapping the upper surface of the first insulating layer 103 (i.e., the third thickness TH3'). Accordingly, the third angle θ3 can decrease. The organic layer 106' after the above flow process can be combined with... Figure 4 The third insulating layer 106 explained in the text Figure 4 They are basically the same.

[0112] Figure 6 This is a cross-sectional view of a display device according to another embodiment.

[0113] In addition to the second insulating layer 105 and the third insulating layer 106, Figure 6 The display device shown in the image and Figure 3 The display devices shown are essentially the same. Figure 6 The same or similar elements shown above have been used in the description Figure 3 The same reference characters are used to mark the implementation of the display device shown in the figure, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0114] refer to Figure 6 In an embodiment of the display device, a third insulating layer 106 may be disposed on the gate electrode GE (or the first electrode layer CE1) and the first insulating layer 103. In an embodiment, for example, the third insulating layer 106 may cover the gate electrode GE. A second insulating layer 105 may be disposed on the third insulating layer 106. The second insulating layer 105 may cover the third insulating layer 106. The inclination of the upper surface of the portion of the third insulating layer 106 overlapping the side surface of the gate electrode GE may be different from the inclination of the side surface of the gate electrode GE. The inclination of the upper surface of the portion of the second insulating layer 105 overlapping the side surface of the gate electrode GE may be different from the inclination of the side surface of the gate electrode GE.

[0115] Figure 7 This is an enlarged cross-sectional view of a display device according to another embodiment. In particular, Figure 7for Figure 6 An enlarged cross-sectional view of section VII.

[0116] refer to Figure 7 In an embodiment of the display device, a third insulating layer 106 may be disposed on the gate electrode GE and the first insulating layer 103. The third insulating layer 106 may directly contact the gate electrode GE and the first insulating layer 103. In an embodiment, for example, the third insulating layer 106 may directly contact the upper and side surfaces of the gate electrode GE and the upper surface of the first insulating layer 103. The third insulating layer 106 may also be disposed in the area around or near the line where the upper surface of the first insulating layer 103 and the side surface of the gate electrode GE intersect.

[0117] A portion of the third insulating layer 106 may overlap with the side surface of the gate electrode GE. A tangent drawn on the upper surface of the portion of the third insulating layer 106 that overlaps with the side surface of the gate electrode GE may form a second angle θ2 with the upper surface of the first insulating layer 103. The side surface of the gate electrode GE may form a first angle θ1 with the upper surface of the first insulating layer 103. The relationship between the first angle θ1 and the second angle θ2 is substantially the same as described above. Accordingly, the third insulating layer 106 may mitigate the tilt caused by the side surface of the gate electrode GE.

[0118] The second insulating layer 105 may be disposed on and cover the third insulating layer 106. The tilt angle formed by the portion of the second insulating layer 105 overlapping the side surface of the gate electrode GE with respect to the upper surface of the first insulating layer 103 may be substantially the same as the tilt angle formed by the portion of the third insulating layer 106 overlapping the side surface of the gate electrode GE with respect to the upper surface of the first insulating layer 103 (i.e., the second angle θ2). Because a portion of the second insulating layer 105 may be disposed on the tilted surface mitigated by the third insulating layer 106, it is substantially the same as... Figure 4 The second insulating layer 105 described in the text is different. Figure 6 The second insulating layer 105 as described herein may not include gap 105-1 ( Figure 4 ).

[0119] Figure 8A , Figure 8B and Figure 8C A cross-sectional view illustrating the operation of a manufacturing process for a display device according to another embodiment. In particular, Figure 8A , Figure 8B and Figure 8C Can be explained Figure 7 A cross-sectional view of the operation in the manufacturing process of the implementation method described in the text.

[0120] Let's refer to each other. Figure 8A and Figure 8BAn organic layer 106' may be formed on the first insulating layer 103 to cover the gate electrode GE. The relationship between the first initial thickness TH1', the second initial thickness TH2', and the third initial thickness TH3' of the organic layer 106' is substantially the same as that described above. The portion of the organic layer 106' that overlaps with the side surface of the gate electrode GE may form a third angle θ3 with the upper surface of the first insulating layer 103. In an embodiment, the first angle θ1 may be substantially the same as the third angle θ3.

[0121] Let's refer to each other. Figure 8B and Figure 8C In this embodiment, the organic layer 106' flows and changes its shape over time, resulting in the formation of a third insulating layer 106. The flow and shape-changing process of the organic layer 106' is substantially the same as described above. Figures 5A to 5C The descriptions are similar.

[0122] In an embodiment, for example, due to the flow of the organic layer 106', the thickness (or the first initial thickness TH1') of the portion of the organic layer 106' disposed on the upper surface of the gate electrode GE can be reduced to the first thickness TH1. The second initial thickness TH2' and the third initial thickness TH3' can also be changed to the second thickness TH2 and the third thickness TH3, respectively, through the flow of the organic layer 106'. (See reference...) Figure 8B and Figure 8C The second thickness TH2 is shown as being less than the second initial thickness TH2', and the third thickness TH3 is shown as being less than the third initial thickness TH3'. However, this disclosure is not limited to this. In another embodiment, the second thickness TH2 may be greater than the second initial thickness TH2', and the third thickness TH3 may be greater than the third initial thickness TH3'. Due to the flow of the organic layer 106', the third angle θ3 may also become the second angle θ2. In an embodiment, the second angle θ2 may be less than the third angle θ3. As described above, the flow of the organic layer 106' and the subsequent formation of the third insulating layer 106 can mitigate the tilt caused by the side surface of the gate electrode GE.

[0123] According to embodiments of the present disclosure as described above, a display device is provided, the display device including an insulating layer disposed on a gate electrode, and capable of mitigating tilt caused by the side surface of the gate electrode.

[0124] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art.

[0125] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, characterized in that... The display device includes: First insulating layer; A first electrode is disposed on the first insulating layer and includes a lower surface that contacts the upper surface of the first insulating layer, an upper surface opposite to the lower surface, and a side surface that connects the upper surface and the lower surface. A second insulating layer is disposed on the first electrode, overlapping the upper surface and the side surface of the first electrode, and comprising an inorganic insulating material; and The third insulating layer is disposed on the second insulating layer. The first and second portions of the upper surface of the second insulating layer face each other, and there is a gap around the line where the upper surface of the first insulating layer and the side surface of the first electrode intersect each other. A portion of the third insulating layer is disposed in the gap.

2. The display device according to claim 1, characterized in that... The thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode is less than the thickness of the portion of the second insulating layer that overlaps with the upper surface of the first electrode.

3. The display device according to claim 1, characterized in that: The thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode is less than the thickness of the portion of the third insulating layer that overlaps with the side surface of the first electrode.

4. The display device according to claim 1, characterized in that... The first tilt angle formed by the side surface of the first electrode relative to the upper surface of the first insulating layer is greater than the second tilt angle formed by the upper surface of the portion of the third insulating layer that overlaps with the side surface of the first electrode and the upper surface of the first insulating layer.

5. The display device according to claim 4, characterized in that... The second tilt angle is in the range of 50 to 60 degrees.

6. A display device, characterized in that... The display device includes: First insulating layer; A first electrode is disposed on the first insulating layer and includes a lower surface that contacts the upper surface of the first insulating layer, an upper surface opposite to the lower surface, and a side surface that connects the upper surface and the lower surface. A third insulating layer is disposed on the first electrode, overlapping the upper surface and the side surface of the first electrode, and comprising an organic insulating material; and The second insulating layer is disposed on the third insulating layer and comprises an inorganic insulating material. Wherein, the first tilt angle formed by the side surface of the first electrode relative to the upper surface of the first insulating layer is greater than the second tilt angle formed by the upper surface of the portion of the third insulating layer overlapping the side surface of the first electrode relative to the upper surface of the first insulating layer, and The third insulating layer is in direct contact with the upper surface and the side surface of the first electrode.

7. The display device according to claim 6, characterized in that... The thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode is less than the thickness of the portion of the second insulating layer that overlaps with the upper surface of the first electrode.

8. The display device according to claim 6, characterized in that... The thickness of the portion of the third insulating layer that overlaps with the upper surface of the first electrode is less than the thickness of the portion of the third insulating layer that overlaps with the side surface of the first electrode.

9. The display device according to claim 6, characterized in that... The maximum thickness of the third insulating layer is less than the thickness of the first electrode.

10. The display device according to claim 6, characterized in that... The second tilt angle is in the range of 50 to 60 degrees.

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