Digital board card testing tool based on universality

Abstract

The utility model relates to the technical field of electronic equipment manufacturing and testing, in particular to a digital board card testing tool based on universality. The detection module is connected with a to-be-detected digital board card; comprising a general signal test board and an adapter board. By arranging an interface chip, an IO pin of an FPGA chip is converted into a fixed test signal pin; by arranging the connector, the to-be-tested signal obtained from the to-be-tested digital board card is led out through the connector, and the universality test of the to-be-tested digital board card is completed; the problems of resource waste, high cost and long time consumption of design and development caused by repeated design of test tool hardware when multiple types of digital board cards to be tested are tested are solved.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic equipment manufacturing test technical field, concretely relates to a kind of digital board card test tool based on universality. BACKGROUND

[0002] Test tool is a kind of device for placing equipment or product to be tested, and controlling test point to test. Usually a kind of equipment or product to be tested needs a test tool, and some equipment or product has very little output but needs to specially design a corresponding test tool, which leads to the increase of research and development cost, and also causes different degrees of resource waste. When equipment or product is tested, a test tool that can be compatible with multiple equipment or product can save research and development cost and avoid resource waste for research and development platform.

[0003] In the process of electronic equipment manufacturing or research and development, various tests need to be carried out in order to verify the performance, quality or safety of equipment. Test tool is a carrier or platform used to perform these test work. It is usually composed of the following key parts: positioning device, clamping device, test interface, control system, and is widely used in communication system, engineering test, electronic equipment manufacturing and other fields.

[0004] At present, when digital board card is tested, there are the following situations:

[0005] 1. When single type digital board card is tested, a test tool is specially designed for it to meet the test of its function and performance. Once the digital board card is no longer produced, the test tool is no longer used, and its use scenario is shown in the accompanying Figure 1 .

[0006] 2. When multiple types of digital board card are tested, a corresponding number of test tools are customized, the design cost is high, the time is long, and it needs to be redesigned each time, which consumes a lot of time and energy of design personnel, and its use scenario is shown in the accompanying Figure 2 .

[0007] A set of test tools can only test one type of digital board card, which leads to resource waste, lack of flexibility and high test cost. The design time of test tool is long, which increases the development cycle of digital board card. CONTENT OF UTILITY MODEL

[0008] The utility model discloses to the current test tool can only test a kind of digital board, leading to resource waste, lack of flexibility, test cost is high;Test tool design time is long, increases the problem of digital board development cycle, and a kind of digital board test tool based on commonality is proposed;With the digital board to be measured connection;Including general signal test board, adapter plate;Through setting interface chip, the IO pin of FPGA chip is changed into fixed test signal pin;Through setting connector, the signal to be measured obtained from the digital board to be measured is led out through connector, and the commonality test to the digital board to be measured is completed;The problem of resource waste, high cost and long design development time caused by repeated design test tool hardware when testing multiple types of digital board to be measured is solved.

[0009] The utility model discloses the following specific implementation contents:

[0010] A kind of digital board test tool based on commonality, with the digital board to be measured connection;Including general signal test board, adapter plate;

[0011] One end of the adapter plate is connected with the digital board to be measured, and the other end is connected with general signal test board through cable;

[0012] The general signal test board includes FPGA chip, interface chip, connector;

[0013] The interface chip is connected with the IO pin of FPGA chip;

[0014] The FPGA chip is connected with adapter plate by interface chip;

[0015] The FPGA chip is connected with host computer by connector;

[0016] The interface chip is used to change the IO pin of FPGA chip into fixed test signal pin;

[0017] The connector is used to lead out the signal to be measured obtained from the digital board to be measured through connector, and complete the commonality test to the digital board to be measured.

[0018] To better realize the utility model, further, the interface chip includes GTX interface chip, CAN interface chip, RS232 interface chip, LVDS interface chip, RS422 / RS485 interface chip;

[0019] The FPGA chip includes first FPGA chip, second FPGA chip;

[0020] The first FPGA chip is connected with the GTX interface chip, CAN interface chip, RS232 interface chip;

[0021] The second FPGA chip is connected with the GTX interface chip, the LVDS interface chip and the RS422 / RS485 interface chip.

[0022] In order to better realize the utility model, further, the digital board card test tool based on universality further includes a repeater, a high-speed connector and a socket.

[0023] One end of the repeater is connected with one end of the high-speed connector, and the other end of the repeater is connected with the GTX interface chip.

[0024] One end of the socket is connected with the CAN interface chip, the RS232 interface chip, the LVDS interface chip and the RS422 / RS485 interface chip, and the other end is connected with the adapter plate.

[0025] In order to better realize the utility model, further, the digital board card test tool based on universality further includes a voltage conversion chip.

[0026] The input end of the voltage conversion chip inputs 5V voltage, and the output end outputs 3.3V voltage, 1.8V voltage, 1.2V voltage, 1.0V voltage and 2.5V voltage.

[0027] In order to better realize the utility model, further, the digital board card test tool based on universality further includes a reset chip.

[0028] The input end of the reset chip inputs 3.3V voltage, and the output end is connected with the first FPGA chip.

[0029] In order to better realize the utility model, further, the digital board card test tool based on universality further includes a clock distribution chip, a clock frequency conversion distribution chip, an attenuator and an SMA connector.

[0030] The input end of the clock distribution chip inputs 100MHZ signal, and the output end is connected with the first FPGA chip and the clock frequency conversion distribution chip.

[0031] The output end of the clock frequency conversion distribution chip is connected with the attenuator, and the attenuator outputs 25M, 125M, 25M, 32.512M and 100M signals.

[0032] The output end of the attenuator is connected with the SMA connector.

[0033] In order to better realize the utility model, further, the universal signal test board and the adapter plate both include a QSFP interface.

[0034] One end of the QSFP interface of the universal signal test board is connected with the QSFP interface of the adapter board through a DAC / optical fiber cable, and the other end of the QSFP interface of the universal signal test board is connected with the repeater.

[0035] The utility model has the following beneficial effects:

[0036] (1) The utility model discloses a universal signal test board and adapter board, wherein the universal signal test board is a universal module, and the core chip in the universal signal test board is two high-performance FPGAs, and the resources of the two high-performance FPGAs are enough to cover the function test of the digital board card.

[0037] (2) The utility model discloses a universal signal test board and adapter board, wherein the universal signal test board is a universal module, and the core chip in the universal signal test board is two high-performance FPGAs, and the resources of the two high-performance FPGAs are enough to cover the function test of the digital board card.

[0038] (3) The utility model discloses a universal signal test board and adapter board, wherein the universal signal test board is a universal module, and the core chip in the universal signal test board is two high-performance FPGAs, and the resources of the two high-performance FPGAs are enough to cover the function test of the digital board card. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 It is single product test schematic diagram.

[0040] Figure 2 It is multi-class product test schematic diagram.

[0041] Figure 3 It is the design principle block diagram provided by the utility model.

[0042] Figure 4 It is the universal signal test board principle block diagram provided by the utility model.

[0043] Figure 5 It is the CAN chip circuit diagram provided by the utility model.

[0044] Figure 6 It is the RS232 chip circuit diagram provided by the utility model.

[0045] Figure 7 It is the RS422 / 485 signal receiving circuit diagram provided by the utility model.

[0046] Figure 8 The utility model provides RS422 / 485 signal transmission circuit diagram.

[0047] Figure 9 The utility model provides power voltage conversion chip circuit diagram.

[0048] Figure 10 The utility model provides reset chip circuit diagram.

[0049] Figure 11 The utility model provides clock distribution chip circuit diagram.

[0050] Figure 12 The utility model provides network transmission chip circuit diagram.

[0051] Figure 13 The utility model provides transformer circuit diagram.

[0052] Figure 14 The utility model provides data storage chip circuit diagram.

[0053] Figure 15 The utility model provides clock crystal oscillator circuit diagram.

[0054] Figure 16 The utility model provides program storage chip circuit diagram.

[0055] Figure 17 The utility model provides voltage conversion chip circuit diagram.

[0056] Figure 18 The utility model provides high speed signal connection principle block diagram.

[0057] Figure 19 The utility model provides low speed signal interconnection structure drawing.

[0058] Figure 20 The utility model provides repeater chip circuit diagram. DETAILED DESCRIPTION

[0059] In order to more clearly illustrate the technical scheme of the utility model embodiment, below will combine the drawings in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, should understand, the described embodiment only is a part of the embodiment of the utility model, instead of all the embodiment, therefore should not be regarded as the limitation of the protection scope. Based on the embodiment in the utility model, all other embodiments that the ordinary skill in the art obtains without making the creative labor, belong to the scope of the utility model protection.

[0060] In the description of the utility model, it is necessary to explain that, unless there is definite stipulation and limitation, the term "arrangement", "connection", "connection" should be broad sense understanding, for example, can be fixed connection, also can be detachable connection, or integrally connected;Can be mechanical connection, also can be electrical connection;Also can be direct connection, also can be indirectly connected through intermediate medium, can be the intercommunication of two elements inside.For the ordinary skill in the art, the specific meaning of the above-mentioned terms in the utility model can be understood according to the specific circumstances.

[0061] Embodiment 1

[0062] The embodiment provides a kind of digital board test tool based on universality, connect with the digital board to be measured;As shown in Figure 3 It includes universal signal test board, adapter plate;

[0063] One end of the adapter plate is connected with the digital board to be measured, and the other end is connected with universal signal test board through cable;

[0064] The universal signal test board includes FPGA chip, interface chip, connector;

[0065] The interface chip is connected with the IO pin of the FPGA chip;

[0066] The FPGA chip is connected with adapter plate through interface chip;

[0067] The FPGA chip is connected with host computer through connector;

[0068] The interface chip is used to change the IO pin of FPGA chip into fixed test signal pin;

[0069] The connector is used to lead out the test signal obtained from the digital board to be measured through connector, and complete the universality test of the digital board to be measured.

[0070] Working principle: the embodiment changes the IO pin of FPGA chip into fixed test signal pin by setting interface chip;Through the setting connector, the test signal obtained from the digital board to be measured is led out through the connector, and the universality test of the digital board to be measured is completed;Solve the problem of resource waste, high cost and long time of design and development caused by repeated design of test tool hardware when testing multiple types of digital board to be measured.

[0071] Embodiment 2

[0072] The embodiment is based on the above-mentioned embodiment 1, as Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8As shown, the structure of the interface chip and the FPGA chip is described in one specific embodiment.

[0073] The interface chip includes a GTX interface chip, a CAN interface chip, an RS232 interface chip, an LVDS interface chip, and an RS422 / RS485 interface chip.

[0074] The FPGA chip includes a first FPGA chip and a second FPGA chip.

[0075] The first FPGA chip is connected with the GTX interface chip, the CAN interface chip, and the RS232 interface chip.

[0076] The second FPGA chip is connected with the GTX interface chip, the LVDS interface chip, and the RS422 / RS485 interface chip.

[0077] Working principle: The design principle block diagram of the universal signal test board of the embodiment is as shown in Figure 4 The test board adopts standardized mature circuit design, and meanwhile, the specific functional requirements of the design are formed into independent functional modules. In order to meet the test requirements of multiple types of digital boards, two FPGA (Field Programmable Gate Array, which is an abbreviation of Field Programmable Gate Array, is a programmable logic device) chips are used for combined design. Both of the two FPGA chips have a minimum system capable of independent operation. According to different test requirements, one or both of the FPGA chips can be freely selected to complete the function and performance test of the digital board under test. The IO pins of the FPGA are connected with peripheral transceiver interface chips to realize CAN, LVDS, RS422, RS485, and other interface signals and LVTTL, LVCOMS, and other discrete signals. The interface signals and discrete signals are connected to the connector and the adapter plate for interconnection, and meanwhile, serial port and Ethernet interface are designed to communicate with the upper computer to complete the test instruction issuing and test information data returning.

[0078] The RS232 level conversion chip set in the embodiment is MAX3232EUE+, the RS422 / RS485 level conversion chip set in the embodiment is MAX3030EESE+ and MAX3096EESE+, the LVDS level conversion chip set in the embodiment is MAX9129EUE+ and MAX9122EUE+, and the CAN level conversion chip set in the embodiment is SN65HVD230QDG4Q1.

[0079] As shown in Figure 5 The CAN chip circuit includes a CAN chip U24, capacitors C249, C250, C251, C252, and a resistor R225. The input end of the CAN chip is connected with the output end of the voltage conversion chip, and a 3.3V voltage is input.

[0080] As shown in Figure 6 , the RS232 chip circuit includes RS232 chip U20, capacitor C172, capacitor C177, capacitor C174, capacitor C178, capacitor C193, capacitor C198, capacitor C199, capacitor C200, resistor R158, resistor R163, resistor R167, resistor R175, resistor R154, resistor R164, resistor R168, resistor R176, resistor R159, resistor R165, resistor R169, and resistor R177; the input end of the RS232 chip is connected with the output end of the voltage conversion chip, and 3.3V voltage is input.

[0081] As shown in Figure 7 , the RS422 / 485 signal receiving circuit includes chip U104, which is SM3096, and the input end inputs 3.3V voltage; as shown in Figure 8 , the RS422 / 485 signal sending circuit includes chip U164, which is SM3030, and the input end inputs 3.3V voltage.

[0082] As shown in Figure 4 , the first FPGA chip is FPGA-XC7K325T-2FF900I, and the second FPGA chip is FPGA-XC7Z045-2FFG676I.

[0083] The other parts of the embodiment are the same as those of the above-mentioned embodiment 1, and thus will not be described again.

[0084] Embodiment 3

[0085] The embodiment is based on any one of the above-mentioned embodiments 1-2, as shown in Figure 4 , Figure 18 , Figure 19 , Figure 20 , a specific embodiment is used to explain the high-speed signal connection.

[0086] The universal-based digital board card test tool further includes a repeater, a high-speed connector, and a socket.

[0087] One end of the repeater is connected with one end of the high-speed connector, and the other end of the repeater is connected with the GTX interface chip.

[0088] One end of the socket is connected with the CAN interface chip, the RS232 interface chip, the LVDS interface chip, and the RS422 / RS485 interface chip, and the other end is connected with the adapter plate.

[0089] Working principle: the interface of the universal tooling and the interface on the universal tooling are consistent, the number changes according to the test function of the digital board card; the fixed cable is used between the two; there are two design points: ① in order to ensure that the communication between the high-speed signals will not have signal integrity problems, the repeater is placed on the adapter plate and the universal tooling, the high-speed signal passes through the high-speed interface, and then passes through the DAC / optical fiber cable, which will cause signal loss, and the repeater will make up for this part of the loss, so that the signal integrity is not damaged, thereby achieving the function of long-distance transmission. The principle diagram is shown in Figure 18 . ② the interconnection of low-speed signals is to use the European ERNI 973028ZD type female socket, the male connector connected to the female socket is welded on the customized small printed board, the signal is led out through the welding hole, and the low-speed signal cable is designed at both ends, which is convenient for plugging and troubleshooting, and can be reused. The structure diagram is shown in Figure 19 .

[0090] As shown in Figure 20 , the repeater chip circuit includes repeater chip U21, capacitor C91, capacitor C92, capacitor C93, capacitor C94, capacitor C107, capacitor C95, capacitor C99, capacitor C111, capacitor C108, capacitor C112, capacitor C116, capacitor C117, capacitor C118, capacitor C119, capacitor C101, capacitor C102, capacitor C103, capacitor C105, capacitor C106, capacitor C120, capacitor C121, capacitor C122, capacitor C123, capacitor C124, capacitor C125, capacitor C126, capacitor C127, capacitor C128, capacitor C129, capacitor C130, capacitor C131, capacitor C132, capacitor C133, capacitor C134, capacitor C135, capacitor C136, capacitor C137, capacitor C138, capacitor C139, resistor R287, resistor R290, resistor R291.

[0091] The other parts of the embodiment are the same as any one of the above embodiments 1-embodiment 2, so they are not described again.

[0092] Embodiment 4:

[0093] Based on any one of the above embodiments 1-embodiment 3, as shown in Figure 9 , Figure 17 , a specific structure of the voltage conversion chip is described in a specific embodiment.

[0094] The universal digital board card test tool based on the universality further includes a voltage conversion chip;

[0095] The input end of the voltage conversion chip inputs 5V voltage, and the output end outputs 3.3V voltage, 1.8V voltage, 1.2V voltage, 1.0V voltage and 2.5V voltage.

[0096] Working principle: the power supply voltage conversion chip circuit proposed in the embodiment comprises a power supply voltage conversion chip LTM4644IY#PBF; the hardware of the embodiment is composed of a general signal test board and an adapter board, wherein the general signal test board is a general module, the core chip in the general module is two high-performance FPGAs, the resources of the two high-performance FPGAs are sufficient to cover the function test of the digital board card, part of the pins of the two high-performance FPGAs are converted into fixed test signal pins through CAN, RS422 / RS485, RS232 and LVDS chips, and then the different voltage signals are tested through a voltage conversion chip. Figure 17 As shown in the figure, the signals related to the digital board card are led out in this way, and the universality test of the signals of the digital board card is realized.

[0097] For different types of digital board cards, only the adapter board needs to be redesigned; the to-be-tested signals on the digital board card are led out in the form of the interface of the general tooling through the adapter board, and then the test environment is built by connecting through the fixed test cable, wherein the general tooling and the test cable are reusable, and the interface signal interconnection is completed at this step.

[0098] Thus, the test cost is reduced, resource waste is avoided, the hardware design difficulty is reduced, and the design and development cycle of the digital board card is shortened.

[0099] The other parts of the embodiment are the same as any one of the above-mentioned embodiment 1 to embodiment 3, and thus will not be described herein again.

[0100] Embodiment 5

[0101] As shown in the figure, the structure of the reset chip is described in a specific embodiment on the basis of any one of the above-mentioned embodiment 1 to embodiment 4. Figure 10

[0102] The general-purpose digital board card test tooling further comprises a reset chip.

[0103] The input end of the reset chip inputs 3.3V voltage, and the output end is connected with the first FPGA chip.

[0104] Working principle: as shown in the figure, the reset chip circuit comprises a reset chip U10, resistors R94, R95 and R96, a capacitor C174 and a switch S2. Figure 10

[0105] ​​The reset chip U10 is CAT811STBI-GT3, and the switch S2 is TC-0204-Z.

[0106] The other parts of this embodiment are the same as any one of the embodiments 1-4 above, so they will not be described again.

[0107] Example 6:

[0108] This embodiment is based on any one of the embodiments 1-5 above, such as Figure 11 As shown, the structure of the clock distribution chip is illustrated with a specific embodiment.

[0109] The general-purpose digital board test fixture also includes a clock distribution chip, a clock frequency conversion distribution chip, an attenuator, and an SMA connector;

[0110] The clock distribution chip receives a 100MHz signal at its input terminal and its output terminal is connected to the first FPGA chip and the clock frequency conversion distribution chip.

[0111] The output of the clock frequency conversion distribution chip is connected to the attenuator, and outputs 25M, 125M, 25M, 32.512M, and 100M signals to the attenuator.

[0112] The output of the attenuator is connected to an SMA connector.

[0113] Working principle: such as Figure 11 As shown, the clock distribution chip circuit includes a clock distribution chip U22, capacitors C275, C276, C277, C278, C279, C280, C281, C282, C283, and C284, resistors R194, R195, R196, R197, R198, R199, and R206, and a ferrite bead FB10; the clock distribution chip U22 is an ADCLK950BCPZ.

[0114] The other parts of this embodiment are the same as any one of the above embodiments 1-5, so they will not be described again.

[0115] Example 7:

[0116] This embodiment is based on any one of the embodiments 1-6 above, such as Figure 18 As shown, both the general signal test board and the adapter board include a QSFP interface;

[0117] One end of the QSFP interface of the general signal test board is connected to the QSFP interface of the adapter board via a DAC / fiber optic cable, and the other end of the QSFP interface of the general signal test board is connected to a repeater.

[0118] Working principle: This embodiment is based on high-speed long-distance signal communication using a QSFP interface, and is also compatible with DAC cables and optical modules.

[0119] The other parts of this embodiment are the same as any one of the embodiments 1 to 6 above, so they will not be described again.

[0120] Example 8:

[0121] This embodiment is based on any one of embodiments 1-7 above, such as... Figure 12 As shown, it also includes a network transmission chip circuit, which includes a network transmission chip U23, and the network transmission chip U23 is 88E1215;

[0122] like Figure 13 As shown, it also includes a transformer circuit, which includes a network transformer chip U23, and the network transformer chip is EPG4014SE-RC.

[0123] In this embodiment, the network transmission chip U23 is a PHY chip. One end is connected to the first FPGA chip, and the other end is connected to the RJ45 connector 56S-8P / 8C-G / Y through the transformer EPG4014SE-RC.

[0124] like Figure 14 As shown, it also includes a data storage chip circuit, which includes a data storage chip U31; in this embodiment, the data storage chip U31 is a DDR chip MT41K256M16TW-107XIT, which is connected to the first FPGA chip.

[0125] like Figure 15 As shown, this embodiment also includes a clock crystal circuit, which includes a crystal Y4, a ferrite bead FB28, capacitors C285, C283, and C284, and resistors R308 and R307.

[0126] The clock crystals include XO75-NAGRC-100MHz and XO75-NAGRC-50MHz.

[0127] like Figure 16 The diagram shows a program memory chip circuit, which includes program memory chip U13 and program memory chip U8; program memory chip U8 is S25FL256SAGNFI000, and program memory chip U13 is S25FL256SAGMFIR01.

[0128] The external interfaces of the universal digital board testing fixture proposed in this embodiment are as follows:

[0129] Program download interface: 1734260-8, using downloader and its connection;

[0130] High-speed interface: QSFP interface is adopted, and 2-3 meter DAC / fiber cable and adapter plate are selected for long-distance transmission connection;

[0131] Low-speed bus interface: ERNI 973028ZD female socket is adopted, and 2-3 meter cable and adapter plate are made of 0.35 square white cable for connection;

[0132] Discrete wire interface: ERNI 973028ZD female socket is adopted, and 2-3 meter cable and adapter plate are made of 0.35 square white cable for connection;

[0133] Network interface: RJ45 interface is adopted, and ordinary network cable and host computer are connected;

[0134] Clock interface: SMA interface is adopted, and RF cable and adapter plate are connected;

[0135] The adapter plate is mainly divided into digital board card (to be tested product) interface and general tooling interface and a small amount of chip related to interface signal integrity.

[0136] The digital board card interface is the interface type matched with the digital board card, and the type is not fixed, and the corresponding interface is matched with different digital board cards, and the two are connected in a straight insertion manner.

[0137] The other parts of the embodiment are the same as any one of the above embodiments 1-7, and will not be repeated.

[0138] The above is only the preferred embodiment of the present application, and does not limit the present application in any form, and any simple modification, equivalent change according to the technical essence of the present application to the above embodiment, all falls within the protection scope of the present application.

Claims

1. A universal digital board testing fixture, connected to the digital board under test; characterized in that, Includes general signal test boards and adapter boards; One end of the adapter board is connected to the digital board under test, and the other end is connected to a general signal test board via a cable; The general signal test board includes an FPGA chip, an interface chip, and a connector; The interface chip is connected to the IO pins of the FPGA chip; The FPGA chip is connected to the adapter board via an interface chip; The FPGA chip is connected to the host computer via a connector. The interface chip is used to convert the IO pins of the FPGA chip into fixed test signal pins. The connector is used to lead out the test signal obtained from the digital board under test through the connector to complete the generality test of the digital board under test.

2. The universal digital board testing fixture according to claim 1, characterized in that, The interface chips include GTX interface chip, CAN interface chip, RS232 interface chip, LVDS interface chip, and RS422 / RS485 interface chip; The FPGA chip includes a first FPGA chip and a second FPGA chip; The first FPGA chip is connected to the GTX interface chip, CAN interface chip, and RS232 interface chip. The second FPGA chip is connected to the GTX interface chip, LVDS interface chip, and RS422 / RS485 interface chip.

3. The universal digital board testing fixture according to claim 2, characterized in that, The general-purpose digital board test fixture also includes repeaters, high-speed connectors, and sockets; One end of the repeater is connected to one end of the high-speed connector, and the other end of the repeater is connected to the GTX interface chip; One end of the socket is connected to the CAN interface chip, RS232 interface chip, LVDS interface chip, and RS422 / RS485 interface chip, and the other end is connected to the adapter board.

4. The universal digital board testing fixture according to claim 2, characterized in that, The general-purpose digital board test fixture also includes a voltage conversion chip; The voltage conversion chip receives a 5V input and outputs 3.3V, 1.8V, 1.2V, 1.0V, and 2.5V.

5. A universal digital board testing fixture according to claim 4, characterized in that, The general-purpose digital board test fixture also includes a reset chip; The reset chip receives a 3.3V voltage at its input terminal and its output terminal is connected to the first FPGA chip.

6. The universal digital board testing fixture according to claim 2, characterized in that, The general-purpose digital board test fixture also includes a clock distribution chip, a clock frequency conversion distribution chip, an attenuator, and an SMA connector; The clock distribution chip receives a 100MHz signal at its input terminal and its output terminal is connected to the first FPGA chip and the clock frequency conversion distribution chip. The output of the clock frequency conversion distribution chip is connected to the attenuator, and outputs 25M, 125M, 25M, 32.512M, and 100M signals to the attenuator. The output of the attenuator is connected to an SMA connector.

7. The universal digital board testing fixture according to claim 3, characterized in that, Both the general signal test board and the adapter board include a QSFP interface; One end of the QSFP interface of the general signal test board is connected to the QSFP interface of the adapter board via a DAC / fiber optic cable, and the other end of the QSFP interface of the general signal test board is connected to a repeater.

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