256-channel nuclear pulse waveform acquisition electronics system
By combining a high-sampling-channel ADC and an FPGA chip, a nuclear imaging electronics system with 256 channels, a 40MHz sampling rate, and 12-bit sampling precision was designed. This solved the problem of insufficient sampling channel number and precision in the existing technology, and achieved high integration and high-performance nuclear imaging effect.
Patent Information
- Application Number
- CN202520640357.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2035-04-07
AI Technical Summary
Existing nuclear imaging equipment suffers from insufficient sampling channels and sampling accuracy in acquiring simulated pulse signals from detectors, resulting in the inability to fully preserve pulse information and affecting the integration and performance of the imaging system.
Using the ADS52J90 high-speed ADC chip with 8 high sampling channels and the Xilinx Kintex7 series FPGA chip, combined with high-density connectors, high-speed operational amplifiers and differential amplifiers, a nuclear imaging electronics system with 256 channels, 40MHz sampling rate and 12-bit sampling precision is designed. The FPGA processing module realizes signal synchronization and data transmission.
It achieves highly integrated and high-performance nuclear imaging capabilities, improves signal anti-interference capabilities and flexible signal input impedance matching, and meets the hardware design requirements of nuclear imaging systems.
Smart Images
Figure CN223955980U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to nuclear imaging technical field relates to a kind of multi-channel, high sampling rate, high sampling precision nuclear imaging electronics, especially in 256 channel nuclear pulse waveform acquisition electronics system. BACKGROUND
[0002] Nuclear imaging as an advanced imaging technology, has been widely used in medical diagnosis, nuclear power plant monitoring, nuclear accident handling and other fields. The current mainstream nuclear imaging equipment includes: CT, PET, PET-CT and PET-MRI and other high-end medical diagnosis and treatment equipment, for radiation source positioning and searching, nuclear power plant internal radioactive hotspot monitoring, security check, nuclear decommissioning, gamma imaging instrument for post-processing.
[0003] Nuclear imaging system is mainly composed of detector system, electronics system, computer system three parts, as shown in Figure. Figure 1 As one of the key subsystems, electronics system undertakes the analog pulse acquisition of detector signal, FPGA digital processing and digital signal transmission and other work.
[0004] Especially in the aspect of analog pulse acquisition of detector signal, its performance is particularly critical. Because for nuclear imaging system, the imaging information obtained by front-end detector is first converted into nuclear pulse signal in the detector, and the number of signals is often hundreds of thousands. Then these signals will be collected by ADC of nuclear imaging electronics system, and then converted into digital signal, and then transmitted to FPGA for signal processing and signal transmission. Therefore, the more the number of signal channels collected by ADC, the higher the sampling rate and sampling precision, the more complete the pulse information can be saved under the limited volume of electronics system, so as to finally realize the function of high integration and high performance of nuclear imaging. Therefore, how to improve the sampling channel, sampling rate and sampling precision of nuclear pulse waveform acquisition electronics system is a problem to be solved. Utility model content
[0005] The utility model discloses a 256 channel nuclear pulse waveform collection electronics system in view of the prior art problem, and the purpose lies in providing a 256 channel nuclear pulse waveform collection electronics system, the scheme is a novel multi -channel, high sampling rate, high sampling accuracy nuclear imaging electronics system, adopts 8 high integration ADC chips and field programmable gate array (FPGA, hereinafter referred to as FPGA) based on JESD204B / LVDS interface as the core module, selects 16 high density connectors as the input interface of 256 analog signals, selects 128 AD8039 chips as the input buffer of 256 analog signals, selects 128 ADA4950-2 chips to drive the analog differential input port of ADC chip, selects LMK04832 chip to provide high-precision programmable clock / synchronous signal based on JESD204B protocol, selects high-precision clock buffer CDCLVD1208 chip to realize JESD204B clock / synchronous signal 1:8 fanout, realizes a 256 channel, 40MHz sampling rate, 12bit sampling accuracy ultra-high density nuclear imaging electronics system, supports 256 channel analog pulse signal to be handled simultaneously with 40MHz signal sampling rate, 12bit signal sampling accuracy.
[0006] The key points of the application include:
[0007] 1, 8 high-speed ADC chips ADS52J90 with the highest sampling channel number in the industry at present are combined with Kintex7 series high-capacity FPGA chips XC7K480T-2FFG1156 of Xilinx company, and the data acquisition and processing of 256 channel nuclear pulse signals are realized.
[0008] 2, the FPGA is used to program LMK04832 chip, and the board-level JESD204B clock and data synchronization are provided through the fanout mode of 4 CDCLVD1208 chips.
[0009] 3, 16 high-density connectors FCS8-20-01-L-S-A-TR of Samtec company are used, each connector processes 16 signals, and a 256 channel nuclear pulse signal input interface module is formed.
[0010] 4, 128 AD8039 chips are used as the input buffer of 256 analog pulse signals.
[0011] 5, 128 ADA4950-2 chips are used to realize the single-ended to differential function of 256 analog pulse signals.
[0012] The technical scheme of the utility model includes:
[0013] A 256-channel nuclear pulse waveform acquisition electronics system, characterized in that it comprises
[0014] a 256-channel nuclear pulse signal input interface module 1 for receiving 256-channel nuclear pulse signals input from outside;
[0015] a 256-channel nuclear pulse signal input buffer module 2 for buffering 256-channel nuclear pulse signals output by the 256-channel nuclear pulse signal input interface module 1;
[0016] a 256-channel single-ended to differential module 4 for performing single-ended to differential processing on 256-channel nuclear pulse signals buffered by the 256-channel nuclear pulse signal input buffer module 2, to obtain 256-channel analog differential signals and input them to an ADC module 5;
[0017] an ADC module 5 for performing analog-to-digital conversion on 256-channel analog differential signals, to obtain 256-channel digital differential signals and input them to an FPGA processing module 6;
[0018] an FPGA processing module 6 for processing 256-channel digital differential signals;
[0019] a high-precision system programmable clock module 14 for generating 5-channel clock signals according to the configuration of the FPGA processing module 6; wherein a first-channel clock signal is used as a system working clock to input the FPGA processing module 6, a second-channel clock signal is used as a JESD204B SYSREF synchronization signal of the FPGA processing module 6 to input an FPGA-JESD synchronization signal fan-out module 12, a third-channel clock signal is used as a JESD204B data clock signal of the FPGA processing module 6 to input a GTX data clock fan-out module 13, a fourth-channel clock signal is used as a JESD204B SYSREF synchronization signal of the ADC module 5 to input an ADC-JESD synchronization signal fan-out module 17, and a fifth-channel clock signal is used as a JESD204B data clock signal of the ADC module 5 to input an ADC data clock fan-out module 18;
[0020] an FPGA-JESD synchronization signal fan-out module 12 for copying 8 copies of the JESD204B SYSREF synchronization signal from the high-precision system programmable clock module 14 to input the FPGA processing module 6;
[0021] a GTX data clock fan-out module 13 for copying 8 copies of the JESD204B data clock signal from the high-precision system programmable clock module 14 and inputting them to the FPGA processing module 6;
[0022] The ADC-JESD synchronization signal fan-out module 17 is used for copying 8 times the JESD204B SYSREF synchronization signal from the high-precision system programmable clock module 14 and inputting to the ADC module 5.
[0023] The ADC data clock fan-out module 18 is used for copying 8 times the JESD204B data clock signal from the high-precision system programmable clock module 14 and inputting to the ADC module 5.
[0024] Further, the 256-channel nuclear pulse signal input interface module 1 comprises 16 FCS8 series high-density connectors, each of which is used for accessing 16 analog pulse signals.
[0025] Further, the ADC module 5 comprises high-speed ADC chips ADS52J90 with 8 JESD204B / LVDS interfaces, each of which realizes the analog-to-digital conversion function of 32 analog differential signals.
[0026] Further, the FPGA processing module 6 adopts an XC7K480T-2FFG1156 chip; the 256-channel nuclear pulse signal input buffer module 2 adopts 128 double-channel high-speed operational amplifiers AD8039 chips; and the 256-channel single-ended to differential module 4 adopts 128 double-channel high-speed differential amplifier chips ADA4950-2, each of which converts a single-ended input signal into an analog differential signal.
[0027] Further, it further comprises an amplifier power supply module 15 used for providing working voltages for the 256-channel nuclear pulse signal input buffer module 2 and the 256-channel single-ended to differential module 4, and an ADC power supply module 16 used for providing working voltages for the ADC module 5.
[0028] Further, the ADC power supply module 16 adopts 3 LT3070 analog power supply chips to provide AVCC_1V8, DVDD_1V8 and DVDD_1V2 working voltages for the ADC module 5.
[0029] Further, the FPGA-JESD synchronization signal fan-out module 12 adopts a 1:8 fan-out high-precision clock buffer chip CDCLVD1208 to copy 8 times a JESD204B SYSREF synchronization signal from the high-precision system programmable clock module 14 and input the same to the FPGA processing module 6.
[0030] Further, the GTX data clock fan-out module 13 uses a 1:8 fan-out high-precision clock buffer chip CDCLVD1208 to copy 8 copies of the 1-way JESD204B data clock signal from the high-precision system programmable clock module 14 and input into the 8 GTX Quads in the FPGA processing module 6.
[0031] Further, the ADC-JESD synchronization signal fan-out module 17 and the ADC data clock fan-out module 18 are both 1:8 fan-out high-precision clock buffer chips CDCLVD1208.
[0032] Further, the 40-way nuclear pulse signal input interface module 3 is further included, which is used to receive 40-way external trigger signals and input the 40-way external trigger signals into the FPGA processing module 6; the LED module 7 is connected with the FPGA processing module 6 and is used to monitor the power-on working state of the system; the gigabit network module 8 is connected with the FPGA processing module 6 and is used to transmit the data processed by the FPGA processing module 6 to a computer and transmit the control instructions of the computer to the FPGA processing module 6; the USB serial module 9 is connected with the FPGA processing module 6 and is used to realize the USB serial communication between the FPGA processing module 6 and the computer; the memory module 10 is used to store the logic code of the working of the FPGA processing module 6 and automatically load the logic code into the FPGA processing module 6 when the system is powered on; and the system digital power module 11 is used to convert external direct current into the working voltage required by the system.
[0033] The advantages of the utility model are as follows:
[0034] The utility model has the characteristics of simple structure, flexible use, high integration degree and low power consumption, and can completely meet the hardware design requirements of nuclear imaging electronics.
[0035] 1, the Samtec interface used in design has wide frequency band, high pin density and high reliability.
[0036] 2, the input buffer module using AD8039 chip as the core improves the signal anti-interference performance and flexible signal input impedance matching adjustment function of the hardware system.
[0037] 3, the JESD204B clock system designed by the utility model has high precision and simple structure and takes LMK04832 and CDCLVD1208 as the core.
[0038] 4, since each ADS52J90 chip processes 32-way signals, 8 chips can realize 256-channel super-high-density signal acquisition, greatly improving the integration degree of the hardware system. BRIEF DESCRIPTION OF DRAWINGS
[0039] Figure 1 is a nuclear imaging system block diagram.
[0040] Figure 2 is a hardware structure block diagram of the design scheme.
[0041] Wherein, 01 - detector system, 02 - electronic system, 03 - computer system;1 - 256 nuclear pulse signal input interface module, 2 - 256 nuclear pulse signal input buffer module, 3 - 40 nuclear pulse signal input interface module, 4 - 256 single-ended to differential module, 5 - ADC module, 6 - FPGA processing module, 7 - LED module, 8 - Gigabit network module, 9 - USB serial module, 10 - memory module, 11 - system digital power module, 12 - FPGA-JESD synchronization signal fanout module, 13 - GTX data clock fanout module, 14 - high-precision system programmable clock module, 15 - amplifier power module, 16 - ADC power module, 17 - ADC-JESD synchronization signal fanout module, 18 - ADC data clock fanout module. DETAILED DESCRIPTION
[0042] The utility model will be further described in detail below in combination with the drawings, the example is only used for explaining the utility model, and is not used for limiting the range of the utility model.
[0043] The hardware structure block diagram of the utility model scheme is as shown in Figure 2 It includes the following modules:
[0044] 256 nuclear pulse signal input interface module 1: 16 Samtec FCS8 series high-density connectors are used, wherein each connector corresponds to 16 analog pulse signal inputs, and a total of 256 nuclear pulse signal input interfaces are used as external inputs.
[0045] 256 nuclear pulse signal input buffer module 2: 128 ADI double-channel high-speed operational amplifiers AD8039 chips are used as 256 nuclear pulse signal input buffers.
[0046] 40 nuclear pulse signal input interface module 3: 2 Samtec FCS8 series high-density connectors are used, wherein each connector corresponds to 20 signal inputs, and a total of 40 external trigger signal input interfaces are used.
[0047] 256-channel single-ended to differential module 4: 128 ADI double-channel high-speed differential amplifier chip ADA4950-2 is used to realize the function of converting 256-channel single-ended signals into differential signals, so as to enter the next step of ADC module 5 processing; wherein each double-channel high-speed differential amplifier chip ADA4950-2 converts two of the 256-channel nuclear pulse signals as input signals to obtain two analog differential signals.
[0048] ADC module 5: 8 JESD204B / LVDS interface-based high-speed ADC chip ADS52J90, each ADC realizes the function of analog-digital conversion of 32-channel analog differential signals.
[0049] FPGA processing module 6: as the core of the hardware system, the high-performance and large-capacity Kintex7 series XC7K480T-2FFG1156 chip of Xilinx Company is used to complete the data processing of the system. The high-speed serial data output by each ADC after conversion is processed by a GTX module inside the FPGA processing module 6, and 8 GTX modules are used inside the FPGA processing module 6 to acquire and process the data of 256-channel pulse signals according to the system clock.
[0050] LED module 7: contains 8 LED lights, which are used to monitor the power-on working state of the entire hardware system.
[0051] Gigabit network module 8: as a bridge for data communication between FPGA and computer, its bidirectional transmission rate is 1Gbps, which transmits the data processed by FPGA to the computer, and the computer can also send commands to FPGA through this module to control its working state.
[0052] USB serial module 9: CP2102 chip is used to realize the USB serial communication between FPGA and computer.
[0053] Memory module 10: used to store the logic code of FPGA operation, which automatically loads the logic code into FPGA at each power-on of the hardware system.
[0054] System digital power module 11: as a digital switching power module of the system, the external DC 12V power supply generates 1V, 1.5V, 1.8V, 2.5V and 3.3V power supply after passing through the system digital power module 11, which provides digital power supply for the entire hardware system.
[0055] FPGA-JESD synchronization signal fan-out module 12: 1:8 fan-out high-precision clock buffer chip CDCLVD1208 is used to copy 8 copies of 1-channel JESD204B SYSREF synchronization signal from high-precision system programmable clock module 14, and then connect them to the FPGA ordinary IO pin of FPGA processing module 6.
[0056] GTX data clock fan-out module 13: using a 1:8 fan-out high-precision clock buffer chip CDCLVD1208, 1 JESD204B data clock signal from the high-precision system programmable clock module 14 is copied 8 times and connected to 8 GTX quads in the FPGA processing module 6.
[0057] High-precision system programmable clock module 14: using programmable clock chip LMK04832 as the core, after being programmed and configured online by the FPGA in the FPGA processing module 6, 5 clock signals are generated. The first clock signal directly enters the FPGA processing module 6 as the system working clock; the second clock enters the FPGA-JESD synchronization signal fan-out module 12 as the JESD204B SYSREF synchronization signal of the FPGA processing module 6; the third clock signal enters the FPGA's GTX data clock fan-out module 13 as the JESD204B data clock signal of the FPGA processing module 6; the fourth clock signal enters the ADC-JESD synchronization signal fan-out module 17 as the JESD204B SYSREF synchronization signal of the ADC module 5; and the fifth clock signal enters the ADC data clock fan-out module 18 as the JESD204B data clock signal of the ADC end.
[0058] Amplifier power module 15: using LDO power chip to provide ±3.3V working voltage chip for the amplifier chip in the 256-channel nuclear pulse signal input buffer module 2 and the 256-channel single-ended to differential module 4.
[0059] ADC power module 16: using 3 LT3070 analog power chips to provide AVCC_1V8, DVDD_1V8 and DVDD_1V2 working voltage for 8 ADC chips in the ADC module 5.
[0060] ADC-JESD synchronization signal fan-out module 17: using a 1:8 fan-out high-precision clock buffer chip CDCLVD1208, 1 JESD204B SYSREF synchronization signal from the high-precision system programmable clock module 14 is copied 8 times and connected to 8 ADC chips in the ADC module 5, for controlling the synchronization analog-digital conversion of 8 ADC chips in the ADC module 5.
[0061] ADC data clock fan-out module 18: using a 1:8 fan-out high-precision clock buffer chip CDCLVD1208, 1 JESD204B data clock signal from the high-precision system programmable clock module 14 is copied 8 times and connected to 8 ADC chips in the ADC module 5.
[0062] After the circuit board is powered on, the high-precision system programmable clock module 14 is programmed by controlling the FPGA processing module 6, and the high-precision system programmable clock module 14 outputs 5-way clock after programming is completed; one of the clock is as a system clock of the FPGA operation, controls the operation of the USB serial port, LED lamp, gigabit network module and the processing of 256-way signal in FPGA later; the second clock is as FPGA-JESD synchronization signal (i.e. JESD204B SYSREF), the third clock is GTX clock, the second clock and the third clock are a pair, and 1 GTX needs to be normally worked together; since 8 GTXs need to work to process 256-way signal, therefore, the FPGA-JESD synchronization signal and the GTX clock are copied 8 times respectively, and 8 GTXs are normally worked through the FPGA-JESD synchronization signal fan-out module 12 and the GTX data clock fan-out module 13.
[0063] The ADC also needs a pair of clock to normally work, i.e. ADC-JESD synchronization signal and ADC clock, and the pair of clock makes 1 ADC normally work; since 8 ADCs are used to realize 256-way signal acquisition, therefore, the clock signal is copied through the ADC-JESD synchronization signal fan-out module 17 and the ADC data clock fan-out module 18 and then provided to the 8 ADCs.
[0064] After the above design, 256-way pulse data can be normally acquired by the ADC and processed in the GTX kernel of the FPGA processing module 6.
[0065] Although the specific embodiments of the utility model are disclosed for the purpose of illustration, the purpose is to help understanding the content of the utility model and to implement, the person skilled in the art can understand that: various replacements, changes and modifications are possible without departing from the spirit and scope of the utility model and the appended claims. Therefore, the utility model should not be limited to the content disclosed by the best mode of implementation, and the scope of the utility model claimed is the scope defined by the claims.
Claims
1. A 256 channel nuclear pulse waveform acquisition electronics system, characterized by, The application relates to a 256-channel nuclear pulse signal input interface module (1) for receiving externally input 256-channel nuclear pulse signals. The application relates to a 256-channel nuclear pulse signal input buffer module (2) for buffering the 256-channel nuclear pulse signals output by the 256-channel nuclear pulse signal input interface module (1). The application relates to a 256-channel single-ended-to-differential module (4) for performing single-ended-to-differential processing on the 256-channel nuclear pulse signals buffered by the 256-channel nuclear pulse signal input buffer module (2), obtaining 256-channel analog differential signals and inputting the 256-channel analog differential signals to an ADC module (5). The application relates to an ADC module (5) for performing analog-to-digital conversion on the 256-channel analog differential signals, obtaining 256-channel digital differential signals and inputting the 256-channel digital differential signals to an FPGA processing module (6). The application relates to an FPGA processing module (6) for processing the 256-channel digital differential signals. The application relates to a high-precision system programmable clock module (14) for generating 5-channel clock signals according to the configuration of the FPGA processing module (6); wherein the first-channel clock signal is used as a system working clock to input the FPGA processing module (6), the second-channel clock signal is used as a JESD204B SYSREF synchronization signal of the FPGA processing module (6) to input an FPGA-JESD synchronization signal fan-out module (12), the third-channel clock signal is used as a JESD204B data clock signal of the FPGA processing module (6) to input a GTX data clock fan-out module (13), the fourth-channel clock signal is used as a JESD204B SYSREF synchronization signal of the ADC module (5) to input an ADC-JESD synchronization signal fan-out module (17), and the fifth-channel clock signal is used as a JESD204B data clock signal of the ADC module (5) to input an ADC data clock fan-out module (18). The application relates to an FPGA-JESD synchronization signal fan-out module (12) for copying the JESD204B SYSREF synchronization signal from the high-precision system programmable clock module (14) 8 times to input the FPGA processing module (6). The application relates to a GTX data clock fan-out module (13) for copying the JESD204B data clock signal from the high-precision system programmable clock module (14) 8 times to input the FPGA processing module (6). The application relates to an ADC-JESD synchronization signal fan-out module (17) for copying the JESD204B SYSREF synchronization signal from the high-precision system programmable clock module (14) 8 times to input the ADC module (5). The application relates to an ADC data clock fan-out module (18) for copying the JESD204B data clock signal from the high-precision system programmable clock module (14) 8 times to input the ADC module (5). The 256-channel nuclear pulse signal input interface module (1) comprises 16 FCS8 series high-density connectors, and each FCS8 series high-density connector is used for accessing 16 analog pulse signals.
2. The 256-channel nuclear pulse waveform acquisition electronics system of claim 1, wherein, 3. The 256-channel nuclear pulse waveform acquisition electronics system of claim 1, wherein, The ADC module (5) comprises high-speed ADC chips ADS52J90 with 8 JESD204B / LVDS interfaces, each of which realizes the analog-digital conversion function of 32 analog differential signals.
4. The 256-channel nuclear pulse waveform acquisition electronics system of claim 1, wherein, The FPGA processing module (6) adopts an XC7K480T-2FFG1156 chip; the 256-channel nuclear pulse signal input buffer module (2) adopts 128 double-channel high-speed operational amplifiers AD8039 chips; and the 256-channel single-ended to differential module (4) adopts 128 double-channel high-speed differential amplifier chips ADA4950-2, each of which converts a single-ended input signal into an analog differential signal.
5. The 256-channel nuclear pulse waveform acquisition electronics system of any of claims 1-4, wherein, An amplifier power module (15) is further included for providing working voltages for the 256-channel nuclear pulse signal input buffer module (2) and the 256-channel single-ended to differential module (4); and an ADC power module (16) is further included for providing working voltages for the ADC module (5).
6. The 256-channel nuclear pulse waveform acquisition electronics system of claim 5, wherein, The ADC power module (16) adopts 3 LT3070 analog power chips to provide AVCC_1V8, DVDD_1V8 and DVDD_1V2 working voltages for the ADC module (5).
7. The 256-channel nuclear pulse waveform acquisition electronics system of any of claims 1-4, wherein, The FPGA-JESD synchronization signal fan-out module (12) adopts a 1:8 fan-out high-precision clock buffer chip CDCLVD1208 to copy 8 copies of the 1-way JESD204B SYSREF synchronization signal from the high-precision system programmable clock module (14) and input them into the FPGA processing module (6) respectively.
8. The 256-channel nuclear pulse waveform acquisition electronics system of any of claims 1-4, wherein, The GTX data clock fan-out module (13) uses a 1:8 fan-out high-precision clock buffer chip CDCLVD1208 to copy 8 copies of the 1-way JESD204B data clock signal from the high-precision system programmable clock module (14) and input them into the 8 GTX Quads in the FPGA processing module (6).
9. The 256-channel nuclear pulse waveform acquisition electronics system of any of claims 1-4, wherein, The ADC-JESD synchronization signal fan-out module (17) and the ADC data clock fan-out module (18) are both 1:8 fan-out high-precision clock buffer chips CDCLVD1208.
10. The 256-channel nuclear pulse waveform acquisition electronics system of any of claims 1-4, wherein, A 40-channel nuclear pulse signal input interface module (3) is further included for receiving 40 external trigger signals and inputting them into the FPGA processing module (6); An LED module (7) is connected with the FPGA processing module (6) and used for monitoring the power-on working state of the system; A gigabit network module (8) is connected with the FPGA processing module (6) and used for transmitting the data processed by the FPGA processing module (6) to a computer and sending control instructions from the computer to the FPGA processing module (6); A USB serial module (9) is connected with the FPGA processing module (6) and used for realizing the USB serial communication between the FPGA processing module (6) and the computer; and A 40-channel nuclear pulse signal input interface module (3) is further included for receiving 40 external trigger signals and inputting them into the FPGA processing module (6); A memory module (10) is used to store the logic code for the FPGA processing module (6) to work, and automatically loads the logic code into the FPGA processing module (6) when the system is powered on. A system digital power module (11) is used to convert external DC power into the working voltage required by the system.