Bias voltage processing circuit and laser detection device

Abstract

The utility model discloses a bias voltage processing circuit and a laser detection device, and relates to the technical field of laser detection, the bias voltage processing circuit comprises a bias voltage output circuit, a discharge output circuit, an enable circuit and a control circuit, the bias voltage output circuit is used for being arranged between a power supply and a laser detection sensor, and the discharge output circuit is used for being arranged between the power supply and the laser detection sensor. The discharge output circuit is connected with the output end of the bias voltage output circuit and the ground, and the enable circuit is connected with the bias voltage output circuit and the discharge output circuit. And the control circuit is connected with the enable circuit, and is configured as follows: when the control circuit outputs a first / second control signal to the enable circuit, the enable circuit outputs two paths of enable level signals to enable the bias voltage output circuit to be connected / disconnected and the discharge output circuit to be disconnected / connected. According to the bias voltage processing circuit, the residual voltage of the output end can be rapidly discharged, and the response capability of the circuit is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to laser detection technical field, especially a kind of bias voltage processing circuit and laser detection device. BACKGROUND

[0002] At present, laser detection sensor of laser detection device needs to use high-voltage power supply as bias voltage to maintain high photoelectric gain, when laser echo signal is strong, to avoid signal output saturation, bias voltage needs to be closed to reduce photoelectric gain.

[0003] However, since laser detection sensor is very large as bias voltage load impedance, when bias voltage processing circuit closes bias voltage, there is residual voltage at the input end of laser detection sensor (or the output end of bias voltage processing circuit), and the residual voltage drops slowly, which affects the real-time response capability of the circuit. UTILITY MODEL CONTENT

[0004] The utility model embodiment provides a kind of bias voltage processing circuit and laser detection device, to solve the technical problem that the residual voltage of output end drops slowly after existing bias voltage processing circuit stops outputting bias voltage in the related art.

[0005] In a first aspect, a bias voltage processing circuit is provided, comprising:

[0006] a bias output circuit configured to be disposed between a power supply and a laser detection sensor;

[0007] a discharge output circuit connected to an output end of the bias output circuit and ground;

[0008] an enable circuit connected to the bias output circuit and the discharge output circuit;

[0009] a control circuit connected to the enable circuit, configured to:

[0010] when the control circuit outputs a first / second control signal to the enable circuit, the enable circuit outputs two enable level signals to turn on / off the bias output circuit and turn off / on the discharge output circuit.

[0011] In some embodiments, the bias output circuit includes a first resistor, a second resistor, a first capacitor, a second capacitor, a MOS tube and a power supply chip;

[0012] a first end of the first resistor is connected to a first end of the MOS tube and a power supply, a second end of the first resistor is connected to a third end of the MOS tube and the enable circuit, a second end of the MOS tube is connected to an input end of the power supply chip;

[0013] The output end of the power supply chip is connected with the first end of the second resistor, and the second end of the second resistor is used as an output end of the bias output circuit and is connected with a laser detection sensor.

[0014] The first end of the first capacitor is connected with the input end of the power supply chip, the second end of the first capacitor is grounded, the first end of the second capacitor is connected with the second end of the second resistor, and the second end of the second capacitor is grounded.

[0015] In some embodiments, the discharge output circuit comprises a third resistor and a light MOS solid-state relay.

[0016] The first end of the third resistor is connected with the second end of the second resistor, the second end of the third resistor is connected with the third end of the light MOS solid-state relay, the first end of the light MOS solid-state relay is connected with the enable circuit, and the second end and the fourth end of the light MOS solid-state relay U2 are grounded.

[0017] In some embodiments, the enable circuit comprises a bias enable unit and a discharge enable unit, the bias enable unit is connected with the control circuit and the bias output circuit, and the discharge enable unit is connected with the control circuit and the discharge output circuit.

[0018] In some embodiments, the bias enable unit comprises a fourth resistor, a fifth resistor, a third capacitor and a first triode.

[0019] The first end of the first triode is connected with the second end of the first resistor, the second end of the first triode is grounded, the first end of the fourth resistor is connected with the control circuit, and the second end of the fourth resistor is connected with the third end of the first triode.

[0020] The first end of the fifth resistor is connected with the first end of the fourth resistor, the second end of the fifth resistor is grounded, the first end of the third capacitor is connected with the second end of the fourth resistor, and the second end of the third capacitor is grounded.

[0021] In some embodiments, the discharge enable unit comprises a sixth resistor, a seventh resistor, a fourth capacitor and a second triode.

[0022] The first end of the sixth resistor is connected with a pull-up voltage, the second end of the sixth resistor is connected with the first end of the second triode and the first end of the light MOS solid-state relay, and the second end of the second triode is grounded.

[0023] The first end of the seventh resistor is connected with the control circuit, the second end of the seventh resistor is connected with the third end of the second triode, the first end of the fourth capacitor is connected with the second end of the seventh resistor, and the second end of the fourth capacitor is grounded.

[0024] In some embodiments, the first transistor and the second transistor are NPN type transistors.

[0025] In some embodiments, the control circuit is a programmable logic chip FPGA.

[0026] In some embodiments, the laser detection sensor is an avalanche photodiode.

[0027] In a second aspect, a laser detection device is provided, comprising the bias voltage processing circuit as described above.

[0028] The beneficial effects brought by the technical solutions of the present application include:

[0029] The bias voltage processing circuit and the laser detection device provided by the embodiments of the present application are characterized in that: the bias voltage processing circuit is provided with a bias output circuit, a discharge output circuit, an enable circuit and a control circuit, on the basis of the bias output circuit, the discharge output circuit is arranged, the discharge output circuit can quickly discharge the output end residual voltage of the bias output circuit when the bias output circuit stops outputting the bias voltage, and the falling speed of the output end residual voltage is greatly improved; on the other hand, through the two enable level signals of the enable circuit, the bias output circuit and the discharge output circuit are simultaneously controlled, the discharge output and the bias output are ensured to be in an interlocking state, that is, only one state can be enabled at the same time of the bias output and the discharge output, and the continuous high-voltage discharge caused by the simultaneous enable of the bias output and the discharge output is avoided, so that the circuit power consumption is not too large and damage is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0031] Figure 1 A principle block diagram of the bias voltage processing circuit provided by the embodiments of the present application is provided.

[0032] Figure 2 A circuit diagram of the bias voltage processing circuit provided by the embodiments of the present application is provided.

[0033] Figure 3 The output end voltage transient response simulation result of the existing bias voltage processing circuit when stopping outputting the bias voltage.

[0034] Figure 4The bias voltage processing circuit stops outputting the bias voltage, and the output end voltage transient response simulation result is provided. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0036] The bias voltage processing circuit provided in the embodiments of the present application can solve the technical problem that the residual voltage of the output end decreases slowly after the existing bias voltage processing circuit stops outputting the bias voltage.

[0037] Referring to Figure 1 The bias voltage processing circuit provided in the embodiments of the present application includes a bias voltage output circuit, a discharge output circuit, an enabling circuit and a control circuit.

[0038] The bias voltage output circuit is arranged between a power supply and a laser detection sensor, the discharge output circuit is connected with the output end of the bias voltage output circuit and the ground, and the enabling circuit is connected with the bias voltage output circuit and the discharge output circuit.

[0039] The control circuit is connected with the enabling circuit, and is configured to:

[0040] When the control circuit outputs a first control signal (high level) to the enabling circuit, the enabling circuit outputs two enabling level signals to make the bias voltage output circuit conductive and the discharge output circuit disconnected, that is, the bias voltage output circuit normally outputs the bias voltage to the laser detection sensor.

[0041] When the control circuit outputs a second control signal (low level) to the enabling circuit, the enabling circuit outputs two enabling level signals to make the bias voltage output circuit disconnected and the discharge output circuit conductive, that is, the bias voltage output circuit stops outputting the bias voltage to the laser detection sensor, and the residual voltage of the output end of the bias voltage output circuit is rapidly discharged through the discharge output circuit.

[0042] Figure 3 For the output end voltage transient response simulation result of the existing bias voltage processing circuit stopping outputting the bias voltage, the bias voltage of the output end needs about 4s to decrease from -500V to 0V, Figure 4The output end voltage transient response simulation result of the bias voltage processing circuit stopping outputting the bias voltage is that the bias voltage of the output end decreases from -500V to 0V in about 4ms, and the decrease speed is greatly improved.

[0043] The bias voltage processing circuit in the embodiment of the utility model, it is provided with bias output circuit, discharge output circuit, enable circuit and control circuit, one aspect sets up discharge output circuit on the basis of bias output circuit, discharge output circuit can be in bias output circuit stops outputting bias voltage, the output end residual voltage of bias output circuit is discharged quickly, the decrease speed of output end residual voltage gets very big promotion, the other side, through the two-way enable level signal of enable circuit, realize control to bias output circuit and discharge output circuit simultaneously, guarantee discharge output and bias output is interlocked state, namely bias output and discharge output can only enable one state at the same time, avoid bias output and discharge output enable simultaneously and cause continuous high voltage discharge and lead to circuit power consumption too big damage.

[0044] As optional implementation, in one embodiment of the utility model, as shown in Figure 2 The bias output circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a MOS tube M1 and a power supply chip U1. Optionally, the MOS tube M1 is a PMOS tube.

[0045] The first end of the first resistor R1 is connected with the first end of the MOS tube M1 and a power supply VCC, the second end of the first resistor R1 is connected with the third end of the MOS tube M1 and the enable circuit, the second end of the MOS tube M1 is connected with the input end (#1 pin) of the power supply chip U1, the output end (#4 pin) of the power supply chip U1 is connected with the first end of the second resistor R2, and the second end of the second resistor R2 is used as the output end of the bias output circuit and is connected with a laser detection sensor. The first end of the first capacitor C1 is connected with the input end (#1 pin) of the power supply chip U1, the second end of the first capacitor C1 is grounded, the first end of the second capacitor C2 is connected with the second end of the second resistor R2, and the second end of the second capacitor C2 is grounded. The first capacitor C1 is an input filter capacitor of the power supply chip U1. The first resistor R1 is a current-limiting resistor, the second resistor R2 and the second capacitor C2 constitute a low-pass filter circuit to suppress bias voltage output ripple.

[0046] When the control circuit outputs a first control signal to the enable circuit, the enable circuit outputs an enable level signal to make the MOS tube M1 conduct, and the bias output circuit normally outputs the bias voltage to the laser detection sensor.

[0047] When the control circuit outputs the second control signal to the enable circuit, the enable circuit outputs an enable level signal to make the MOS transistor M1 disconnected, and the bias voltage output circuit stops outputting the bias voltage to the laser detection sensor.

[0048] As an optional embodiment, in one utility model embodiment, referring to Figure 2 As shown in the figure, the discharge output circuit comprises a third resistor R3 and a light MOS solid-state relay U2.

[0049] The first end of the third resistor R3 is connected with the second end of the second resistor R2, the second end of the third resistor R3 is connected with the third end (#3 pin) of the light MOS solid-state relay U2, the first end (#1 pin) of the light MOS solid-state relay U2 is connected with the enable circuit, and the second end (#2 pin) and the fourth end (#4 pin) of the light MOS solid-state relay U2 are grounded. The third resistor R3 is a current-limiting resistor for protecting the discharge output circuit.

[0050] When the control circuit outputs the first control signal to the enable circuit, the enable circuit outputs an enable level signal to the first end (#1 pin) of the light MOS solid-state relay U2, and the third end (#3 pin) and the fourth end (#4 pin) of the light MOS solid-state relay U2 are disconnected.

[0051] When the control circuit outputs the second control signal to the enable circuit, the enable circuit outputs an enable level signal to the first end (#1 pin) of the light MOS solid-state relay U2, and the third end (#3 pin) and the fourth end (#4 pin) of the light MOS solid-state relay U2 are connected to discharge the residual voltage at the output end of the bias voltage output circuit.

[0052] The light MOS solid-state relay is internally integrated with a bidirectional high-voltage MOS transistor, can realize controlled conduction of positive and negative voltages, has a switching time of not more than 2 ms, reduces the occupied space of the circuit, and reduces the material cost. The control loop and the conduction loop of the light MOS solid-state relay are realized by photoelectric coupling to achieve physical insulation of the loops, which can greatly reduce the crosstalk risk of high-voltage discharge to low-voltage circuits.

[0053] As an optional embodiment, in one utility model embodiment, referring to Figure 2 As shown in the figure, the enable circuit comprises a bias enable unit and a discharge enable unit, the bias enable unit is connected with the control circuit and the bias voltage output circuit, and the discharge enable unit is connected with the control circuit and the discharge output circuit.

[0054] Further, the bias voltage enabling unit comprises a fourth resistor R4, a fifth resistor R5, a third capacitor C3 and a first triode Q1, a first end of the first triode Q1 is connected with a second end of the first resistor R1, a second end of the first triode Q1 is grounded, a first end of the fourth resistor R4 is connected with the control circuit, a second end of the fourth resistor R4 is connected with a third end of the first triode Q1, a first end of the fifth resistor R5 is connected with the first end of the fourth resistor R4, a second end of the fifth resistor R5 is grounded, a first end of the third capacitor C3 is connected with the second end of the fourth resistor R4, and a second end of the third capacitor C3 is grounded, the fifth resistor R5 is a pull-down resistor, used for stabilizing the output state of the control signal, the fourth resistor R4 and the third capacitor C3 form a low-pass filter circuit, preventing the control signal from being triggered by mistake due to interference, and the first triode Q1 is used for level conversion.

[0055] The discharge enabling unit comprises a sixth resistor R6, a seventh resistor R7, a fourth capacitor C4 and a second triode Q2, a first end of the sixth resistor R6 is connected with a pull-up voltage VDD, a second end of the sixth resistor R6 is connected with a first end of the second triode Q2 and a first end of the optical MOS solid-state relay U2, a second end of the second triode Q2 is grounded, a first end of the seventh resistor R7 is connected with the control circuit, a second end of the seventh resistor R7 is connected with a third end of the second triode Q2, a first end of the fourth capacitor C4 is connected with the second end of the seventh resistor R7, and a second end of the fourth capacitor C4 is grounded, the seventh resistor R7 and the fourth capacitor C4 form a low-pass filter circuit, preventing the control signal from being triggered by mistake due to interference, the second triode Q2 is used for level conversion, and the sixth resistor R6 is a current-limiting resistor.

[0056] As an optional implementation, in one utility model embodiment, the control circuit adopts a programmable logic chip FPGA, and the programmable logic chip FPGA can output a first control signal (low level) or a second control signal (high level) in real time and accurately according to requirements.

[0057] As an optional implementation, in one utility model embodiment, the laser detection sensor is an avalanche photodiode. The avalanche photodiode can detect extremely weak light signals and convert them into corresponding electric signals, and has the characteristics of high sensitivity, high gain and fast response.

[0058] The working principle of the bias voltage processing circuit in the utility model embodiment is as follows:

[0059] When the control circuit outputs a first control signal (high level) to the enable circuit, the enable circuit outputs an enable level signal (low level) to the third end (gate) of the MOS tube M1, so that the MOS tube M1 is turned on, and the bias voltage output circuit normally outputs the bias voltage to the laser detection sensor. At the same time, the enable circuit outputs an enable level signal (low level) to the first end (#1 pin) of the optical MOS solid-state relay U2, so that the third end (#3 pin) of the optical MOS solid-state relay U2 is disconnected from the fourth end (#4 pin).

[0060] When the control circuit outputs a second control signal (low level) to the enable circuit, the enable circuit outputs an enable level signal (high level) to the third end (gate) of the MOS tube M1, so that the MOS tube M1 is turned off, and the bias voltage output circuit stops outputting the bias voltage to the laser detection sensor. At the same time, the enable circuit outputs an enable level signal (high level) to the first end (#1 pin) of the optical MOS solid-state relay U2, so that the third end (#3 pin) of the optical MOS solid-state relay U2 is connected to the fourth end (#4 pin), and the residual voltage at the output end of the bias voltage output circuit is quickly discharged.

[0061] The utility model embodiment further provides a laser detection device comprising the bias voltage processing circuit.

[0062] In the description of the utility model, it is necessary to explain that the position or position relation indicated by the term "upper", "lower" and the like is the position or position relation shown in the drawing, and is only for the convenience of describing the utility model and simplifying the description, and is not indicative or suggestive of the device or element indicated must have a specific position, a specific position structure and operation, therefore, it cannot be understood as the limitation of the utility model. Unless otherwise specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, it can be fixed connection, can also be detachable connection, or integrally connected, can be mechanical connection, can also be electrical connection, can be directly connected, can also be indirectly connected through an intermediate medium, and can be the communication between two elements. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.

[0063] It should be noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0064] The above description is merely that of the specific embodiments of the present application, and enables those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bias voltage processing circuit, characterized by, The bias voltage processing circuit comprises: a bias voltage output circuit arranged between a power supply and a laser detection sensor; a discharge output circuit connected to an output terminal of the bias voltage output circuit and a ground; an enabling circuit connected to the bias voltage output circuit and the discharge output circuit; a control circuit connected to the enabling circuit, and configured to: output a first / second control signal to the enabling circuit, so that the enabling circuit outputs two enabling level signals to turn on / off the bias voltage output circuit and turn off / on the discharge output circuit.

2. The bias voltage processing circuit according to claim 1, wherein: the bias voltage output circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor, a MOS transistor and a power supply chip; a first terminal of the first resistor is connected to a first terminal of the MOS transistor and a power supply, a second terminal of the first resistor is connected to a third terminal of the MOS transistor and the enabling circuit, a second terminal of the MOS transistor is connected to an input terminal of the power supply chip; an output terminal of the power supply chip is connected to a first terminal of the second resistor, and a second terminal of the second resistor is used as an output terminal of the bias voltage output circuit and is connected to the laser detection sensor; a first terminal of the first capacitor is connected to the input terminal of the power supply chip, a second terminal of the first capacitor is grounded, a first terminal of the second capacitor is connected to the second terminal of the second resistor, and a second terminal of the second capacitor is grounded.

3. The bias voltage processing circuit according to claim 2, wherein: the discharge output circuit comprises a third resistor and a light MOS solid-state relay; a first terminal of the third resistor is connected to the second terminal of the second resistor, a second terminal of the third resistor is connected to a third terminal of the light MOS solid-state relay, a first terminal of the light MOS solid-state relay is connected to the enabling circuit, and a second terminal and a fourth terminal of the light MOS solid-state relay U2 are grounded.

4. The bias voltage processing circuit according to claim 3, wherein: the enabling circuit comprises a bias voltage enabling unit and a discharge enabling unit, the bias voltage enabling unit is connected to the control circuit and the bias voltage output circuit, and the discharge enabling unit is connected to the control circuit and the discharge output circuit.

5. The bias voltage processing circuit according to claim 4, wherein: the bias voltage enabling unit comprises a fourth resistor, a fifth resistor, a third capacitor and a first triode; a first terminal of the first triode is connected to the second terminal of the first resistor, a second terminal of the first triode is grounded, a first terminal of the fourth resistor is connected to the control circuit, and a second terminal of the fourth resistor is connected to a third terminal of the first triode; a first terminal of the fifth resistor is connected to the first terminal of the fourth resistor, a second terminal of the fifth resistor is grounded, a first terminal of the third capacitor is connected to the second terminal of the fourth resistor, and a second terminal of the third capacitor is grounded.

6. The bias voltage processing circuit according to claim 5, wherein: the discharge enabling unit comprises a sixth resistor, a seventh resistor, a fourth capacitor and a second triode; A first end of the sixth resistor is connected to a pull-up voltage, a second end of the sixth resistor is connected to a first end of the second triode and a first end of the optical MOS solid-state relay, and a second end of the second triode is grounded. A first end of the seventh resistor is connected to the control circuit, a second end of the seventh resistor is connected to a third end of the second triode, a first end of the fourth capacitor is connected to the second end of the seventh resistor, and a second end of the fourth capacitor is grounded.

7. The bias voltage processing circuit according to claim 6, characterized by: The first triode and the second triode are NPN type triodes.

8. The bias voltage processing circuit of claim 1, wherein: The control circuit adopts a programmable logic chip FPGA.

9. The bias voltage processing circuit of claim 1, wherein: The laser detection sensor is an avalanche photodiode.

10. A laser detection apparatus, characterized by, The bias voltage processing circuit of any one of claims 1-9.

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