Current protection circuit and electric signal buffer system

Abstract

The utility model provides a current protection circuit. The current protection circuit comprises a switching element, a first capacitor, a first resistor, a second resistor, a third resistor and a second capacitor, one end of the first capacitor is connected with the output end of the switch piece, the first resistor is connected with the second resistor in series, one end of the first resistor is connected with the control end of the switch piece, one end of the second resistor is grounded, and the common end of the first resistor and the second resistor is connected with the other end of the first capacitor. One end of the second capacitor is connected with the other end of the third resistor, and the other end of the second capacitor is grounded. The utility model further provides an electric signal buffering system, and the current protection circuit and the electric signal buffering system can remarkably relieve the power-on peak current impact when the industrial instrument is mounted without power failure through the arrangement of the switch piece, the first capacitor, the first resistor and the second resistor.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of industrial automation, and particularly relates to a current protection circuit and an electric signal buffering system. BACKGROUND

[0002] The 4~20mA signal is a current loop signal widely used in industrial automation and process control, and is used for communication between sensors, transducers and controllers, and has the advantages of strong anti-interference ability, long transmission distance and easy realization of accurate signal transmission.

[0003] However, there are a large number of electromagnetic interferences in the industrial environment, which can be coupled into the 4~20mA signal through the power line or the signal line, or a sharp current is introduced by the switching device during power-on. In the prior art, an RC filter circuit or an LC filter circuit is usually used to reduce the current sharp peak amplitude, but the effect of the existing scheme is not obvious, and the stability is not high. CONTENT OF THE INVENTION

[0004] To solve the above technical problems, the application provides a current protection circuit and an electric signal buffering system, which can significantly reduce the sharp peak amplitude of the power-on current, and is stable and reliable, and ensures the stability of the subsequent mounting.

[0005] To achieve the above effects, the application adopts the following technical scheme:

[0006] The application provides a current protection circuit, which comprises: a switching device, a first capacitor, a first resistor and a second resistor; the input end of the switching device receives a voltage signal; one end of the first capacitor is connected with the input end of the switching device; the first resistor and the second resistor are connected in series, one end of the first resistor is connected with the control end of the switching device, one end of the second resistor is grounded, and the common end of the first resistor and the second resistor is connected with the other end of the first capacitor.

[0007] Preferably, the current protection circuit further comprises a third resistor; one end of the third resistor is connected with the output end of the switching device, and the other end of the third resistor serves as the circuit output end of the current protection circuit.

[0008] Preferably, the current protection circuit further comprises a second capacitor; one end of the second capacitor is connected with the other end of the third resistor, and the other end of the second capacitor is grounded.

[0009] Preferably, the first resistor and the second resistor have the same structure.

[0010] Preferably, the switching device is a PNP type triode, the base of the PNP type triode serves as the control end of the switching device and is connected with one end of the first resistor, and the emitter of the PNP type triode serves as the input end of the switching device and receives the voltage signal.

[0011] Preferably, the switch is a P-type MOS transistor, a gate of the PMOS transistor is connected to a control terminal of the switch and an end of the first resistor, and a source of the P-type MOS transistor is connected to an input terminal of the switch to receive the voltage signal.

[0012] The application provides an electric signal buffering system comprising the current protection circuit.

[0013] Preferably, the electric signal buffering system further comprises a voltage stabilizer, a power input terminal of the voltage stabilizer is connected to an output terminal of the current protection circuit.

[0014] Preferably, the voltage stabilizer is a low dropout linear voltage stabilizer, the low dropout linear voltage stabilizer comprises a reference voltage source, an error amplifier, a regulating circuit, a first compensation circuit and a second compensation circuit; the reference voltage source is configured to provide a reference voltage; the error amplifier is coupled to the reference voltage source, configured to receive a feedback voltage and the reference voltage, compare the feedback voltage and the reference voltage, and output a control voltage according to a comparison result of the feedback voltage and the reference voltage; the regulating circuit is coupled to the error amplifier, configured to receive the control voltage, and output a regulating current under control of the control voltage, the regulating current flows through a load to form a voltage on the load, the feedback voltage is related to the voltage on the load; the first compensation circuit is coupled to the regulating circuit, configured to adjust a main pole and a secondary main pole of the low dropout linear voltage stabilizer to adjust a phase margin; the second compensation circuit is coupled to the first compensation circuit, configured to adjust the main pole of the low dropout linear voltage stabilizer to be smaller and the secondary main pole of the low dropout linear voltage stabilizer to be larger on the basis that the first compensation circuit has adjusted the main pole and the secondary main pole of the low dropout linear voltage stabilizer, so as to adjust the phase margin and adjust a gain-bandwidth product of the low dropout linear voltage stabilizer.

[0015] Preferably, the electric signal buffering system further comprises a voltage stabilizer, a power input terminal of the voltage stabilizer is connected to an output terminal of the current protection circuit.

[0016] The current protection circuit and the electric signal buffering system of the application comprise a switch, a first capacitor, a first resistor, and a second resistor; the input end of the switch receives a voltage signal; one end of the first capacitor is connected with the input end of the switch; the first resistor and the second resistor are connected in series, one end of the first resistor is connected with the control end of the switch, one end of the second resistor is grounded, and the common end of the first resistor and the second resistor is connected with the other end of the first capacitor. Therefore, the RC delay circuit is used to delay the switch-on of the switch, and the RC delay circuit is used for buffering, so that the power-on peak current of the 4-20mA communication level can be significantly reduced, thereby the peak current impact of the industrial instrument during the power-on of the continuous power hanging can be significantly reduced.

[0017] The above description is only a summary of the technical solutions of the application, in order to more clearly understand the technical means of the application, and to be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the application more obvious and easy to understand, the following describes the specific embodiments, and the detailed description is as follows in cooperation with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The structure and connection relationship of the current protection circuit of an embodiment of the application are shown in the schematic diagram.

[0019] Figure 2 The structure of the electric signal buffering system of an embodiment of the application is shown in the schematic diagram.

[0020] Figure 3 The module of the voltage stabilizer of an embodiment of the application is shown in the schematic diagram.

[0021] Figure 4 The circuit structure of the voltage stabilizer of an embodiment of the application is shown in the schematic diagram.

[0022] Figure 5 The circuit structure of the error amplifier of an embodiment of the application is shown in the schematic diagram.

[0023] Figure 6 The circuit structure of the voltage stabilizer of another embodiment of the application is shown in the schematic diagram.

[0024] Wherein, Q1 is a switch, C1 is a first capacitor, R1 is a first resistor, R2 is a second resistor, R3 is a third resistor, C2 is a second capacitor, 10 is a current protection circuit, and 20 is a voltage stabilizer. DETAILED DESCRIPTION

[0025] In order to facilitate understanding of the application, the application will be described more fully below with reference to the related drawings. The specific embodiments of the application are shown in the drawings, and the detailed description of the application is as follows in combination with the following drawings and examples.

[0026] Figure 1The structure and connection relationship of the current protection circuit are shown in the schematic diagram of an embodiment of the present application. Figure 1

[0027] The current protection circuit comprises a switch Q1, a first capacitor C1, a first resistor R1 and a second resistor R2.

[0028] The input end of the switch Q1 receives a voltage signal as the circuit input end In. The voltage signal is preferably a 4-20 mA communication level of 3.3 V or 5 V.

[0029] One end of the first capacitor C1 is connected to the input end of the switch Q1. The first resistor R1 and the second resistor R2 are connected in series, one end of the first resistor R1 is connected to the control end of the switch Q1, one end of the second resistor R2 is grounded, and the common end of the first resistor R1 and the second resistor R2 is connected to the other end of the first capacitor C1.

[0030] When the current protection circuit is powered on, the voltage signal is received through the circuit input end In, and the RC delay circuit composed of the first capacitor C1 and the second resistor R2 buffers the power-on spike of the voltage signal. The voltage at the control end of the switch Q1 continuously rises with the voltage across the first capacitor C1, and the switch Q1 is turned on only after the voltage reaches the turn-on threshold. At this time, the voltage signal can be output through the turned-on switch Q1. Therefore, the current protection circuit of the embodiment can significantly reduce the amplitude of the power-on current spike, is stable and reliable, and can ensure the stability of the subsequent mounting.

[0031] In an embodiment, the switch Q1 is a PNP type transistor, and the first resistor R1 can be a resistor internally provided in the PNP type transistor. The base of the PNP type transistor is connected to one end of the first resistor R1 as the control end of the switch Q1, and the emitter of the PNP type transistor receives the voltage signal as the input end of the switch Q1. In other embodiments, the switch Q1 can also be other transistors, for example, a P-type MOS tube. The gate of the PMOS tube is connected to one end of the first resistor R1 as the control end of the switch Q1, and the source of the P-type MOS tube receives the voltage signal as the input end of the switch Q1.

[0032] Specifically, taking the switch Q1 as a PNP type transistor as an example, the principle of the current protection circuit of the embodiment is explained as follows: when the current protection circuit input end In receives a power-on jump current, the RC delay circuit composed of the first capacitor C1 and the second resistor R2 makes the voltage across the first resistor R1 slowly rise. When the voltage across the first resistor reaches the turn-on voltage of the base of the control end of the switch Q1, the switch Q1 is turned on, and the third resistor R3 and the second capacitor C2 also form an RC delay circuit. After the switch Q1 is turned on, the current is further buffered.

[0033] ​In an embodiment, the current protection circuit further comprises a third resistor R3. One end of the third resistor R3 is connected to the output end of the switch Q1, and the other end of the third resistor R3 serves as the circuit output end of the current protection circuit, so as to further buffer the power-on spike through the third resistor R3.

[0034] In an embodiment, the current protection circuit further comprises a second capacitor C2. One end of the second capacitor C2 is connected to the other end of the third resistor R3, and the other end of the second capacitor C2 is grounded.

[0035] In an embodiment, the first resistor R1 and the second resistor R2 are preferably resistors of the same structure and specification, and the resistance value of the first resistor R1 is preferably 180k ohms, and the resistance value of the second resistor R2 is 180k ohms.

[0036] The specific implementation process of the current protection circuit is as follows:

[0037] The circuit input end In receives an external voltage signal, and the voltage signal is preferably a 3.3V or 5V electrical signal. When powered on, the circuit input end In receives a power-on spike. The first capacitor C1 and the second resistor R2 constitute an RC delay circuit to buffer the power-on spike. After the voltage at the control end of the switch Q1 reaches the conduction threshold, the switch Q1 is turned on, and the voltage signal enters the RC delay circuit composed of the third resistor R3 and the second capacitor C2 through the turned-on switch Q1, so as to further buffer the power-on spike. The buffered electrical signal is then output by the circuit output end Out.

[0038] The application also provides a kind of electrical signal buffering system, as shown in Figure 2 , which comprises the current protection circuit 10 in the above embodiment.

[0039] In an embodiment, the electrical signal buffering system further comprises a voltage stabilizer 20, and the power input end of the voltage stabilizer 20 is connected to the output end of the current protection circuit. In an embodiment, the enable end of the voltage stabilizer 20 is connected to the output end Out of the current protection circuit.

[0040] In an embodiment, the voltage stabilizer 20 is preferably a low dropout linear voltage stabilizer. As shown in Figure 3 , the low dropout linear voltage stabilizer comprises a reference voltage source 201, an error amplifier 202, a regulation circuit 203, a first compensation circuit 204, a second compensation circuit 205, and a load 206.

[0041] The reference voltage source 201 is configured to provide a reference voltage. The error amplifier 202 is coupled to the reference voltage source 201 and configured to receive the feedback voltage and the reference voltage, compare the feedback voltage and the reference voltage, and output a control voltage according to a comparison result of the feedback voltage and the reference voltage. The regulation circuit 203 is coupled to the error amplifier 202 and configured to receive the control voltage and output a regulation current under control of the control voltage. The load 206 is coupled to the regulation circuit 203 and the error amplifier 202, and the regulation current flows through the load 206 to form a voltage on the load 206. The first compensation circuit 204 is coupled to the regulation circuit 203 and configured to adjust a dominant pole and a sub-dominant pole of the low-dropout linear regulator to adjust a phase margin. The second compensation circuit 205 is coupled to the first compensation circuit 204 and configured to further adjust the dominant pole and the sub-dominant pole of the low-dropout linear regulator to adjust the phase margin and adjust a gain-bandwidth product of the low-dropout linear regulator on the basis of the first compensation circuit 204 having adjusted the dominant pole and the sub-dominant pole of the low-dropout linear regulator. The feedback voltage is related to the voltage on the load, and in general, the feedback voltage is linearly related to the voltage on the load. For example, the feedback voltage is the voltage on the load, or the feedback voltage is in a predetermined proportional relationship with the voltage on the load, and the like.

[0042] The negative input of the error amplifier 202 is connected to the reference voltage source 201 and configured to receive the reference voltage from the reference voltage source. The positive input of the error amplifier 202 is coupled to the load and configured to receive the feedback voltage. Figure 4 As shown, the first compensation circuit 204 can be a Miller capacitor-zeroing resistor compensation circuit, that is, the first compensation circuit 204 can include a zeroing resistor 2041 and a Miller compensation capacitor 2042, the Miller compensation capacitor 2042 is connected to the drain of the transistor 203 and to one end of the zeroing resistor 2041; the other end of the zeroing resistor 2041 is connected to the second compensation circuit 205. The regulation circuit 203 can be a power MOS device such as a transistor. The second compensation circuit 205 can include a compensation resistor 2051, one end of the compensation resistor 2051 is connected to the output of the error amplifier 202, and the other end is connected to one end of the zeroing resistor 2041 and the gate of the regulation circuit 203. The compensation resistor 2051 can be a silicon diffusion resistor, a MOS device resistor, or a metal trace resistor.

[0043] Figure 5 The circuit structure of the error amplifier of an embodiment of the present application is shown in the figure. The error amplifier 202 can be composed of a bias current source 2021, an input pair transistor 2022, and an output current mirror 2023, wherein the input pair transistor 2022 is coupled between the bias current source 2021 and the output current mirror 2023.

[0044] Figure 6The circuit structure schematic diagram of low dropout linear regulator of another embodiment of the present application is shown in the figure. Figure 6 As shown in the figure, in order to adjust the output voltage of the low dropout linear regulator, the feedback circuit 207 can also generate a feedback voltage according to the voltage on the load in another embodiment of the present application. Figure 6 As shown in the figure, the feedback circuit 207 can be composed of a first voltage dividing resistor 2071 and a second voltage dividing resistor 2072, one end of the first voltage dividing resistor 2071 is connected with the positive input of the error amplifier 202, the other end is connected with the power supply ground, one end of the second voltage dividing resistor 2072 is connected with the positive input of the error amplifier 202, the other end is connected with the drain of the transistor 203 and the load. Thus, by adjusting the resistance of the first voltage dividing resistor and the resistance of the second voltage dividing resistor 2072, the size of the feedback voltage can be changed, thereby changing the size of the voltage on the load of the low dropout linear regulator.

[0045] In an embodiment, the electric signal buffering system further comprises a voltage reduction circuit, and a power input end of the voltage reduction circuit is connected with an output end of the current protection circuit.

[0046] The present application provides a current protection circuit, which can be used to solve the influence of the power-on spike on the line load at the 4~20mA communication level, and can effectively reduce the amplitude of the power-on spike. The electric signal buffering system provided by the present application combines the current protection circuit and the voltage stabilizer / voltage reduction circuit, further improves the function of the electric signal buffering, provides a safe and reliable electric signal buffering scheme, and significantly reduces the power-on spike current impact when the industrial instrument is continuously powered.

[0047] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the technical solution of the present application, and any simple modification, equivalent change and modification of the above embodiment according to the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A current protection circuit, characterized by, The current protection circuit comprises: a switch, a first capacitor, a first resistor, and a second resistor; an input end of the switch receives a voltage signal; one end of the first capacitor is connected to the input end of the switch; the first resistor and the second resistor are connected in series, one end of the first resistor is connected to a control end of the switch, one end of the second resistor is grounded, and the other end of the first resistor and the second resistor is connected to the other end of the first capacitor.

2. A current protection circuit as claimed in claim 1, characterized in that: The current protection circuit further comprises a third resistor; one end of the third resistor is connected to an output end of the switch, and the other end of the third resistor serves as a circuit output end of the current protection circuit.

3. A current protection circuit as claimed in claim 2, characterized in that: The current protection circuit further comprises a second capacitor; one end of the second capacitor is connected to the other end of the third resistor, and the other end of the second capacitor is grounded.

4. A current protection circuit as claimed in claim 1, characterized in that: The first resistor and the second resistor have the same structure.

5. A current protection circuit as claimed in claim 1, characterized in that: The switch is a PNP triode, a base of the PNP triode serves as the control end of the switch and is connected to one end of the first resistor, and an emitter of the PNP triode serves as the input end of the switch and receives the voltage signal.

6. The current protection circuit of claim 1, wherein, The switch is a P-type MOS tube, a gate of the P-type MOS tube serves as the control end of the switch and is connected to one end of the first resistor, and a source of the P-type MOS tube serves as the input end of the switch and receives the voltage signal.

7. An electrical signal buffering system characterized by, The current protection circuit comprises any one of claims 1-6.

8. The electrical signal buffering system of claim 7, wherein, The current protection circuit further comprises: a voltage stabilizer, a power input end of the voltage stabilizer is connected to an output end of the current protection circuit.

9. An electrical signal buffering system as claimed in claim 8, characterized in that The voltage stabilizer is a low-dropout linear voltage stabilizer, and the low-dropout linear voltage stabilizer comprises a reference voltage source, an error amplifier, a regulating circuit, a first compensation circuit, and a second compensation circuit. The reference voltage source is configured to provide a reference voltage. The error amplifier is coupled to the reference voltage source, configured to receive a feedback voltage and the reference voltage, compare the feedback voltage and the reference voltage, and output a control voltage according to a comparison result of the feedback voltage and the reference voltage. The regulating circuit is coupled to the error amplifier, configured to receive the control voltage, and output a regulating current under control of the control voltage, the regulating current flows through a load to form a voltage on the load, and the feedback voltage is related to the voltage on the load. The first compensation circuit is coupled to the regulating circuit, configured to adjust a main pole and a sub-main pole of the low-dropout linear voltage stabilizer to adjust a phase margin. The second compensation circuit is coupled to the first compensation circuit, configured to, on the basis that the first compensation circuit has adjusted the main pole and the sub-main pole of the low-dropout linear voltage stabilizer, adjust the main pole of the low-dropout linear voltage stabilizer to be smaller, and further adjust the sub-main pole to be larger, so as to adjust the phase margin and adjust a gain-bandwidth product of the low-dropout linear voltage stabilizer.

10. An electrical signal buffering system as claimed in claim 7, characterized in that The current protection circuit further comprises: a step-down circuit, a power input end of the step-down circuit is connected to an output end of the current protection circuit.

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