PCB (printed circuit board) structure of network socket for reducing crosstalk caused by twisting of Ethernet twisted pair

Abstract

The utility model provides a PCB structure of a network socket capable of reducing crosstalk caused by open twisting of Ethernet twisted pairs, which comprises a first PCB layer, a second PCB layer, a third PCB layer and a fourth PCB layer, and each layer comprises two groups of signal transmission ends which are respectively provided with eight signal transmission ends and are communicated through a transmission line; wherein the first PCB layer comprises a first filtering area, the second PCB layer comprises a second filtering area, the third PCB layer comprises a third filtering area, and the fourth PCB layer comprises a fourth filtering area; each filtering area forms a plurality of interdigital capacitors through transmission line structures of two signal transmission ends so as to reduce crosstalk. The PCB structure of the network socket capable of reducing crosstalk caused by open twisting of the Ethernet twisted pair provided by the utility model has the remarkable beneficial effects that the signal transmission quality is improved, the cost is reduced, and the design flexibility and the product competitiveness are also improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of network sockets, in particular to a PCB structure of a network socket for reducing crosstalk caused by opening of Ethernet twisted pair wires. BACKGROUND

[0002] As shown in the Ethernet communication system, twisted pair wires are widely used as a transmission medium, and their performance directly affects the quality and stability of data transmission. Figure 1 However, in practical applications, the twisted pair wire C1 of the crystal head C4 often needs to be opened C3 when connecting the contact terminal C2 of the crystal head, in order to connect with the contact terminal of the crystal head C4. This opening process often destroys the balanced structure of the non-twisted pair wire area, that is, in the non-twisted pair wire area (the area between the twisted pair wires at one end of the PCB board C5 of the socket and the twisted pair wires at the other end), near-end crosstalk is caused, leading to unbalanced signal transmission and causing near-end crosstalk (NEXT) and other electrical characteristic problems.

[0003] Near-end crosstalk refers to the interference of signals on one pair of wires to the adjacent pair of wires in the same cable bundle. In Ethernet communication, near-end crosstalk can seriously affect the quality of signal transmission, reduce data transmission rate, and even cause communication failure. Therefore, how to effectively reduce the crosstalk problem caused by opening of twisted pair wires has become an important issue in the design of Ethernet sockets.

[0004] The traditional solution is to add physical capacitors inside the socket for filtering to suppress the generation of crosstalk signals. However, this method not only increases the cost of the socket, but also limits the flexibility of the design. In addition, the introduction of physical capacitors may also bring additional parasitic inductance and resistance, which adversely affect signal transmission.

[0005] In order to overcome the shortcomings of the traditional method, the present application provides a PCB structure of a network socket for reducing crosstalk caused by opening of Ethernet twisted pair wires. This structure cleverly uses PCB traces to construct interdigital capacitors, achieving effective filtering of crosstalk between differential pairs. Interdigital capacitors, as a special capacitor structure, have electrodes composed of interlaced finger lines, which can provide a larger capacitance value in a smaller space. In this application, by reasonably designing the layout and shape of the PCB traces, the transmission lines of the two signal transmission ends can form multiple interdigital capacitors, thereby achieving filtering and balancing of crosstalk signals. CONTENT OF THE INVENTION

[0006] The purpose of the present application is to provide a PCB structure of a network socket for reducing crosstalk caused by opening of Ethernet twisted pair wires, which cleverly uses PCB traces to construct interdigital capacitors, achieving effective filtering of crosstalk between differential pairs.

[0007] To achieve the above objectives, this application provides the following technical solution:

[0008] A PCB structure for a network socket that reduces crosstalk caused by untwisted Ethernet twisted pairs includes a first PCB layer, a second PCB layer, a third PCB layer, and a fourth PCB layer. Each layer contains two groups of eight signal transmission terminals connected by transmission lines. The first PCB layer includes a first filtering area, the second PCB layer includes a second filtering area, the third PCB layer includes a third filtering area, and the fourth PCB layer includes a fourth filtering area. Each filtering area forms multiple interdigitated capacitors through the transmission lines of the two signal transmission terminals to reduce crosstalk.

[0009] In one embodiment, the first filtering region includes a first interdigitated capacitor, a second interdigitated capacitor, a third interdigitated capacitor, a fourth interdigitated capacitor, and a fifth interdigitated capacitor. The first interdigitated capacitor is constructed from the transmission line between the first signal transmission terminal and the third signal transmission terminal. The second interdigitated capacitor is constructed from the transmission line between the third signal transmission terminal and the fifth signal transmission terminal. The third interdigitated capacitor is constructed from the transmission line between the fifth signal transmission terminal and the sixth signal transmission terminal. The fourth interdigitated capacitor is constructed from the transmission line between the sixth signal transmission terminal and the seventh signal transmission terminal. The fifth interdigitated capacitor is constructed from the transmission line between the sixth signal transmission terminal and the eighth signal transmission terminal.

[0010] In one embodiment, the first interdigital capacitor is formed by the transmission lines of the first signal transmission terminal and the third signal transmission terminal wrapping around each other in a U-shape.

[0011] In one embodiment, the third interdigitated capacitor is formed by the transmission lines of the fifth signal transmission terminal and the sixth signal transmission terminal wrapping around each other in a U-shape.

[0012] In one embodiment, the second interdigitated capacitor is provided in two groups, and each group is formed by bending and inserting the transmission lines of the third signal transmission end and the fifth signal transmission end into each other and arranging them alternately.

[0013] In one embodiment, the fourth interdigitated capacitor is provided in two groups, and each group is formed by bending and inserting the transmission lines of the sixth signal transmission end and the seventh signal transmission end into each other and arranging them alternately.

[0014] In one embodiment, the fifth interdigital capacitor is formed by bending and inserting the transmission lines of the sixth signal transmission terminal and the eighth signal transmission terminal into each other in an alternating arrangement.

[0015] In one embodiment, the second filtering region includes two sets of sixth interdigitated capacitors, which are formed by bending and inserting the transmission lines of the third signal transmission end and the fifth signal transmission end into each other and arranging them alternately.

[0016] In one embodiment, the third filtering region includes two sets of seventh interdigitated capacitors, which are formed by bending and inserting the transmission lines of the fourth signal transmission end and the seventh signal transmission end into each other and arranging them alternately.

[0017] In one embodiment, the fourth filtering region includes an eighth interdigitated capacitor, a ninth interdigitated capacitor, a tenth interdigitated capacitor, and an eleventh interdigitated capacitor. The eighth interdigitated capacitor is provided in two groups, and each group is formed by bending and interpenetrating the transmission lines of the fourth signal transmission end and the sixth signal transmission end, and arranging them alternately. The ninth interdigitated capacitor is formed by bending and interpenetrating the transmission lines of the sixth signal transmission end and the eighth signal transmission end, and arranging them alternately. The tenth interdigitated capacitor is formed by the transmission lines of the third signal transmission end and the fourth signal transmission end wrapping around each other in a U-shape. The eleventh interdigitated capacitor is formed by the transmission lines of the first signal transmission end and the third signal transmission end wrapping around each other in a U-shape.

[0018] The beneficial effects of this application are as follows:

[0019] (1) By setting up filtering areas on each PCB layer and constructing multiple interdigital capacitors, this application effectively reduces electrical characteristic problems such as near-end crosstalk (NEXT) caused by twisting of twisted pairs. As a highly efficient filtering component, interdigital capacitors can significantly improve the purity and stability of signal transmission without increasing additional cost and complexity, thereby ensuring high-quality Ethernet communication.

[0020] (2) Traditional methods typically require adding physical capacitors inside the network socket for filtering, which not only increases manufacturing costs but also limits design flexibility. In contrast, this application uses PCB traces to directly construct interdigital capacitors, eliminating the need for additional components and significantly reducing costs. Furthermore, since the construction of interdigital capacitors is entirely dependent on the PCB trace design, filtering performance can be adjusted and optimized more flexibly, improving design flexibility and manufacturability.

[0021] (3) The PCB structure design of this application is reasonable. Each filtering area forms an interdigital capacitor through carefully arranged transmission lines, which not only realizes the filtering function, but also optimizes the layout and space utilization of the PCB. This design makes the network socket more compact and lightweight, which is convenient for installation and use in limited space, and meets the needs of modern electronic devices for miniaturization and integration. Attached Figure Description

[0022] Figure 1Structure diagram of network socket provided by an embodiment of the present application when two ends of the network socket are connected with plug crystal heads;

[0023] Figure 2 Structure diagram of PCB structure of network socket provided by an embodiment of the present application;

[0024] Figure 3 Structure diagram of network socket PCB structure forming interdigital capacitors provided by an embodiment of the present application;

[0025] Figure 4 Structure diagram of transmission line of first PCB layer forming multiple interdigital capacitors provided by an embodiment of the present application;

[0026] Figure 5 Structure diagram of transmission line of second PCB layer forming multiple interdigital capacitors provided by an embodiment of the present application;

[0027] Figure 6 Structure diagram of transmission line of third PCB layer forming multiple interdigital capacitors provided by an embodiment of the present application;

[0028] Figure 7 Structure diagram of transmission line of fourth PCB layer forming multiple interdigital capacitors provided by an embodiment of the present application;

[0029] Explanation of reference signs:

[0030] 1, first PCB layer; 2, first dielectric layer; 3, second PCB layer; 4, second dielectric layer; 5, third PCB layer; 6, third dielectric layer; 7, fourth PCB layer; 9, transmission line;

[0031] A, first filter area; B, second filter area; C, third filter area; D, fourth filter area;

[0032] A1, first interdigital capacitor; A2, second interdigital capacitor; A3, third interdigital capacitor; A4, fourth interdigital capacitor; A5, fifth interdigital capacitor;

[0033] B1, sixth interdigital capacitor;

[0034] C1, seventh interdigital capacitor;

[0035] D1, eighth interdigital capacitor; D2, ninth interdigital capacitor; D3, tenth interdigital capacitor; D4, eleventh interdigital capacitor; DETAILED DESCRIPTION

[0036] The terms used in the embodiment part of the present application are only used for explaining the specific embodiments of the present application, and are not intended to limit the present application, and the embodiment of the present application will be described in detail below in combination with the drawings.

[0037] like Figure 2 As shown, a PCB structure for a network socket that reduces crosstalk caused by untwisted Ethernet twisted pairs includes a first PCB layer 1, a first dielectric layer 2, a second PCB layer 3, a second dielectric layer 4, a third PCB layer 5, a third dielectric layer 6, and a fourth PCB layer 7 arranged sequentially from top to bottom.

[0038] like Figure 3 As shown, each layer contains two groups of eight signal transmissions. The signal transmission ends of the first group are S1, S2, S3, S4, S5, S6, S7 and S8, and the signal transmission ends of the second group are D1, D2, D3, D4, D5, D6, D7 and D8. S1 and D1 are connected through transmission line 9, S2 and D2 are connected through transmission line 9, S3 and D3 are connected through transmission line 9, S4 and D4 are connected through transmission line 9, S5 and D5 are connected through transmission line 9, S6 and D6 are connected through transmission line 9, S7 and D7 are connected through transmission line 9, and S8 and D8 are connected through transmission line 9.

[0039] like Figures 4 to 7 As shown, the first PCB layer 1 includes a first filter area A, the second PCB layer 3 includes a second filter area B, the third PCB layer 5 includes a third filter area C, and the fourth PCB layer 7 includes a fourth filter area F; each filter area is constructed with multiple interdigitated capacitors through the transmission lines 9 of the two signal transmission ends to reduce crosstalk.

[0040] The basic principle of interdigital capacitors is to utilize the energy storage properties of electromagnetic fields to store charge between interleaved metal electrode plates. This structure allows interdigital capacitors to store more charge because their effective electrode area is much larger than that of ordinary capacitors.

[0041] When an Ethernet twisted-pair cable is connected to a network socket, its signal is transmitted through the signal transmission terminals on each PCB layer. During transmission, crosstalk signals caused by the untwisting of the twisted pair are absorbed and filtered out by the interdigital capacitors in each filtering area, thereby reducing the impact of crosstalk on signal transmission quality.

[0042] like Figure 4As shown, in one embodiment, the first filter area A includes a first interdigital capacitor A1, a second interdigital capacitor A2, a third interdigital capacitor A3, a fourth interdigital capacitor A4, and a fifth interdigital capacitor A5. The first interdigital capacitor A1 is formed by the transmission lines 9 of the first signal transmission end D1 and the third signal transmission end D3. The second interdigital capacitor A2 is formed by the transmission lines 9 of the third signal transmission end S3 and the fifth signal transmission end S5. The third interdigital capacitor A3 is formed by the transmission lines 9 of the fifth signal transmission end S5 and the sixth signal transmission end S6. The fourth interdigital capacitor A4 is formed by the transmission lines 9 of the sixth signal transmission end S6 and the seventh signal transmission end S7. The fifth interdigital capacitor A5 is formed by the transmission lines 9 of the sixth signal transmission end S6 and the eighth signal transmission end S8.

[0043] In one embodiment, the first interdigital capacitor A1 is formed by the transmission lines 9 of the first signal transmission end D1 and the third signal transmission end D3, which are mutually surrounded and in the shape of a back character. This design not only increases the surface area of the capacitor, but also optimizes the electrical performance of the capacitor, so that the signal in a certain frequency range is effectively filtered.

[0044] In one embodiment, the third interdigital capacitor A3 is formed by the transmission lines 9 of the fifth signal transmission end S5 and the sixth signal transmission end S8, which are mutually surrounded and in the shape of a back character. This design not only increases the surface area of the capacitor, but also optimizes the electrical performance of the capacitor, so that the signal in a certain frequency range is effectively filtered.

[0045] In one embodiment, the second interdigital capacitor A2 is provided with two groups, and each group is formed by the transmission lines 9 of the third signal transmission end S3 and the fifth signal transmission end S5, which are respectively bent and inserted into each other and alternately arranged. This arrangement enhances the coupling effect of the capacitor and further improves the filtering effect.

[0046] In one embodiment, the fourth interdigital capacitor A4 is provided with two groups, and each group is formed by the transmission lines 9 of the sixth signal transmission end S6 and the seventh signal transmission end S7, which are respectively bent and inserted into each other and alternately arranged. This arrangement enhances the coupling effect of the capacitor and further improves the filtering effect.

[0047] In one embodiment, the fifth interdigital capacitor A5 is formed by the transmission lines 9 of the sixth signal transmission end S6 and the eighth signal transmission end S8, which are respectively bent and inserted into each other and alternately arranged. This arrangement enhances the coupling effect of the capacitor and further improves the filtering effect.

[0048] As shown, Figure 5As shown, in one embodiment, the second filtering region B includes two groups of sixth interdigitated capacitors B1. The first group of sixth interdigitated capacitors B1 is formed by bending and interpenetrating the transmission lines 9 of the third signal transmission terminal S3 and the fifth signal transmission terminal S5, and arranging them alternately. The second group of sixth interdigitated capacitors B1 is formed by bending and interpenetrating the transmission lines 9 of the third signal transmission terminal D3 and the fifth signal transmission terminal D5, and arranging them alternately. Similar to some of the interdigitated capacitors in the first filtering region A, multipath filtering of the signal is achieved.

[0049] like Figure 6 As shown, in one embodiment, the third filtering region C includes two groups of seventh interdigitated capacitors C1. The first group of seventh interdigitated capacitors C1 is formed by bending and interpenetrating the transmission lines 9 of the fourth signal transmission terminal S4 and the seventh signal transmission terminal S7, and arranging them alternately. The second group of seventh interdigitated capacitors C1 is formed by bending and interpenetrating the transmission lines 9 of the fourth signal transmission terminal D4 and the seventh signal transmission terminal D7, and arranging them alternately. This arrangement enhances the coupling effect of the capacitors, further improving the filtering effect. It also enriches the hierarchy of the filtering structure and improves the filtering accuracy.

[0050] like Figure 7 As shown, in one embodiment, the fourth filter region F includes an eighth interdigitated capacitor F1, a ninth interdigitated capacitor F2, a tenth interdigitated capacitor F3, and an eleventh interdigitated capacitor F4. The eighth interdigitated capacitor F1 is provided in two groups. One group is formed by bending and inserting the transmission lines 9 of the fourth signal transmission terminal S4 and the sixth signal transmission terminal S7 into each other and arranging them alternately. The other group is formed by bending and inserting the transmission lines 9 of the fourth signal transmission terminal F4 and the sixth signal transmission terminal F7 into each other and arranging them alternately. The ninth interdigitated capacitor F2 is formed by bending and inserting the transmission lines 9 of the sixth signal transmission terminal F6 and the eighth signal transmission terminal S8 into each other and arranging them alternately. The tenth interdigitated capacitor is formed by the transmission lines 9 of the third signal transmission terminal D3 and the fourth signal transmission terminal S4 surrounding each other in a U-shape. The eleventh interdigitated capacitor F4 is formed by the transmission lines 9 of the first signal transmission terminal D1 and the third signal transmission terminal S3 surrounding each other in a U-shape.

[0051] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0052] In the embodiments of the present application or implied device or element must have a specific orientation, in a particular orientation and operation, therefore can not be understood as a limitation of the embodiments of the present application. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more than two, unless otherwise specified.

[0053] The terms "first", "second", "third", "fourth" and the like in the description of the embodiments of the present application and the above-mentioned drawings (if any) are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein, for example, can be implemented in an order other than those illustrated or described herein. In addition, the terms "may include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0054] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, but not to limit them. Although the embodiments of the present application are described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features. The modification or replacement does not make the essence of the corresponding technical solution deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCB structure for a network jack that reduces crosstalk caused by untwisting of Ethernet twisted pair wires, comprising: a plurality of conductive traces on a substrate; a plurality of vias connecting the plurality of conductive traces; and a plurality of ground vias connecting the plurality of conductive traces to a ground plane. It includes a first PCB layer, a second PCB layer, a third PCB layer, and a fourth PCB layer. Each layer contains two sets of eight signal transmission terminals, which are connected by transmission lines. The first PCB layer includes a first filtering area, the second PCB layer includes a second filtering area, the third PCB layer includes a third filtering area, and the fourth PCB layer includes a fourth filtering area. Each filtering area forms multiple interdigital capacitors through the transmission lines of the two signal transmission terminals to reduce crosstalk.

2. The PCB structure of a network jack for reducing crosstalk caused by untwisting of Ethernet twisted pair wires according to claim 1, wherein: The first filtering region includes a first interdigitated capacitor, a second interdigitated capacitor, a third interdigitated capacitor, a fourth interdigitated capacitor, and a fifth interdigitated capacitor. The first interdigitated capacitor is constructed from the transmission line between the first signal transmission terminal and the third signal transmission terminal. The second interdigitated capacitor is constructed from the transmission line between the third signal transmission terminal and the fifth signal transmission terminal. The third interdigitated capacitor is constructed from the transmission line between the fifth signal transmission terminal and the sixth signal transmission terminal. The fourth interdigitated capacitor is constructed from the transmission line between the sixth signal transmission terminal and the seventh signal transmission terminal. The fifth interdigitated capacitor is constructed from the transmission line between the sixth signal transmission terminal and the eighth signal transmission terminal.

3. The PCB structure of a network jack for reducing crosstalk caused by untwisting of Ethernet twisted pair wires according to claim 2, wherein: The first interdigital capacitor is formed by the transmission lines of the first signal transmission terminal and the third signal transmission terminal wrapping around each other in a U-shape.

4. The PCB structure of a network jack for reducing crosstalk caused by untwisting of Ethernet twisted pair wires according to claim 2, wherein: The third interdigitated capacitor is formed by the transmission lines of the fifth signal transmission terminal and the sixth signal transmission terminal wrapping around each other in a U-shape.

5. The PCB structure of a network jack for reducing crosstalk caused by untwisting of Ethernet twisted pair wires according to claim 2, wherein: the first and second twisted pair wire ports are arranged in a staggered manner. The second interdigital capacitor is provided in two groups, and each group is formed by bending and inserting the transmission lines of the third signal transmission end and the fifth signal transmission end into each other and arranging them alternately.

6. The PCB structure of a network jack to reduce crosstalk caused by untwisting of Ethernet twisted pair wires according to claim 2, wherein: The fourth interdigital capacitor is provided in two groups, and each group is formed by bending and inserting the transmission lines of the sixth signal transmission end and the seventh signal transmission end into each other and arranging them alternately.

7. The PCB structure of a network jack to reduce crosstalk caused by untwisting of Ethernet twisted pair wires according to claim 2, wherein: The fifth interdigital capacitor is formed by bending and inserting the transmission lines of the sixth signal transmission end and the eighth signal transmission end into each other and arranging them alternately.

8. The PCB structure of a network jack for reducing crosstalk caused by untwisting of Ethernet twisted pair wires according to claim 1, wherein: The second filtering region includes two sets of sixth interdigitated capacitors, which are formed by bending and inserting the transmission lines of the third signal transmission end and the fifth signal transmission end into each other and arranging them alternately.

9. The PCB structure of a network jack for reducing crosstalk caused by untwisting of twisted pair Ethernet cables according to claim 1, wherein: The third filtering region includes two sets of seventh interdigitated capacitors, which are formed by bending and inserting the transmission lines of the fourth signal transmission end and the seventh signal transmission end into each other and arranging them alternately.

10. The PCB structure of a network jack for reducing crosstalk caused by untwisting of Ethernet twisted pair wires according to claim 1, wherein: The fourth filtering region includes an eighth interdigitated capacitor, a ninth interdigitated capacitor, a tenth interdigitated capacitor, and an eleventh interdigitated capacitor. The eighth interdigitated capacitor is provided in two groups, and each group is formed by bending and interpenetrating the transmission lines of the fourth signal transmission end and the sixth signal transmission end, and arranging them alternately. The ninth interdigitated capacitor is formed by bending and interpenetrating the transmission lines of the sixth signal transmission end and the eighth signal transmission end, and arranging them alternately. The tenth interdigitated capacitor is formed by the transmission lines of the third signal transmission end and the fourth signal transmission end wrapping around each other in a U-shape. The eleventh interdigitated capacitor is formed by the transmission lines of the first signal transmission end and the third signal transmission end wrapping around each other in a U-shape.

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