Memory structure

Abstract

The utility model relates to a memory structure. The memory structure comprises a plurality of memory units, each memory unit comprises two active regions and four gate structures, the length directions of the active regions extend along a first direction, the length directions of the gate structures extend along a second direction, and the second direction is perpendicular to the first direction. Each gate structure extends across a plurality of channel regions of the active region. The memory structure further includes a pair of gate-cut dielectric features at a plurality of cell edges between each memory cell and having a length direction extending along the first direction, each gate-cut dielectric feature contacting each of the four gate structures in each memory cell.

Description

TECHNICAL FIELD

[0001] The utility model relates to memory structure and its forming method, especially relate to gate-cut part. BACKGROUND

[0002] The electronics industry has experienced a continuous increase in demand for smaller and faster electronic devices that can simultaneously support a greater number and more complex and sophisticated functions. To meet these demands, there has been an unrelenting trend in the integrated circuit (IC) industry to produce low cost, high performance, and low power integrated circuits. These goals have been largely achieved by shrinking the size of integrated circuits (e.g., minimum feature size) to improve manufacturing efficiency and reduce associated costs. However, such size shrinkage has also increased the complexity of the integrated circuit fabrication process. Thus, achieving continuous evolution in integrated circuit devices and their performance requires similar evolution in the integrated circuit fabrication process and technology.

[0003] As technology nodes become smaller, uniformity control of active regions becomes an issue across adjacent cells (e.g., across adjacent static random access memory (SRAM) cells) and across adjacent elements (e.g., across adjacent N-type transistor elements and / or adjacent P-type transistor elements). For example, when forming fin active regions for fin field effect transistors (finFETs) or gate all around (GAA) transistors, very poor performance and worse element matching can result if the fin active region layout is unconventional (e.g., short fin length, random dense / isolated fin spacing, irregular fin end shape). In the layout of static random access memory cells, there is a risk of unconventional fin active region layout due to the need for the pull-up transistor to have discontinuous active regions to avoid leakage current between adjacent static random access memory cells. Having discontinuous active regions can cause performance issues due to poor isolation between the discontinuous active regions and / or irregular fin end shape. In addition, there can also be unintended bridging or merging between source / drain epitaxial parts of different adjacent elements due to insufficient and non-uniform isolation.

[0004] Thus, while existing structures and methods of implementing memory cell layouts are generally adequate for their intended purposes, they are not in every respect satisfactory. SUMMARY

[0005] A memory structure comprising: a plurality of memory cells, each memory cell comprising two active regions and four gate structures, a length direction of the active regions extending along a first direction, a length direction of the gate structures extending along a second direction, the second direction being perpendicular to the first direction, each gate structure extending across a plurality of channel regions of the active regions; and a pair of gate-cut dielectric features, at a plurality of cell edges between each memory cell and extending along the first direction, each gate-cut dielectric feature contacting each of the four gate structures in each memory cell.

[0006] In an embodiment, each memory cell is defined by a cell height along the first direction, and a cell width along the second direction, the cell height being greater than the cell width.

[0007] In an embodiment, the cell height is equal to four times a spacing between individual centerlines of two adjacent gate structures along the first direction, wherein the cell width is a spacing between individual centerlines of two adjacent gate-cut dielectric features along the second direction.

[0008] In an embodiment, a first memory cell and a second memory cell of the plurality of memory cells are adjacent to each other and share a bit line contact and a bit line bar contact, wherein a length direction of the bit line contact extends on and across a gate-cut dielectric feature of the plurality of gate-cut dielectric features to fall on a plurality of source / drain components of a plurality of first pass-gate transistors in the first memory cell and the second memory cell, wherein a length direction of the bit line bar contact extends across the gate-cut dielectric feature to fall on a plurality of source / drain components of a plurality of second pass-gate transistors in the first memory cell and the second memory cell.

[0009] In an embodiment, in each memory cell: two of the four gate structures comprise a plurality of dielectric gates, extending across a plurality of channel regions of a first active region of the two active regions, wherein the plurality of dielectric gates cut through the first active region along the second direction and directly abut one of the plurality of gate-cut dielectric features, wherein the plurality of dielectric gates are directly adjacent to a plurality of pull-up transistors formed on the first active region along the first direction.

[0010] In an embodiment, in each memory cell: the plurality of gate-cut dielectric features, the plurality of dielectric gates, and the plurality of metal gates of the four gate structures are each formed on an isolation structure on a substrate, wherein the plurality of gate-cut dielectric features and the plurality of dielectric gates penetrate into the isolation structure, and the plurality of dielectric gates penetrate into the isolation structure deeper than the plurality of gate-cut dielectric features.

[0011] In one embodiment, in each memory cell, the plurality of source / drain components formed on the two active regions includes a plurality of epitaxial components directly contacting the plurality of gate cut dielectric components.

[0012] A memory structure includes a first memory cell spanning between a first gate cut dielectric line and a second gate cut dielectric line, the length direction of the first and second gate cut dielectric lines extending along a first direction, and a second memory cell spanning between the second gate cut dielectric line and a third gate cut dielectric line, the length direction of the third gate cut dielectric line extending along the first direction. The first memory cell includes a first active region and a second active region on a substrate, the length direction of the first and second active regions extending along the first direction, and a plurality of first gate structures on a plurality of channel regions of the first and second active regions, the length direction of the first gate structures extending along a second direction, the second direction perpendicular to the first direction. The second memory cell includes a third active region and a fourth active region on the substrate, the length direction of the third and fourth active regions extending along the first direction, and a plurality of second gate structures on a plurality of channel regions of the third and fourth active regions, the length direction of the second gate structures extending along the second direction, wherein the second gate cut dielectric line directly contacts the side surfaces of the first and second gate structures.

[0013] In one embodiment, the first active region and the plurality of first gate structures form a first pass gate transistor, a first pull-down transistor, a second pull-down transistor, and a second pass gate transistor, wherein the second active region and the plurality of first gate structures form a first pull-up transistor and a second pull-up transistor, wherein the third active region and the plurality of second gate structures form a third pass gate transistor, a third pull-down transistor, a fourth pull-down transistor, and a fourth pass gate transistor, wherein the fourth active region and the plurality of second gate structures form a third pull-up transistor and a fourth pull-up transistor.

[0014] In one embodiment, the plurality of source / drain contacts on the plurality of source / drain regions of the first, second, third, and fourth active regions includes a bit line contact falling on a source region of the first and third pass gate transistors, and a bit line bar contact falling on a source region of the second and fourth pass gate transistors, wherein the bit line contact and the bit line bar contact fall on the top surface of the second gate cut dielectric line. BRIEF DESCRIPTION OF DRAWINGS

[0015] The schemes of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present application. It should also be noted that the accompanying drawings illustrate only general embodiments of the present application and should not be considered limiting in scope, as the present application can be equally applied to other embodiments. In addition, the accompanying drawings can implicitly describe components not detailed in the specification.

[0016] Figure 1 is a static random access memory array having a plurality of memory cells and bit lines and word lines each extending over the memory cells, according to an embodiment of the present application.

[0017] Figure 2 is a circuit diagram of a static random access memory array having a plurality of memory cells, according to an embodiment of the present application.

[0018] Figure 3 、 4A , 4B, 5A, and 5B are top view cell layouts of a static random access memory array as in Figure 1 corresponding to the circuit diagram of Figure 2 , according to an embodiment of the present application.

[0019] Figure 6 is a top view cell layout of a static random access memory array having two adjacent memory cells, according to an embodiment of the present application.

[0020] Figure 7A is a cross-sectional view of a static random access memory array taken along line segment A of Figure 6 , according to an embodiment of the present application.

[0021] Figure 7B is a cross-sectional view of a static random access memory array taken along line segment B of Figure 6 , according to an embodiment of the present application.

[0022] Figure 7C-1 and Figure 7C-2 is a cross-sectional view of a static random access memory array taken along line segment C of Figure 6 , according to an embodiment of the present application.

[0023] Figure 7D-1 and Figure 7D-2 is a cross-sectional view of a static random access memory array taken along line segment D of Figure 6 , according to an embodiment of the present application.

[0024] Figure 7E-1 and Figure 7E-2 is a cross-sectional view showing a static random access memory array cut along a line segment E according to an embodiment of the present application. Figure 6

[0025] Figure 7F-1 and Figure 7F-2 is a cross-sectional view showing a static random access memory array cut along a line segment F according to an embodiment of the present application. Figure 6

[0026] Figure 7G is a cross-sectional view showing a static random access memory array cut along a line segment G according to an embodiment of the present application. Figure 6

[0027] Figure 7H is a cross-sectional view showing a static random access memory array cut along a line segment H according to an embodiment of the present application. Figure 6

[0028] Figure 8 is a top view layout of a static random access memory array having two adjacent memory cells according to another embodiment of the present application.

[0029] Figure 8I is a cross-sectional view showing a static random access memory array cut along a line segment I according to an embodiment of the present application. Figure 8

[0030] Figure 8J is a cross-sectional view showing a static random access memory array cut along a line segment J according to an embodiment of the present application. Figure 8

[0031] Figure 9 , 10 , 11, and 12 are top view layouts of a static random access memory array corresponding to circuit diagrams of Figure 2

[0032] Figure 13 is a method of forming a static random access memory array having a gate terminal dielectric line according to an embodiment of the present application.

[0033] wherein the reference numerals are explained as follows:

[0034] 100: substrate

[0035] 101: isolation structure

[0036] ​​​​​​​102: Static random access memory array

[0037] 104: Memory cell

[0038] 104a: Memory cell

[0039] 104a': Memory cell

[0040] 104b: Memory cell

[0041] 104b': Memory cell

[0042] 106: Active region

[0043] 106-1: N-type active region

[0044] 106-2: P-type active region

[0045] 106a: Channel region

[0046] 106b: Source / drain region

[0047] 108: Gate

[0048] 109: Gate dielectric

[0049] 111: Gate spacer

[0050] 112: Source / drain contact

[0051] 113: Inner spacer

[0052] 116: Gate via

[0053] 120: Source / drain via

[0054] 130: Interlayer dielectric

[0055] 136: Transistor channel

[0056] 142: Source / drain bottom dielectric

[0057] 180: Gate cap

[0058] 208: Dielectric gate

[0059] 302: Element layout

[0060] 308: Gate cut dielectric line

[0061] 316: Silicide feature

[0062] 402a: Element layout

[0063] 402b: Element layout

[0064] 502a: element layout

[0065] 502b: element layout

[0066] 602: element layout

[0067] 802: element layout

[0068] 902: element layout

[0069] 1002: element layout

[0070] 1102: element layout

[0071] 1202: element layout

[0072] 1300: method

[0073] 1302: operation

[0074] 1304: operation

[0075] 1306: operation

[0076] 1308a-1: operation

[0077] 1308a-2: operation

[0078] 1308b-1: operation

[0079] 1308b-2: operation

[0080] 1308b-3: operation

[0081] 1310: operation

[0082] 1312: operation

[0083] 1314: operation

[0084] A: line segment

[0085] B: line segment

[0086] BL1: bit line

[0087] BL2: bit line

[0088] BL M1: bit line landing pad

[0089] BL M2: bit line landing pad

[0090] BL M3: bit line metal

[0091] BLB1: bit line bar

[0092] BLB2: bit line bar

[0093] BLB M1: bit line bar landing pad

[0094] BLB M2: bit line bar landing pad

[0095] BLB M3: bit line bar metal

[0096] C: line segment

[0097] C-1: cross-section

[0098] C-2: cross-section

[0099] D: line segment

[0100] D-1: cross-section

[0101] D-2: cross-section

[0102] E: line segment

[0103] E-1: cross-section

[0104] E-2: cross-section

[0105] F: line segment

[0106] F-1: cross-section

[0107] F-2: cross-section

[0108] G: line segment

[0109] H: line segment

[0110] I: line segment

[0111] J: line segment

[0112] LI M1: local interconnect line

[0113] M1: first metal line

[0114] M2: second metal line

[0115] M3: third metal line

[0116] PD1: pull-down transistor

[0117] PD1': pull-down transistor

[0118] PD2: pull-down transistor

[0119] PD2': pull-down transistor

[0120] PD3: pull-down transistor

[0121] PD3': pull-down transistor

[0122] PD4: pull-down transistor

[0123] PD4': pull-down transistor

[0124] PG1: pass-gate transistor

[0125] PG1': pass-gate transistor

[0126] PG2: pass-gate transistor

[0127] PG2': pass-gate transistor

[0128] PG3: pass-gate transistor

[0129] PG3': pass-gate transistor

[0130] PG4: pass-gate transistor

[0131] PG4': pass-gate transistor

[0132] PU1: pull-up transistor

[0133] PU1': pull-up transistor

[0134] PU2: pull-up transistor

[0135] PU2': pull-up transistor

[0136] PU3: pull-up transistor

[0137] PU3': pull-up transistor

[0138] PU4: pull-up transistor

[0139] PU4': pull-up transistor

[0140] V1: first via

[0141] V2: second via

[0142] Vdd M1: high voltage landing pad

[0143] Vss M1: low voltage landing pad

[0144] Vss M2: low voltage landing pad

[0145] Vss M3: low voltage metal

[0146] WL-1M1: word line landing pad

[0147] WL-1M2: word line metal

[0148] WL-2M1: word line landing pad

[0149] WL-2M2: word line metal

[0150] WL_1: first word line

[0151] WL_2: second word line DETAILED DESCRIPTION

[0152] The following disclosure provides many different embodiments, or examples, for implementing different components of the provided transaction. Specific examples of components and configurations are described below to provide a thorough description of embodiments of the application. Of course, it is contemplated that the application can be practiced with embodiments other than those described specifically herein. For example, the above description may have mentioned forming a first component on a second component, which can include embodiments where the first and second components are formed in direct contact, and embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Furthermore, the application can be implemented in various examples with repeated use of reference characters and / or numbers to identify like elements. This repetition of reference characters and / or numbers is intended to aid the reader in identifying common components in various embodiments of the application.

[0153] In addition, spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper", "over", and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0154] In addition, when a numerical or a numerical range is described herein, this description is intended to encompass numbers within a reasonable range of the number or range of numbers described, as understood by those skilled in the art, such as within ±10% of the number or range of numbers described, or other numbers. For example, if manufacturing tolerances associated with depositing a layer of material are known by those skilled in the art to be ±10%, a layer of material having a thickness of "about 5 nanometers" can encompass a range of sizes from 4.5 nanometers to 5.5 nanometers. When comparing a size or a dimension of a component to a size or a dimension of another component, the terms "substantially the same", "essentially the same", "similar size", and the like, can be understood to be within ±10% of the compared components. In addition, the sizes of different components disclosed can implicitly disclose a ratio of sizes between the different components.

[0155] The present utility model relates to memory devices and structures, and in particular to memory structures with gate-cut dielectric lines on the edges of memory cells, and shared bit lines and bit line bars that cross adjacent memory cells. The memory structures can employ an array of static random access memory (SRAM) cells. The gate-cut dielectric lines, bit lines, and bit line bars provide benefits in cell performance. For example, the gate-cut (or gate-end) dielectric lines avoid unintended bridging or merging between the source / drain (S / D) epitaxial components of different adjacent memory devices. In addition, the gate-cut dielectric lines provide proper isolation between the active regions of different memory cells, thus resolving concerns of line-end scaling when forming interrupted active regions. Furthermore, the gate-cut dielectric lines allow for smaller gate-end spacing between the gates of different memory cells due to the dedicated gate-cut regions. In addition, the shared bit line and bit line bar design merges two memory cells to have a pair of bit lines and a pair of bit line bars, allowing for wider bit lines and bit line bars for larger memory arrays, or allowing for larger metal spacing of other metal components to reduce parasitic capacitance. The present utility model includes other layout improvements, such as dielectric gate portions to isolate pull-up transistors, additional gate-cut components to avoid noise coupling, and various placements of local interconnects, bit lines, bit line bars, and word lines that further improve cell performance and uniformity control.

[0156] Figure 1 A static random access memory array 102 is shown with a plurality of memory cells 104 adjacent to each other along an X direction. The memory cells 104 can include memory cell 104a, memory cell 104b, memory cell 104b', and memory cell 104a'. For example, memory cell 104a corresponds to cell-1, memory cell 104b corresponds to cell-2, memory cell 104b' corresponds to cell-3, and memory cell 104a' corresponds to cell-4. As shown, cell-1 and cell-2 share a vertical cell edge along a Y direction, cell-2 and cell-3 share a vertical cell edge along the Y direction, and cell-3 and cell-4 share a vertical cell edge along the Y direction. Although not shown, the static random access memory array 102 can include additional memory cells 104. For example, additional memory cells 104 can be adjacent to the top and / or bottom horizontal cell edges (X direction) of cell-1 through cell-4. By way of another example, additional memory cells 104 can be adjacent to the vertical cell edges (Y direction) of cell-1 and / or cell-4.

[0157] With continued reference to Figure 1 The static random access memory array 102 includes a first pair of bit signal lines (e.g., bit line BL1 and bit line bar BLB1) for cell-1 and cell-2. Cell-1 and cell-2 share the same bit line BL1 and the same bit line bar BLB1. The length of the bit line BL1 extends across cell-2 along the Y direction, while the length of the bit line bar BLB1 extends across cell-1 along the Y direction. The bit line BL1 can land on a via connection on the top edge of cell-2. The bit line bar BLB1 can land on a via connection on the bottom edge of cell-1.

[0158] The static random access memory array 102 further includes a second pair of bit signal lines (e.g., bit line BL2 and bit line bar BLB2) for cell-3 and cell-4. Cell-3 and cell-4 share the same bit line BL2 and the same bit line bar BLB2. The length of the bit line BL2 extends across cell-3 along the Y direction, while the length of the bit line bar BLB2 extends across cell-4 along the Y direction. The bit line BL2 can land on a via connection on the top edge of cell-3. The bit line bar BLB2 can land on a via connection on the bottom edge of cell-4.

[0159] The static random access memory array 102 further includes a first word line WL_1 and a second word line WL_2 extending across cell-1 through cell-4. In the illustrated embodiment, cell-1 and cell-4 share the same first word line WL_1, while cell-2 and cell-3 share the same second word line WL_2. For example, the first word line WL_1 can land on a via connection within cell-1 and cell-4, while the second word line WL_2 can land on a via connection within cell-2 and cell-3.

[0160] With continued reference to Figure 1The first word line WL l and the second word line WL 2 can extend continuously in the X direction across additional, not shown, memory cells 104, each connected to a different group of memory cells 104. The bit lines BLl, BL2, bit line bar BLBl, and bit line bar BLB2 can also extend continuously in the Y direction across additional, not shown, memory cells 104, each connected to a different pair of memory cells 104. In one embodiment, there can be a pair of shared bit lines (e.g., bit line BLl and bit line bar BLBl for cell- 1 and cell-2) for every two adjacent memory cells 104 (e.g., memory cell 104a and memory cell 104b).

[0161] Figure 2 A circuit diagram of a static random access memory array 102 having a plurality of memory cells 104 is shown. In the present embodiment, the circuit diagram corresponds to four memory cells 104 (also referred to herein as static random access memory cells) of a static random access memory array 102. The circuit diagram is consistent with the static random access memory array 102 of Figure 1 and can depict the static random access memory array 102 of Figure 1 As shown, the static random access memory array 102 includes memory cell 104a, memory cell 104a', memory cell 104b, and memory cell 104b'. Each of the memory cells 104a, 104a', 104b, and 104b' is formed with six transistors (two pull-down transistors, two pull-up transistors, and two pass-gate transistors). Each transistor is defined by a source, a drain, and a gate. Each memory cell 104 stores a bit of storage by way of the pull-down and pull-up transistors, and the memory cell 104 is addressed by way of the word and bit lines by way of the pass-gate transistors.

[0162] Memory cell 104a includes pull-up transistor PU1, pull-up transistor PU2, pull-down transistor PD1, pull-down transistor PD2, pass-gate transistor PG1, and pass-gate transistor PG2. The sources of pull-up transistor PU1 and pull-up transistor PU2 are coupled together and connected to a high voltage Vdd. The sources of pull-down transistor PD1 and pull-down transistor PD2 are coupled together and connected to a low voltage Vss or ground. The gates of pull-up transistor PU1 and pull-down transistor PD1 are coupled together and connected to a common drain of pull-up transistor PU2, pull-down transistor PD2, and pass-gate transistor PG2. The gates of pull-up transistor PU2 and pull-down transistor PD2 are coupled together and connected to a common drain of pull-up transistor PU1, pull-down transistor PD1, and pass-gate transistor PG1. Pull-up transistor PU1, pull-up transistor PU2, pull-down transistor PD1, and pull-down transistor PD2 form a first set of cross coupled inverters to store a data bit. The source of pass-gate transistor PG1 is connected to bit line BL1, and the source of pass-gate transistor PG2 is connected to bit line BLB1. The gates of pass-gate transistor PG1 and pass-gate transistor PG2 are connected to a first word line WL_1.

[0163] Memory cell 104b includes pull-up transistor PU3, pull-up transistor PU4, pull-down transistor PD3, pull-down transistor PD4, pass-gate transistor PG3, and pass-gate transistor PG4. The sources of pull-up transistor PU3 and pull-up transistor PU4 are coupled together and connected to a high voltage Vdd. The sources of pull-down transistor PD3 and pull-down transistor PD4 are coupled together and connected to a low voltage Vss or ground. The gates of pull-up transistor PU3 and pull-down transistor PD3 are coupled together and connected to a common drain of pull-up transistor PU4, pull-down transistor PD4, and pass-gate transistor PG4. The gates of pull-up transistor PU4 and pull-down transistor PD4 are coupled together and connected to a common drain of pull-up transistor PU3, pull-down transistor PD3, and pass-gate transistor PG3. Pull-up transistor PU3, pull-up transistor PU4, pull-down transistor PD3, and pull-down transistor PD4 form a second set of cross coupled inverters to store a data bit. The source of pass-gate transistor PG3 is connected to the same bit line BL1, and the source of pass-gate transistor PG4 is connected to the same bit line BLB1. The gates of pass-gate transistor PG3 and pass-gate transistor PG4 are connected to a second word line WL_2.

[0164] Memory cell 104a' and memory cell 104b' are configured similarly to memory cell 104a and memory cell 104b, respectively. Memory cell 104a' includes pull-up transistor PU1', pull-up transistor PU2', pull-down transistor PD1', pull-down transistor PD2', pass-gate transistor PG1', and pass-gate transistor PG2'. Memory cell 104b' includes pull-up transistor PU3', pull-up transistor PU4', pull-down transistor PD3', pull-down transistor PD4', pass-gate transistor PG3', and pass-gate transistor PG4'. For simplicity, similar configurations and connections will not be repeated here. Memory cell 104a' and memory cell 104b' include a third set of cross-coupled inverters and a fourth set of cross-coupled inverters to individually store a data bit. The sources of pass-gate transistor PG1' and pass-gate transistor PG3' are connected to bit line BL2. The sources of pass-gate transistor PG2' and pass-gate transistor PG4' are connected to bit line BLB2. Memory cell 104a' shares the same first word line WL_1 as memory cell 104a, while memory cell 104b' shares the same second word line WL_2 as memory cell 104b. That is, the gates of pass-gate transistor PG1' and pass-gate transistor PG2' are also connected to first word line WL_1, and the gates of pass-gate transistor PG3' and pass-gate transistor PG4' are also connected to second word line WL_2.

[0165] It should be noted that, Figure 2 An example embodiment of a static random access memory array is shown, but other configurations are possible. For example, in other embodiments, the source and drain nodes of different pull-up and pull-down transistors can be flipped. Also, the high voltage Vdd node and the low voltage Vss node can also be flipped. In other words, in some embodiments, high voltage Vdd can be connected to the source or drain of either of the pull-up and pull-down transistors of the static random access memory array. Also, in other embodiments, low voltage Vss or ground can be connected to the source or drain of either of the pull-up and pull-down transistors of the static random access memory array. As such, electrical connections to high voltage Vdd and low voltage Vss here are referred to as power lines, power signal lines, or power line connections, which provide a circuit to turn on the pull-up and pull-down transistors in memory cell 104.

[0166] Figure 3 An upper view layout 302 of static random access memory array 102 is shown, as Figure 1 The static random access memory array 102 of FIG. 3A and corresponding to Figure 2circuit diagram. The element layout 302 represents a partial memory structure having various semiconductor components, as described herein. As shown, the element layout 302 includes memory cell 104a, memory cell 104b, memory cell 104b', and memory cell 104a', defined by dashed cell edges. The memory cell 104a, memory cell 104b, memory cell 104b', and memory cell 104a' can correspond to Figure 2 memory cell 104a, memory cell 104b, memory cell 104b', and memory cell 104a'.

[0167] The memory cell 104a and memory cell 104b are adjacent to each other in the X direction and mirror each other across the vertical cell edge between them. The memory cell 104b' and memory cell 104a' are adjacent to each other in the X direction and mirror each other across the vertical cell edge between them. The memory cell 104a and memory cell 104b, which correspond to cell-1 and cell-2 of group-1, share a first pair of bit line signal contacts (e.g., bit line contact and bit line stripe contact). The memory cell 104b' and memory cell 104a', which correspond to cell-3 and cell-4 of group-2, share a second pair of bit line signal contacts (e.g., bit line contact and bit line stripe contact). Further, as shown by the portions of different transistors (pull-down transistor PD1, pull-down transistor PD2, etc.), group-2 mirrors group-1 across the Y axis (e.g., pull-up transistor PU3 mirrors pull-up transistor PU3', pull-down transistor PD3 mirrors pull-down transistor PD3', etc.).

[0168] Figure 3 The location of each of the pull-up transistor PU1, pull-up transistor PU1', pull-up transistor PU2, pull-up transistor PU2', pull-up transistor PU3, pull-up transistor PU3', pull-up transistor PU4, pull-up transistor PU4', pull-down transistor PD1, pull-down transistor PD1', pull-down transistor PD2, pull-down transistor PD2', pull-down transistor PD3, pull-down transistor PD3', pull-down transistor PD4, pull-down transistor PD4', pass-gate transistor PG1, pass-gate transistor PG1', pass-gate transistor PG2, pass-gate transistor PG2', pass-gate transistor PG3, pass-gate transistor PG3', pass-gate transistor PG4, and pass-gate transistor PG4' is indicated on the gate 108 of each transistor. How each transistor is connected to each other has been described with reference to Figure 2 and will not be repeated here for the sake of simplicity. It should be noted that each of these transistors is formed and defined by the individual channel regions of the active region 106 under the individual gates 108, and the source / drain regions adjacent to the channel regions having epitaxial components.

[0169] The element layout 302 includes several active regions 106 extending along the Y direction. The active regions 106 can be configured for planar, fin, or fully wrapped gate semiconductor structures. In one embodiment, the active regions 106 are fin structures that protrude in the positive Z direction from the substrate. The active regions 106 can include N-type active regions 106-1 that form pull-down transistors and pass-gate transistors (e.g., pass-gate transistor PG1, pull-down transistor PD1, pull-down transistor PD2, and pass-gate transistor PG2), and P-type active regions 106-2 that form pull-up transistors (e.g., pull-up transistor PU1 and pull-up transistor PU2). The P-type active regions 106-2 are discontinuous and extend shorter along the Y direction than the N-type active regions 106-1. As shown, the P-type active regions 106-2 are segmented due to being cut apart by dielectric gate portions 208 of the gates 108. In this way, the P-type active regions 106-2 span a length that is at most less than the height of the memory cells 104 along the Y direction. On the other hand, the N-type active regions 106-1 can span multiple memory cells 104 continuously along the Y direction. In some embodiments, as shown, the N-type active regions 106-1 can be wider than the P-type active regions 106-2 in the X direction.

[0170] The element layout 302 includes a plurality of gates 108 disposed on channel regions of the active regions 106. The channel region (or transistor channel) represents the portion of the active region 106 directly underneath the gate 108. Adjacent to the channel region (e.g., between gates 108 along the Y direction) are source / drain regions of the active region 106. The source / drain regions can individually or collectively represent a source or a drain, depending on the context. For the N-type active regions 106-1, the source / drain regions can include epitaxial components doped with N-type dopants, such as phosphor (P) or arsenic (As). For the P-type active regions 106-2, the source / drain regions can include epitaxial components doped with P-type dopants, such as boron (B). The epitaxial components can be grown from semiconductor material using suitable epitaxial growth techniques.

[0171] The length of the gate 108 extends in the X direction and is non-continuous due to being cut apart by the gate cut dielectric lines 308, which extend in the length direction along the Y direction. The gate 108 is a gate structure that includes a metal gate (also referred to as a metal gate portion), and in some cases, also includes a dielectric gate 208 (also referred to as a dielectric gate portion). In each memory cell 104, two gates 108 include a metal gate (or metal gate portion) that continuously spans between the gate cut dielectric lines 308. The metal gate can include a gate spacer around a gate stack, and the gate stack can include a gate electrode on a gate dielectric. In each memory cell 104, the other two gates 108 include a metal gate (or metal gate portion) and a dielectric gate 208 (or dielectric gate portion) that together continuously span between the gate cut dielectric lines 308. In particular, the dielectric gate 208 is incorporated into the gate 108 that sandwiches a pull-up transistor (such as pull-up transistor PU1 and pull-up transistor PU2) in the Y direction. The dielectric gate 208 cuts through the channel region of the P-type active region 106-2 to isolate the pull-up element in one memory cell 104 from the pull-up element in the adjacent memory cell 104 (in the Y direction). By incorporating the dielectric gate 208, the P-type active region 106-2 can first be continuously formed, similar to the N-type active region 106-1. Thereafter, when the gate 108 is formed, the P-type active region 106-2 is cut apart so as to be isolated. Thereafter, the dielectric gate 208 is formed in the cut apart region. This process resolves concerns of line end narrowing when forming the broken active region 106.

[0172] The element layout 302 includes a gate cut dielectric line 308 disposed along the vertical cell edges of the memory cells 104. The gate cut dielectric line 308 can also be referred to herein as a gate cut dielectric feature, a gate end dielectric line, or a gate end cut structure. The gate cut dielectric line 308 is in direct contact with the side surfaces of the gate 108. The gate cut dielectric line 308 extends continuously along the Y-direction and cuts through the gate 108 extending along the Y-direction, such that the isolated gate 108 is self-contained in the individual memory cell 104a. In other words, the gate 108 in one memory cell 104 (e.g., memory cell 104a) is isolated and separated from the gate 108 in an adjacent memory cell 104 (e.g., memory cell 104b) by the gate cut dielectric line 308. Furthermore, the gate cut dielectric line 308 also cuts through any overgrown source / drain features grown from the source / drain regions of the active region 106, and the source / drain features in one memory cell 104 (e.g., memory cell 104a) are isolated and separated from the source / drain features in an adjacent memory cell 104 (e.g., memory cell 104b) by the gate cut dielectric line 308. In this way, the continuous gate cut dielectric line 308 avoids concerns of source / drain epitaxial overgrowth bridging (or merging), and allows the source / drain features to a maximum epitaxial size (e.g., reaching and stopping at the gate cut dielectric line 308). As such, the source / drain regions in the N-type active region 106-1 can be scaled up to have a larger volume to reduce source / drain resistance (N-type metal-oxide semiconductor field effect transistor (MOSFET) of silicon phosphide (SiP) or silicon carbophosphide (SiCP)), while the source / drain regions in the P-type active region 106-2 can be scaled up to have a larger volume to act as a strain film (P-type MOSFET of silicon germanium (SiGe)), thereby benefiting overall cell performance. Furthermore, by having a clearly defined gate cut isolation, the gate cut dielectric line 308 also allows for a smaller gate end spacing with superior gate critical dimension uniformity control. In one embodiment, the gate to gate end isolation can be in the range of 3 nm to 20 nm (e.g., the width of the gate cut dielectric line 308 in the X-direction).

[0173] In the illustrated embodiment, each memory cell 104 is defined by two active regions 106 (e.g., N-type active region 106-1 and P-type active region 106-2), and four gates 108 extending over the two active regions 106. The N-type active region 106-1 and individual gates 108 form two pass-gate transistors that sandwich two pull-down transistors along the Y direction. The P-type active region 106-2 and individual gates 108 form two dielectric gates 208 that sandwich a pull-up transistor along the Y direction. For example, in each cell, the top and bottom gates 108 along the Y direction are gates 108 of pass-gate transistors (e.g., pass-gate transistor PG1 and pass-gate transistor PG2) that have a dielectric gate 208, and a metal gate portion. In addition, in each cell, the middle gate 108 along the Y direction is a gate 108 of a pull-down transistor and a pull-up transistor (e.g., a gate 108 shared by pull-down transistor PD1 and pull-up transistor PU1, and a gate 108 shared by pull-down transistor PD2 and pull-up transistor PU2) that has only a metal gate portion. Furthermore, each memory cell 104 is defined by a gate cut dielectric line 308 disposed along a vertical cell edge of the memory cell 104. In other words, each memory cell 104 spans between two gate cut dielectric lines 308. It should be noted that, similar to the metal portion of the gates 108, the dielectric gates 208 can extend to directly contact a side surface of the gate cut dielectric line 308.

[0174] With continued reference to Figure 3 Each memory cell 104 is defined by a cell height along the Y direction (e.g., Y1-pitch) and a cell width along the X direction (e.g., X1-pitch), the cell height being greater than the cell width. The cell height (e.g., Y1-pitch) is substantially equal to four times a spacing between individual centerlines of gates 108 of two adjacent cells along the Y direction. The cell width (e.g., X1-pitch) is a spacing between individual centerlines of two adjacent gate cut dielectric lines 308 along the X direction. In one embodiment, a ratio of the cell height to the cell width is in a range between 1.2 and 2.6.

[0175] With continued reference to Figure 3The element layout 302 further includes source / drain contacts 112 on the source / drain regions of the active regions 106. The source / drain contacts 112 can be metal contacts (e.g., tungsten, W) that are located on the source / drain epitaxial features in the source / drain regions of the active regions 106. As shown, the source / drain contacts 112 can be shared slot contacts that extend in the X-direction to be located on multiple source / drain regions of different transistors. The source / drain contacts can include: (1) node contacts, such as data node contacts and data node bar contacts, that connect the shared drain of the pull-down transistor, the pull-up transistor, and the pass-gate transistor together; (2) power line contacts, such as low voltage Vss contacts and high voltage Vdd contacts, to connect the shared source of the individual pull-down transistor and pull-up transistor together; and (3) bit line contacts, such as bit line contacts and bit line bar contacts, that connect the shared source of the individual pass-gate transistor together. For every two adjacent memory cells 104 (e.g., cell-1 and cell-2, or cell-3 and cell-4), the shared bit line contacts and shared bit line bar contacts extend across the vertical cell edges. As shown, the bit line contacts and bit line bar contacts can extend on and be located on the top surface of the gate cut dielectric lines 308. In addition, as shown, the low voltage Vss contacts and high voltage Vdd contacts can also extend on and be located on the top surface of the gate cut dielectric lines 308.

[0176] Figure 4A An upper view element layout 402a of the static random access memory array 102 is shown, as Figure 1 The static random access memory array 102 of Figure 2 corresponds to the circuit diagram of Figure 4A The element layout 402a represents a partial memory structure with various semiconductor components, as described herein. Figure 3 For simplicity, similar components will not be repeated here. The differences are, Figure 4AFurther shown are gate vias 116, source / drain vias 120, and first metal lines Ml. Gate vias 116 are located on gates 108 (or on their metal gate portions). Source / drain vias 120 are located on source / drain contacts 112. First metal lines Ml are located on gate vias 116 and / or source / drain vias 120. Gate vias 116 and source / drain vias 120 pull individual gates 108 and source / drain contacts 112 to higher material layers (e.g., a first metal layer having first metal lines Ml). As shown, first metal lines Ml include local connection lines LIMl, word line landing pads WL-IMl, word line landing pads WL-2Ml, bit line landing pads BLMl, bit line bar landing pads BLBMl, high voltage landing pads VddMl, and low voltage landing pads VssMl. In the embodiment shown, each memory cell 104 includes two local connection lines LIMl, one electrically connected to a data node contact of a source / drain contact 112 having a gate 108, and the other electrically connected to a data node bar contact of a source / drain contact 112 having another gate 108. Each memory cell 104 includes either word line landing pad WL-IMl or word line landing pad WL-2Ml located between the two local connection lines LIMl along the X direction. Word line landing pad WL-IMl and word line landing pad WL-2Ml are each located on two gate vias 116 connected to a pass gate transistor. At the vertical cell edge of memory cell 104, there are bit line landing pad BLMl, bit line bar landing pad BLBMl, high voltage landing pad VddMl, and low voltage landing pad VssMl. Each landing pad is located on a source / drain via 120 and provides a landing area to pull its individual node (e.g., bit line, bit line bar, high voltage, and low voltage) to a higher material layer (e.g., a second metal layer having second metal lines M2). In the embodiment shown, there is one high voltage landing pad VddMl per two Xl-pitches at one vertical cell edge, and one bit line landing pad BLMl, one bit line bar landing pad BLBMl, and one low voltage landing pad VssMl per two Xl-pitches at the opposite vertical cell edge.

[0177] Figure 4B An upper view element layout 402b of static random access memory array 102 is shown, as Figure 1 The static random access memory array 102 of Figure 2 corresponds to the circuit diagram of Figure 4B Element layout 402b represents a partial memory structure with various semiconductor components, as described herein. Figure 4A For simplicity, similar components will not be repeated here. The differences are, Figure 4B Only Figure 4Aof the first metal lines Ml, while components disposed thereunder are filtered out for illustration. Figure 4B Further shown are first vias Vl disposed on the first metal lines Ml, second metal lines M2 disposed on the first vias Vl, second vias V2 disposed on the second metal lines M2, and third metal lines M3 disposed on the second vias V2. The first vias Vl pull individual first metal lines Ml to a higher material layer (e.g., a second metal layer having the second metal lines M2). The second vias V2 pull individual second metal lines M2 to a higher material layer (e.g., a third metal layer having the third metal lines M3). As shown, the second metal lines M2 include word line metal WL-l M2 and word line metal WL-2 M2. The word line metal WL-l M2 and the word line metal WL-2 M2 are global word lines each continuously extending in length along the X direction across a plurality of memory cells 104 in a column. Each memory cell 104 includes the word line metal WL-l M2 and the word line metal WL-2 M2 extending across the memory cell 104. The word line metal WL-l M2 and the word line metal WL-2 M2 each electrically connect gates 108 of pass-gate transistors in different memory cells 104 together. Note that the word line metal WL-l M2 and the word line metal WL-2 M2 are each connected to different groups of memory cells 104.

[0178] Continuing to refer to Figure 4B As shown, the second metal lines M2 further include low voltage landing pads Vss M2, bit line landing pads BL M2, and bit line bar landing pads BLB M2. Each landing pad is disposed on a first via Vl and provides a landing region to pull its individual node (e.g., low voltage, bit line, and bit line bar) to a higher material layer (e.g., a third metal layer having the third metal lines M3). As shown, the third metal lines M3 include bit line metal BL M3 and bit line bar metal BLB M3. The bit line metal BL M3 and the bit line bar metal BLB M3 are global bit lines and bit line bars each continuously extending in length along the Y direction across a plurality of memory cells 104 in a row. In this embodiment, each memory cell 104 includes only one bit line metal BL M3 or one bit line bar metal BLB M3 extending across the memory cell 104, which each pull a bit line or a bit line bar of two adjacent memory cells 104. The third metal lines M3 further include low voltage metal Vss M3 continuously extending in length along the Y direction along a vertical cell edge. Each low voltage metal Vss M3 is disposed between the bit line metal BL M3 and the bit line bar metal BLB M3 along the X direction.

[0179] Continuing to refer to Figure 4BThe layout design of sharing the neighboring bitline and bitline bar, and the strategic placement of the first metal line Ml, the second metal line M2, and the third metal line M3 each allows for improved cell performance. For example, the layout design allows for more space to implement a wider bitline metal BL M3 and bitline bar metal BLB M3, or to implement a greater spacing between the bitline metal BL M3 and the bitline bar metal BLB M3 to reduce parasitic capacitance. In the present embodiment, the global bitline and bitline bar are moved from the first metal layer with the first metal line Ml to the third metal layer with the third metal line M3, thereby freeing up space in the first metal layer and the third metal layer. In the present embodiment, the global bitline and bitline bar (e.g., in the third metal layer) are disposed above the global wordline (e.g., in the second metal layer).

[0180] Figure 5A and Figure 5B shows top view cell layouts 502a and 502b of the static random access memory array 102 as Figure 1 Figure 2 Figure 5A and Figure 5B are similar to Figure 4A and Figure 4B , for simplicity, similar components will not be repeated here. The difference is that, Figure 5A and Figure 5B show embodiments with different layout configurations for the first metal line Ml. As shown in Figure 5A and Figure 5B , the wordline landing pad WL-1M1 or the wordline landing pad WL-2M1 in each memory cell 104 is located along the X direction between the local interconnect line LI M1 and the low voltage landing pad Vss M1 (or the bitline landing pad BL M1 or the bitline bar landing pad). As such, the location of the first via V1 connected to the wordline metal WL-1M2 and the wordline metal WL-2M2 also changes (refer to Figure 5B ).

[0181] Figure 6 shows a top view cell layout 602 of the static random access memory array 102 with two adjacent memory cells 104. In the present embodiment, Figure 6 shows cell-1 and cell-2 of group-1 (corresponding to memory cells 104a and 104b) of Figure 3 . Note that, Figure 6 Additional line segments A-H are shown cutting through various regions of the cell layout 602. The static random access memory array 102 at line segments A-H is referred to​​Figure 7A , 7B , 7C-1, 7C-2, 7D-1, 7D-2, 7E-1, 7E-2, 7F-1, 7F-2, 7G, and 7H are described.

[0182] Figure 7A A cross-sectional schematic view showing static random access memory array 102 cut along a line segment A of Figure 6 . This cross-sectional schematic view is referred to as cross-section A. Cross-section A is cut along the X direction across gate 108, which is used for both pull-down transistors and pull-up transistors (e.g., pull-up transistor PU1, pull-down transistor PD1, pull-down transistor PD3, and pull-up transistor PU3). As shown in cross-section A, static random access memory array 102 includes substrate 100. Substrate 100 can be a silicon (Si) substrate, or a substrate with other semiconductor materials (e.g., germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond). Substrate 100 can include N-type wells doped with N-type dopants for forming P-type transistor elements (e.g., pull-up transistor PU1 and pull-up transistor PU3), and P-type wells doped with P-type dopants for forming N-type transistor elements (e.g., pull-down transistor PD1 and pull-down transistor PD3). The N-type and P-type wells can have a depth in a range between about 50 nm to 300 nm.

[0183] Continuing to refer to Figure 7A , cross-section A shows that channel region 106a of active region 106 is protruding from substrate 100. Active region 106 can include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide (GaAs), gallium nitride (GaN), carbon (C), indium (In), or combinations thereof. Active region 106 (including channel region 106a) is separated from each other by isolation structure 101. Isolation structure 101 provides isolation between adjacent fin active regions 106, and can be a shallow trench isolation (STI) layer. Isolation structure 101 can include silicon oxide (SiO), silicon oxynitride (SiON), fluorine-doped silicon glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In this embodiment, isolation structure 101 is disposed on substrate 100, and each active region 106 is protruding from substrate 100 above isolation structure 101.

[0184] With continued reference to Figure 7A For a full wrap gate element, the channel region 106a can include a transistor channel 136 completely wrapped by the gate 108 (as shown). For a fin element, the channel region 106a can include a single fin channel wrapped on three sides by the gate 108 (not shown). The gate 108 includes a metal gate portion that wraps a gate dielectric layer 109, which in turn wraps the channel region 106a. The gate dielectric layer 109 can include a high-k dielectric material, such as a material having a dielectric constant greater than that of silicon oxide (~3.9). The high-k dielectric material can include a metal oxide, such as hafnium oxide (Hf02), zirconium oxide (Zr02), aluminum oxide (AI2O3), or combinations thereof. In one embodiment, the metal gate portion of the gate 108 can include different metal materials to wrap the transistor channels 136 of P-type transistor elements (e.g., pull-up transistors PU1 and PU3) and N-type transistor elements (e.g., pull-down transistors PD1 and PD3).

[0185] With continued reference to Figure 7AThe gate cut dielectric lines 308 completely cut through the gates 108 at the cell edges (e.g., the first cell edges, the second cell edges, etc.). The gate cut dielectric lines 308 isolate the gates 108 between different individual memory cells 104. In some embodiments, the gate cut dielectric lines 308 further penetrate into the isolation structures 101, with the bottoms of the gate cut dielectric lines 308 buried in the isolation structures 101. The gate cut dielectric lines 308 can include a single dielectric layer or multiple dielectric layers, and the single dielectric layer or multiple dielectric layers can include silicon dioxide (Si02), silicon oxycarbide (SiOC), silicon oxynitride, silicon oxycarbonitride (SiOCN), carbon-containing oxides, nitrogen-containing oxides, metal oxide dielectrics, hafnium oxide, tantalum oxide (Ta02), titanium oxide (Ti02), zirconium oxide, aluminum oxide, yttrium oxide (Y203), or combinations thereof. In one embodiment, the gate cut dielectric lines 308 and the isolation structures 101 include different dielectric materials (e.g., the gate cut dielectric lines 308 include silicon oxynitride, while the isolation structures 101 include silicon oxide). In the illustrated embodiment, the top surfaces of the gate cut dielectric lines 308 and the gates 108 are substantially coplanar after a planarization process. As shown, an interlayer dielectric (ILD) layer 130 can be disposed on the top surfaces of the gate cut dielectric lines 308 and the gates 108. The interlayer dielectric layer 130 can include a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, tetra ethyl orthosilicate (TEOS) formed oxides, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, other suitable dielectric materials, or combinations thereof.

[0186] Figure 7B The static random access memory array 102 is shown along Figure 6A cross-sectional view of a line segment B cut into the static random access memory array 102. This cross-sectional view is referred to as cross-section B. Cross-section B is similar to cross-section A, except that cross-section B is cut along the X direction across the gate 108 of pass-gate transistors (e.g., pass-gate transistor PG1 and pass-gate transistor PG3). In cross-section B, the gate 108 includes a metal gate portion that encloses the transistor channel 136, and a dielectric gate 208 adjacent to the metal gate portion. The metal gate portion can be referred to simply as the metal gate. As shown, the dielectric gate 208 is sandwiched between the gate cut dielectric line 308 and the side surface of the metal gate. The dielectric gate 208 can directly contact the gate cut dielectric line 308 and the side surface of the metal gate. The top surface of the dielectric gate 208 can be substantially coplanar with the top surface of the gate cut dielectric line 308 and the metal gate portion of the gate 108.

[0187] Continuing to refer to Figure 7B , and in contrast to Figure 7A , the dielectric gate 208 completely passes through the channel region 106a of the pull-up transistor (e.g., pull-up transistor PU1 and pull-up transistor PU3). In fact, the dielectric gate 208 replaces the individual channel regions 106a and acts as an active region isolation along the Y direction (refer to Figure 6 ). The dielectric gate 208 thus forms separate active regions 106 of the pull-up transistors of different memory cells 104. In one embodiment, the dielectric gate 208 completely passes through the isolation structure 101 to sit on the top surface of the substrate 100. As such, the bottom surface of the dielectric gate 208 can be substantially coplanar with the bottom surface of the isolation structure 101. As shown, the bottom surface of the dielectric gate 208 can be below the bottom surface of the gate cut dielectric line 308, which can be lower than the bottom surface of the metal gate of the gate 108. In one embodiment, the dielectric gate 208 has a vertical height in a range between about 60 nm and 300 nm. In one embodiment, the dielectric gate 208 can include silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, silicon nitride, carbon-containing oxides, nitrogen-containing oxides, air gaps, or combinations thereof. In one embodiment, the dielectric gate 208 and the gate cut dielectric line 308 include different dielectric materials (e.g., the dielectric gate 208 includes silicon oxide, while the gate cut dielectric line 308 includes silicon oxynitride).

[0188] Figure 7C-1 A cross-sectional view of a line segment B cut into the static random access memory array 102. This cross-sectional view is referred to as cross-section B. Cross-section B is similar to cross-section A, except that cross-section B is cut along the X direction across the gate 108 of pass-gate transistors (e.g., pass-gate transistor PG1 and pass-gate transistor PG3). In cross-section B, the gate 108 includes a metal gate portion that encloses the transistor channel 136, and a dielectric gate 208 adjacent to the metal gate portion. The metal gate portion can be referred to simply as the metal gate. As shown, the dielectric gate 208 is sandwiched between the gate cut dielectric line 308 and the side surface of the metal gate. The dielectric gate 208 can directly contact the gate cut dielectric line 308 and the side surface of the metal gate. The top surface of the dielectric gate 208 can be substantially coplanar with the top surface of the gate cut dielectric line 308 and the metal gate portion of the gate 108. Figure 6FIG. 3 illustrates a cross-sectional view of a portion of the static random access memory array 102 along the line C-C. The cross-sectional view is taken along the X direction across the source / drain contact 112. The cross-sectional view is referred to as cross-section C-l. The cross-section C-l is taken along the X direction across the source / drain contact 112. The cross-section C-l shows the source / drain region 106b of the active region 106 that protrudes from the substrate 100. The source / drain region 106b includes an epitaxial component, which is represented in the figures as P-type epitaxy and / or N-type epitaxy. The epitaxial component can be formed to have an extended profile to form a widened shape on top of the source / drain region 106b. The epitaxial component can be N-type epitaxy doped with N-type dopants and / or P-type epitaxy doped with P-type dopants. In some embodiments, for N-type transistors, the epitaxial component includes silicon and can be doped with carbon, phosphorous, arsenic, other N-type dopants, or combinations thereof (e.g., form a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial source / drain component). In some embodiments, for P-type transistors, the epitaxial component includes silicon germanium or germanium and can be doped with boron, other P-type dopants, or combinations thereof (e.g., form a Si:Ge:B epitaxial source / drain component).

[0189] With continued reference to Figure 7C-1 , the source / drain contact 112 sits on the epitaxial component of the source / drain region 106b. In this cross-sectional view, the source / drain contact 112 extends in the X direction between the gate cut dielectric lines 308 and sits on adjacent epitaxial components of opposite types (e.g., N-type epitaxy and P-type epitaxy). Note that in this embodiment, the gate cut dielectric lines 308 are disposed directly between adjacent source / drain contacts 112 of different memory cells 104. The gate cut dielectric lines 308 provide isolation between the epitaxial components (e.g., N-type epitaxy or P-type epitaxy) of different memory cells 104, thereby avoiding any unwanted epitaxial merging or bridging. Although not shown, due to the gate cut dielectric lines 308, the epitaxial components (e.g., N-type epitaxy or P-type epitaxy) can be grown to extend to directly contact and touch the side surfaces of the gate cut dielectric lines 308. As shown, the top surface of the source / drain contact 112 is above the top surface of the gate cut dielectric lines 308, which is above the top surface of the epitaxial component. An interlayer dielectric layer 130 (as previously described) can be disposed on the epitaxial component of the source / drain region 106b, the source / drain contact 112, and the gate cut dielectric lines 308, which can cover the epitaxial component of the source / drain region 106b, the source / drain contact 112, and the gate cut dielectric lines 308.

[0190] Figure 7C-2 FIG. 4 illustrates a cross-sectional view of a portion of the static random access memory array 102 along the line D-D. The cross-sectional view is taken along the Y direction across the source / drain contact 112. The cross-sectional view is referred to as cross-section D-l. The cross-section D-l is taken along the Y direction across the source / drain contact 112. The cross-section D-l shows the source / drain region 106b of the active region 106 that protrudes from the substrate 100. The source / drain region 106b includes an epitaxial component, which is represented in the figures as P-type epitaxy and / or N-type epitaxy. The epitaxial component can be formed to have an extended profile to form a widened shape on top of the source / drain region 106b. The epitaxial component can be N-type epitaxy doped with N-type dopants and / or P-type epitaxy doped with P-type dopants. In some embodiments, for N-type transistors, the epitaxial component includes silicon and can be doped with carbon, phosphorous, arsenic, other N-type dopants, or combinations thereof (e.g., form a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial source / drain component). In some embodiments, for P-type transistors, the epitaxial component includes silicon germanium or germanium and can be doped with boron, other P-type dopants, or combinations thereof (e.g., form a Si:Ge:B epitaxial source / drain component). Figure 6A cross-sectional view cut by line segment C is shown. This cross-sectional view is referred to as section C-2. Section C-2 is the same as section C-1, except that the source / drain region 106b may include a source / drain bottom dielectric layer 142. The source / drain bottom dielectric layer 142 is disposed under the epitaxial component of the source / drain region 106b, and the source / drain bottom dielectric layer 142 provides isolation between the doped epitaxial component and the substrate 100 (or its well regions, such as N-type and P-type wells). Such isolation in the epitaxial component improves transistor operation by isolating a first type of dopant in the well region from a second type of dopant, wherein the first type of dopant and the second type of dopant are dopant of opposite types.

[0191] Figure 7D-1 The static random access memory array 102 is shown along... Figure 6 A cross-sectional view cut by line segment D is shown. This cross-sectional view is referred to as section D-1. Section D-1 is similar to cross section C-1 and also cuts across the source / drain contact 112 along the X direction. The difference is that in section D-1, the source / drain contact 112 extends across the gate dicing dielectric 308 (e.g., cell edge) in the X direction and sits on adjacent epitaxial components of the same type (e.g., N-type and N-type epitaxial, or P-type and P-type epitaxial). The source / drain contact 112 also sits on the gate dicing dielectric 308. It should be noted that in this embodiment, the gate dicing dielectric 308 is directly disposed below the source / drain contact 112 between adjacent epitaxial components of different memory cells 104. As shown, the top surface of the gate dicing dielectric 308 may be located below the top surface of the epitaxial component. An interlayer dielectric layer 130 (as previously described) may be disposed on the epitaxial components of the source / drain region 106b, the source / drain contact 112, and the gate diced dielectric 308, which may cover the epitaxial components of the source / drain region 106b, the source / drain contact 112, and the gate diced dielectric 308.

[0192] Figure 7D-2 The static random access memory array 102 is shown along... Figure 6 A cross-sectional view cut by line segment D is shown. This cross-sectional view is referred to as section D-2. Section D-2 is the same as section D-1, except that the source / drain region 106b may include a source / drain bottom dielectric layer 142. The source / drain bottom dielectric layer 142 is disposed under the epitaxial component of the source / drain region 106b, and the source / drain bottom dielectric layer 142 provides isolation between the doped epitaxial component and the substrate 100 (or its well regions, such as N-type and P-type wells). Such isolation in the epitaxial component improves transistor operation by isolating a first type of dopant in the well region from a second type of dopant, wherein the first type of dopant and the second type of dopant are dopant of opposite types.

[0193] Figure 7E-1The static random access memory array 102 is shown along... Figure 6 A cross-sectional view cut by line segment E is shown. This cross-sectional view is referred to as section E-1. Section E-1 cuts across the N-type active region 106-1 along the Y direction, whereby pull-down transistors and gate transistors (e.g., gate transistor PG1, pull-down transistor PD1, pull-down transistor PD2, and gate transistor PG2) are formed on the P-type well of the substrate 100. Section E-1 shows the Y1 pitch corresponding to the cell height of the memory cell 104. The Y1 pitch covers the continuous N-type active region 106-1 extending in the Y direction. The N-type active region 106-1 includes a channel region 106a and a source / drain region 106b adjacent to the channel region 106a. The Y1 pitch further covers four gates 108 (or specifically, metal gate portions of gates 108) on the channel region 106a. Y1-pitch further encompasses the N-type epitaxial layer as part of (or disposed on) the source / drain region 106b. In the illustrated embodiment, each gate 108 is a metal gate, and the metal gate includes a gate stack having a gate dielectric layer 109 surrounding the transistor channel 136 and a gate electrode surrounding the gate dielectric layer 109. The metal gate has a top located above the topmost transistor channel 136 and a bottom located below the topmost transistor channel 136. The top is surrounded by gate spacers 111, and the bottom is surrounded by inner spacers 113. The inner spacers 113 are vertically disposed between the transistor channels 136. Source / drain contacts 112 are disposed on the epitaxial portion of the source / drain region 106b (e.g., the N-type epitaxial layer) and may be adjacent to the gate spacers 111. In one embodiment, silicide portions 316 are vertically disposed between the epitaxial portions of the source / drain contacts 112 to improve surface contact. In one embodiment, a gate cap 180 may be disposed on the gate 108 and the gate spacer 111. The top surface of the gate cap 180 may be substantially coplanar with the top surface of the source / drain contact 112. The gate spacer 111, the inner spacer 113, and the gate cap 180 may be formed of any suitable dielectric material. An interlayer dielectric layer 130 (as previously described) may be disposed on the source / drain contact 112 and the gate cap 180.

[0194] Figure 7E-2 The static random access memory array 102 is shown along... Figure 6A cross-sectional view cut by line segment E is shown. This cross-sectional view is referred to as section E-2. Section E-2 is the same as section E-1, except that the source / drain region 106b may include a source / drain bottom dielectric layer 142. The source / drain bottom dielectric layer 142 is disposed under the epitaxial component of the source / drain region 106b, and the source / drain bottom dielectric layer 142 provides isolation between the doped epitaxial component and the substrate 100 (or its well regions, such as N-type and P-type wells). Such isolation in the epitaxial component improves transistor operation by isolating a first type of dopant in the well region from a second type of dopant, wherein the first type of dopant and the second type of dopant are dopant of opposite types.

[0195] Figure 7F-1 The static random access memory array 102 is shown along... Figure 6 A cross-sectional view cut by line segment F is shown. This cross-sectional view is referred to as section F-1. Section F-1 is similar to section E-1, except that section F-1 cuts into the P-type active region 106-2 along the Y direction, and the P-type active region 106-2 forms pull-up transistors (e.g., pull-up transistors PU-1 and PU-2) on the N-type well of the substrate 100. Thus, a P-type epitaxial layer is formed in or above the source / drain region 106b, instead of an N-type epitaxial layer. Furthermore, in section F-1, two dielectric gates 208 pass through and replace the channel region 106a, which is adjacent to the channel region 106a of pull-up transistors PU-1 and PU-2. These dielectric gates 208 enclose the gates 108 (e.g., metal gates) of pull-up transistors PU-1 and PU-2. It should be noted that the dielectric gates 208 and the gates 108 (e.g., metal gates) may have substantially the same width along the Y direction. In the illustrated embodiment, a gate cap 180 may be provided on the top surface of the dielectric gate 208.

[0196] Figure 7F-2 The static random access memory array 102 is shown along... Figure 6 A cross-sectional view cut by line segment F is shown. This cross-sectional view is referred to as section F-2. Section F-2 is the same as section F-1, except that the source / drain region 106b may include a source / drain bottom dielectric layer 142. The source / drain bottom dielectric layer 142 is disposed under the epitaxial component of the source / drain region 106b, and the source / drain bottom dielectric layer 142 provides isolation between the doped epitaxial component and the substrate 100 (or its well regions, such as N-type and P-type wells). Such isolation in the epitaxial component improves transistor operation by isolating a first type of dopant in the well region from a second type of dopant, wherein the first type of dopant and the second type of dopant are dopant of opposite types.

[0197] Figure 7G The static random access memory array 102 is shown along... Figure 6A cross-sectional view of line segment G is shown. This cross-sectional view is referred to as section G. Section G cuts across the gate dicing dielectric 308 along the Y direction, and the gate dicing dielectric 308 cuts through the gate 108 to separate the pull-down transistor and the on-gate transistor in the adjacent memory cell 104. In this cross-sectional view, an isolation structure 101 is provided on the substrate 100, the gate dicing dielectric 308 is provided on the isolation structure 101, and source / drain contacts 112 are provided on the gate dicing dielectric 308. The source / drain contacts 112 may partially penetrate into the gate dicing dielectric 308. Both of the source / drain contacts 112 may be located on the cell edges of the static random access memory array 102, and one of the source / drain contacts 112 may be located between the cell edges of the static random access memory array 102.

[0198] Figure 7H The static random access memory array 102 is shown along... Figure 6 A cross-sectional view of line segment H is shown. This cross-sectional view is referred to as section H. Section H cuts along the Y direction across another gate cleavage dielectric 308, which cuts through the gate 108 to isolate the pull-up transistor in the adjacent memory cell 104. In this cross-sectional view, an isolation structure 101 is provided on the substrate 100, the gate cleavage dielectric 308 is provided on the isolation structure 101, and source / drain contacts 112 are provided on the gate cleavage dielectric 308. The source / drain contacts 112 can partially penetrate into the gate cleavage dielectric 308 and are located between the cell edges of the static random access memory array 102.

[0199] Figure 8 According to another embodiment of the present invention, a top-view element layout 802 of a static random access memory array 102 having two adjacent memory cells 104 is shown. Figure 8 Similar to Figure 6 ,and Figure 8 Similarly shown Figure 3 Cells 1 and 2 of group-1 (corresponding to memory cells 104a and 104b). It should be noted that... Figure 8 Show line segments I and J, which correspond to respectively... Figure 6 Line segments B and H. Static random access memory array 102 for line segments I and J (refer to...) Figure 8I and Figure 8J describe.

[0200] Figure 8I The static random access memory array 102 is shown along... Figure 8 A schematic diagram of a cross-section cut by line segment I. This schematic diagram is called section I. Figure 8I Similar to Figure 7BFor simplicity, similar components will not be described again here. The difference lies in that the dielectric gate 208 (or a portion thereof) may be disposed on top of the adjacent gate dicing dielectric wire 308. In this embodiment, the dielectric gate 208 may be formed after the gate dicing dielectric wire 308 is formed. When the dielectric gate 208 is formed, the top of the individual gate dicing dielectric wire 308 is partially etched, such that the dielectric gate 208 is formed on top of the gate dicing dielectric wire 308.

[0201] Figure 8J The static random access memory array 102 is shown along... Figure 8 A schematic diagram of a cross-section cut by line segment J. This schematic diagram is called section J. Figure 8J Similar to Figure 7H For the sake of simplicity, similar components will not be described again here. The difference is that the dielectric gate 208 (or a portion thereof) may be surrounded by gate-cut dielectric wires 308.

[0202] Figures 9-12 According to an additional embodiment of the present invention, a corresponding embodiment is shown. Figure 2 The circuit diagram shows the top-view component layout of the static random access memory array 102.

[0203] Reference Figure 9 The component layout 902 is similar to Figure 3 In component layout 302, except that the transistors in cells -3 and -4 of group -2 are rotated so that they are not mirror images of group -1 on the Y-axis (as in...). Figure 3 (in the middle). Conversely, compared to group-1, units-3 and-4 of group-2 are flipped 180° on the X-axis. As shown, in this configuration, memory unit 104a' corresponds to unit-3, while memory unit 104b' corresponds to unit-4; however, in Figure 3 In the configuration of component layout 302, memory cell 104b' corresponds to cell-3, and memory cell 104a' corresponds to cell-4.

[0204] Reference Figure 10 The component layout 1002 is similar to Figure 3The element layout 302 in FIG. 3B is similar to the element layout 302 in FIG. 3A, except that additional gate cut dielectric lines 308 are located between pass-gate transistors (e.g., pass-gate transistor PG1 and pass-gate transistor PG2) and the dielectric gate 208. These additional gate cut dielectric lines 308 do not extend continuously across the memory cell 104 along the Y direction (e.g., the additional gate cut dielectric lines 308 do not cut through the pull-down transistor and pull-up transistor gates 108). These additional gate cut dielectric lines 308 help to prevent diffusion of metal particles in the gates 108 of the pass-gate transistors (e.g., pass-gate transistor PG1 and pass-gate transistor PG2) into the dielectric gate 208. Such diffusion can cause unwanted coupling between the diffused metal particles and surrounding components. In this embodiment, the gate cut dielectric lines 308 and the additional gate cut dielectric lines 308 are formed after the dielectric gate 208 is formed.

[0205] Referring to FIG. 3C, Figure 11 the element layout 1102 further illustrates the gate vias 116, the source / drain vias 120, and the first metal lines Ml on the element layout 1002 in FIG. 3B. The element layout 1102 is similar to the element layout 502a previously described in FIG. 3A, except that some or all of the memory cells 104 (e.g., cell-2 and cell-4) can have two local interconnect lines LIM1 flip positions in an embodiment due to the additional gate cut dielectric lines 308 when compared to the element layout 502a in FIG. 3A. Figure 10 Figure 5A Figure 5A

[0206] Referring to FIG. 3D, Figure 12 the element layout 1202 corresponds to the element layout 1102 in FIG. 3C. Figure 11 Figure 12 Only the first metal lines Ml of FIG. 3D are shown, and the components disposed thereunder are filtered out for illustration purposes. Figure 11 The element layout 1202 further illustrates first vias Vl sitting on the first metal lines Ml, second metal lines M2 sitting on the first vias Vl, second vias V2 sitting on the second metal lines M2, and third metal lines M3 sitting on the second vias V2. Figure 12 The element layout 1202 includes similar features as the element layout 1102 in FIG. 3C, and similar components will not be repeated here for brevity. Figure 12 Figure 5B

[0207] Figure 13 ​​​​​​is a method 1300 of forming a static random access memory array structure (e.g., static random access memory array 102) with a gate terminal dielectric line (e.g., gate cut dielectric line 308), according to an embodiment of the present inventive concept. In operation 1302, method 1300 forms an active region (e.g., active region 106) on a substrate (e.g., substrate 100), the active region extending in a lengthwise direction along a first direction (e.g., Y direction). In operation 1304, method 1300 forms a dummy gate (not shown) on a channel region (e.g., channel region 106a) of the active region, the dummy gate extending in a lengthwise direction along a second direction (e.g., X direction) perpendicular to the first direction. The dummy gate can include polysilicon, amorphous silicon, or microcrystalline silicon. In operation 1306, method 1300 forms source / drain epitaxial components (e.g., N-type epitaxy and P-type epitaxy) in a source / drain region (e.g., source / drain region 106b) of the active region.

[0208] With continued reference to Figure 13 When forming the gate structure (e.g., gate 108) and the gate terminal dielectric line (e.g., gate cut dielectric line 308), method 1300 can include two separate paths.

[0209] In a first path, method 1300 replaces a first portion of the dummy gate with a metal gate (e.g., gate portion of a non-dielectric gate) and replaces a second portion of the dummy gate with a dielectric gate (e.g., dielectric gate 208) in operation 1308a-1. In one embodiment, the metal gate portion is formed first by a first patterning process, and then the dielectric gate portion is formed by a second patterning process. In another embodiment, the dielectric gate portion is formed first by a first patterning process, and then the metal gate portion is formed by a second patterning process. Thereafter, method 1300 forms the gate terminal dielectric line (e.g., gate cut dielectric line 308) through the metal gate and the dielectric gate in operation 1308a-2 along the first direction. After a planarization process, the resulting gate structure can be similar to Figure 7B shown.

[0210] In a second path, method 1300 replaces the dummy gate with a metal gate in operation 1308b-1. Thereafter, method 1300 forms the gate terminal dielectric line (e.g., gate cut dielectric line 308) through the metal gate in operation 1308b-2 along the first direction. Thereafter, method 1300 forms the dielectric gate (e.g., dielectric gate 208) to replace a portion of the metal gate in operation 1308b-3. After a planarization process, the resulting gate structure can be similar to Figure 8I shown.

[0211] With continued reference to Figure 13After forming various gate components (e.g., metal gates, dielectric gates, and gate-end dielectric lines), the method 1300 forms source / drain contacts (e.g., source / drain contacts 112) on the source / drain epitaxial components in operation 1310. In operation 1312, the method 1300 forms first metal lines (e.g., first metal lines Ml) on the source / drain contacts and the metal gates, the length of the first metal lines extending along a first direction. In operation 1314, the method 1300 forms second metal lines (e.g., second metal lines M2) on the first metal lines, the length of the second metal lines extending along a second direction and including word lines connected to the metal gates of pass-gate transistors (e.g., pass-gate transistors PG1 and PG2). In operation 1316, the method 1300 forms third metal lines (e.g., third metal lines M3) on the second metal lines, the length of the third metal lines extending along the first direction and including bit lines or bit line strips connected to the epitaxial components of the pass-gate transistors (e.g., pass-gate transistors PG1 and PG2).

[0212] While not limited, the present disclosure provides advantages for memory cell structures. One example advantage is the inclusion of gate-end dielectric lines to facilitate uniform isolation between memory cells and to allow the formation of source / drain components up to the gate-end dielectric lines. Another example advantage is the inclusion of dielectric gates to facilitate uniform isolation between memory cells for pull-up transistors. Another example advantage is the sharing of bit lines and bit line strips across two memory cells and moving these bit lines to higher metal layers for better metal spacing and distribution.

[0213] One aspect of the present disclosure relates to a memory structure. The memory structure includes: a plurality of memory cells, each memory cell including two active regions and four gate structures, the length of the active regions extending along a first direction, the length of the gate structures extending along a second direction, the second direction being perpendicular to the first direction, each gate structure extending across a plurality of pass regions of the active regions; and a pair of gate-cut dielectric components at a plurality of cell edges between each memory cell, the length of the gate-cut dielectric components extending along the first direction, each gate-cut dielectric component contacting each of the four gate structures in each memory cell.

[0214] In an embodiment, each memory cell is defined by a cell height along a first direction and a cell width along a second direction, and the cell height is greater than the cell width. In an embodiment, the cell height is substantially equal to four times a spacing between respective centerlines of two adjacent gate structures along the first direction, and the cell width is a spacing between respective centerlines of two adjacent gate cut dielectric features along the second direction. In an embodiment, each memory cell includes two pull-down transistors and two pass-gate transistors formed on a first active region of two active regions, and two pull-up transistors formed on a second active region of the two active regions. In an embodiment, a first memory cell and a second memory cell of the memory cells are adjacent to each other and share a bitline contact and a bitline strip contact, the bitline contact extending lengthwise over and across one of the gate cut dielectric features to land on source / drain components of a plurality of first pass-gate transistors in the first memory cell and the second memory cell, and the bitline strip contact extending lengthwise across the gate cut dielectric features to land on source / drain components of a plurality of second pass-gate transistors in the first memory cell and the second memory cell. In an embodiment, in each memory cell: two of the four gate structures include dielectric gates extending across a plurality of channel regions of the first active region of the two active regions, the dielectric gates cut through the first active region along the second direction and directly abut one of the gate cut dielectric features, the dielectric gates directly adjacent to the plurality of pull-up transistors formed on the first active region along the first direction. In an embodiment, in each memory cell: the gate cut dielectric feature, the dielectric gates, and the plurality of metal gates of the four gate structures are each formed on an isolation structure on a substrate, the gate cut dielectric feature and the dielectric gates penetrating into the isolation structure, and the dielectric gates penetrating into the isolation structure deeper than the gate cut dielectric feature penetrating into the isolation structure. In an embodiment, the memory structure further includes: a plurality of bitline metals electrically connected to source / drain components of the plurality of pass-gate transistors in the memory cells, in each memory cell, the pass-gate transistors formed on one of the two active regions; and a plurality of wordline metals electrically connected to gates of the pass-gate transistors in the memory cells. The bitline metals are a plurality of global bitlines extending lengthwise continuously across a column of the memory cells along the first direction, and the wordline metals are a plurality of global wordlines extending lengthwise continuously across a row of the memory cells along the second direction, the bitline metals disposed in a first metal layer and the wordline metals disposed in a second metal layer, and the first metal layer is above the second metal layer. In an embodiment, in each memory cell, the plurality of source / drain components formed on the two active regions include epitaxial components directly contacting the gate cut dielectric feature. In an embodiment, the gate cut dielectric feature and the gate structures substantially have coplanar top surfaces.In one embodiment, the memory structure further comprises: a first metal layer having a plurality of first metal lines, a length direction of the first metal layer extending along a first direction, the first metal lines comprising a plurality of local interconnects electrically connecting together a plurality of gates of a plurality of different transistors in a memory cell, electrically connecting together a plurality of source / drain components of a plurality of different transistors in a memory cell, or electrically connecting together a plurality of gates and a plurality of source / drain components of a plurality of different transistors in a memory cell; a second metal layer having a plurality of second metal lines, a length direction of the second metal layer extending along a second direction, the second metal lines comprising a plurality of word line metals electrically connecting together a plurality of gates of a plurality of different pass-gate transistors in a plurality of different memory cells; and a third metal layer having a plurality of third metal lines, a length direction of the third metal layer extending along the first direction, the third metal lines comprising a plurality of bit line metals and a plurality of bit line bar metals electrically connecting together a plurality of sources of a plurality of different pass-gate transistors in a plurality of different memory cells.

[0215] Another aspect of the present disclosure relates to a memory structure. The memory structure comprises: a first memory cell spanning between a first gate cut dielectric line and a second gate cut dielectric line, a length direction of the first gate cut dielectric line and the second gate cut dielectric line extending along a first direction; and a second memory cell spanning between the second gate cut dielectric line and a third gate cut dielectric line, a length direction of the third gate cut dielectric line extending along the first direction. The first memory cell comprises: a first active region and a second active region on a substrate, a length direction of the first active region and the second active region extending along the first direction; and a plurality of first gate structures on a plurality of channel regions of the first active region and the second active region, a length direction of the first gate structures extending along a second direction, the second direction perpendicular to the first direction. The second memory cell comprises: a third active region and a fourth active region on the substrate, a length direction of the third active region and the fourth active region extending along the first direction; and a plurality of second gate structures on a plurality of channel regions of the third active region and the fourth active region, a length direction of the second gate structures extending along the second direction, wherein the second gate cut dielectric line directly contacts side surfaces of the first gate structures and the second gate structures.

[0216] In one embodiment, the first active region and the first gate structure form a first pass-gate transistor, a first pull-down transistor, a second pull-down transistor, and a second pass-gate transistor, the second active region and the first gate structure form a first pull-up transistor and a second pull-up transistor, the third active region and the second gate structure form a third pass-gate transistor, a third pull-down transistor, a fourth pull-down transistor, and a fourth pass-gate transistor, and the fourth active region and the second gate structure form a third pull-up transistor and a fourth pull-up transistor. In one embodiment, the memory structure further comprises a plurality of source / drain contacts on the plurality of source / drain regions of the first, second, third, and fourth active regions. The source / drain contacts comprise a bit line contact on a source region of the first and third pass-gate transistors, and a bit line stripe contact on a source region of the second and fourth pass-gate transistors, the bit line contact and the bit line stripe contact being on a top surface of the second gate cut dielectric line. In one embodiment, the first gate structure comprises a plurality of first dielectric gate portions and a plurality of first metal gate portions, wherein the first dielectric gate portions cut through the second active region to contact the first gate cut dielectric line, wherein the first and second pull-up transistors are sandwiched between the first dielectric gate portions, and the second gate structure comprises a plurality of second dielectric gate portions and a plurality of second metal gate portions, wherein the second dielectric gate portions cut through the fourth active region to contact the third gate cut dielectric line, wherein the third and fourth pull-up transistors are sandwiched between the second dielectric gate portions. In one embodiment, the memory structure further comprises a first gate cut component disposed between the first pass-gate transistor and one of the first dielectric gate portions, a second gate cut component disposed between the second pass-gate transistor and another of the first dielectric gate portions, a third gate cut component disposed between the third pass-gate transistor and one of the second dielectric gate portions, and a fourth gate cut component disposed between the fourth pass-gate transistor and another of the second dielectric gate portions.

[0217] In one embodiment, the memory structure further comprises a plurality of dummy gates on a plurality of channel regions of the plurality of active regions, the dummy gates having a length direction extending along a second direction perpendicular to the first direction, and a plurality of source / drain epitaxial components in a plurality of source / drain regions of the plurality of active regions. In one embodiment, the memory structure further comprises a plurality of metal gates replacing a plurality of first portions of the dummy gates, and a plurality of dielectric gates replacing a plurality of second portions of the dummy gates. In one embodiment, the memory structure further comprises a plurality of gate end dielectric lines cutting through the metal gates and the dielectric gates along the first direction. In one embodiment, the memory structure further comprises a plurality of source / drain contacts on the source / drain epitaxial components.

[0218] In one embodiment, replacing the first portion and the second portion of the dummy gate includes replacing the dummy gate with a plurality of metal gates, and forming a plurality of dielectric gates replacing a plurality of portions of the metal gates, wherein forming the gate-end dielectric line is performed after forming the dielectric gates. In one embodiment, the method of forming the memory structure further includes forming a plurality of gate cut features between the dielectric gates and the metal gates. In one embodiment, replacing the first portion and the second portion of the dummy gate includes replacing the dummy gate with a plurality of metal gates, and forming a plurality of dielectric gates replacing a plurality of portions of the metal gates, wherein forming the gate-end dielectric line is performed before forming the dielectric gates.

[0219] The above outlines features of several embodiments to enable those skilled in the art to better understand the inventive concept of the embodiments. Those skilled in the art will understand that other processes and structures can be readily devised or modified based on the embodiments to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such, or other similar, structures do not depart from the spirit and scope of the embodiments, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the embodiments.

Claims

1. A memory structure, comprising: comprise: a plurality of memory cells, each of the plurality of memory cells comprising two active regions whose length direction extends along a first direction and four gate structures whose length direction extends along a second direction perpendicular to the first direction, each gate structure extending across channel regions of the two active regions; and a pair of gate cut dielectric members at cell edges between each memory cell and extending lengthwise along the first direction, each gate cut dielectric member contacting each of the four gate structures in each memory cell.

2. The memory structure of claim 1, wherein: each memory cell is defined by a cell height along the first direction and a cell width along the second direction, the cell height being greater than the cell width.

3. The memory structure of claim 2, wherein: the cell height is equal to four times a spacing between individual centerlines of two adjacent gate structures along the first direction, wherein the cell width is a spacing between individual centerlines of two adjacent gate cut dielectric members along the second direction.

4. The memory structure of claim 1, wherein: a first memory cell and a second memory cell of the plurality of memory cells are adjacent to each other and share a bit line contact and a bit line strip contact, wherein the bit line contact extends lengthwise over and across a gate cut dielectric member of the plurality of gate cut dielectric members to fall on source / drain components of first pass-gate transistors in the first memory cell and the second memory cell, wherein the bit line strip contact extends lengthwise across the gate cut dielectric member to fall on source / drain components of second pass-gate transistors in the first memory cell and the second memory cell.

5. The memory structure of claim 1, wherein: in each memory cell: two of the four gate structures comprise dielectric gates extending across channel regions of a first active region of the two active regions, wherein the dielectric gates cut through the first active region along the second direction and directly abut one of the gate cut dielectric members, wherein the dielectric gates directly adjoin pull-up transistors formed on the first active region along the first direction.

6. The memory structure of claim 5, wherein: in each memory cell: the gate cut dielectric members, the dielectric gates, and metal gates of the four gate structures are each formed on an isolation structure on a substrate, wherein the gate cut dielectric members and the dielectric gates penetrate the isolation structure, and the dielectric gates penetrate the isolation structure deeper than the gate cut dielectric members.

7. The memory structure of claim 1, wherein: In each memory cell, the plurality of source / drain components formed on the two active regions includes a plurality of epitaxial components directly contacting a plurality of gate cut dielectric components.

8. A memory structure, comprising: Comprises: a first memory cell spanning between a first gate cut dielectric line and a second gate cut dielectric line, the length direction of the first and second gate cut dielectric lines extending along a first direction; and a second memory cell spanning between the second gate cut dielectric line and a third gate cut dielectric line, the length direction of the third gate cut dielectric line extending along the first direction, wherein the first memory cell comprises: a first active region and a second active region on a substrate, the length direction of the first and second active regions extending along the first direction, and a plurality of first gate structures on channel regions of the first and second active regions, the length direction of the plurality of first gate structures extending along a second direction perpendicular to the first direction, wherein the second memory cell comprises: a third active region and a fourth active region on the substrate, the length direction of the third and fourth active regions extending along the first direction, and a plurality of second gate structures on channel regions of the third and fourth active regions, the length direction of the plurality of second gate structures extending along the second direction, wherein the second gate cut dielectric line directly contacts the side surfaces of the plurality of first and second gate structures.

9. The memory structure of claim 8, wherein: the first active region and the plurality of first gate structures form a first pass gate transistor, a first pull-down transistor, a second pull-down transistor, and a second pass gate transistor, wherein the second active region and the plurality of first gate structures form a first pull-up transistor and a second pull-up transistor, wherein the third active region and the plurality of second gate structures form a third pass gate transistor, a third pull-down transistor, a fourth pull-down transistor, and a fourth pass gate transistor, wherein the fourth active region and the plurality of second gate structures form a third pull-up transistor and a fourth pull-up transistor.

10. The memory structure of claim 9, wherein, Further comprises: a plurality of source / drain contacts on source / drain regions of the first, second, third, and fourth active regions, the plurality of source / drain contacts comprising: a bit line contact falling on a source region of the first and third pass gate transistors, and a bit line bar contact falling on a source region of the second and fourth pass gate transistors, wherein the bit line contact and the bit line bar contact fall on the top surface of the second gate cut dielectric line.

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