Electronic device

Abstract

The utility model relates to an electronic device. The disclosure relates to the formation of variable trench dimension regions, including a plurality of trenches extending in a strip-like manner in a top planar view. A larger trench accommodates both the source polycrystalline field plate contact and the polycrystalline gate region. All trenches are spaced apart from each other by a constant amount to maintain the expected field plate effect and avoid the impact on the breakdown voltage. To restore the larger pitch dimension thus produced, the grooves around the larger pitch dimension are formed to be smaller and decrease from the inner groove dimension to the outer groove dimension. The sum of the pitches of these cells will be equal to the sum of the pitches of the same number of standard cells. In this way, the impact on electrical performance and efficiency is limited or even avoided.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority benefit of Italian Patent Application No. 102023000025728, filed December 1, 2023, entitled “Dispositivo Elettronico con Porta a Trincea con Field Plate di Sorgente Sepolto, e Relativo Metodo di Fabbricazione,” which is incorporated herein by reference to the fullest extent permitted by law. TECHNICAL FIELD

[0003] The present disclosure relates to trench-gate electronic devices, in particular trench-gate power MOSFETs. BACKGROUND

[0004] Reference is made to Figure 1 where a power MOS transistor 1 according to the prior art is shown in lateral section (Fig. 1) and in plan view (Fig. 2). Figure 1 is a simplified view of a MOS transistor, in which elements not useful for understanding the present disclosure are not illustrated and described. Figure 1 is represented in a triaxial reference system, in which the three axes X, Y, Z are orthogonal to each other.

[0005] The power MOS transistor 1 comprises a semiconductor substrate 2 having a first side 2a and a second side 2b opposite each other along the direction of the axis Z and having a first conductivity type (N); a trench 3 in the semiconductor substrate 2 at the first side 2a; an oxide region 4 extending at the bottom and lateral walls of the trench 3; a conductive gate region 5a in the trench 3, wherein the oxide region 4 extends around the gate region 5a in such a way that the gate region 5a is electrically isolated from the semiconductor substrate 2 by the oxide region 4; a field plate 5b made of a conductive material such as N-doped polysilicon, located in the trench 3 and embedded within the oxide region 4 below the conductive gate region 5a and electrically insulated from the conductive gate region 5a by a portion of the oxide region 4. The embedded field plate 5b is formed in the trench 3 below the conductive gate region 5a in a known manner and serves to reduce the electric field in the semiconductor substrate 2 near the trench 3 and to reduce the parasitic capacitance. Since the field plate 5b is electrically isolated from the conductive gate region 5a, this structure is also referred to as "shielded gate" or "split gate". A top oxide region 28 also exists above the trench 3 and on the conductive gate region 5a. It is clear to the person skilled in the art that one or more further layers 9 can be present. The semiconductor substrate 2 accommodates first and second body regions 7 having a second conductivity type (P) laterally to the trench 3, facing the first side 2a of the semiconductor substrate 2 and adjacent to the opposite (in the direction of the axis X) lateral sides of the trench 3. First and second source regions 10 having the first conductivity type (N) extend within the first and second body regions 7, respectively, and face the first side 2a. A drain electrode 11 extends at the second side 2b. The source, gate and drain metal terminals are shown schematically in the figure.

[0006] During device turn-off operation, the rise of the drain voltage creates power dissipation as the drain current falls from its maximum value to approximately zero. Any reduction in the rise profile of this voltage will result in higher power dissipation and lower efficiency. The problem of slowing down the drain voltage rise during turn-off is the dynamic grounding of the polysilicon field plate. The grounding delay can cause a temporary BVdss (breakdown voltage drain to source) at low voltage, which in turn causes voltage rise clamping and current conduction until the entire polysilicon field plate is grounded.

[0007] The polysilicon field plate 5b is connected to the ground voltage by means of one or more contacts 12 (shown in the figure) coupled to the metal source terminal. The contacts 12 of the field plate 5b are formed by etching the semiconductor substrate 2 at the first side 2a until the field plate 5b is reached. In order to form these contacts 12, the conductive gate region 5a is locally interrupted to avoid gate leakage current (Igss) problems and to provide sufficient space for its field plate contacts. Figure 2

[0008] ​As known, in a top plan view on the XY plane, the gate regions 5a, the field plate 5b, the body region 7 and the source region 10 extend in strip-like fashion, for example with a main extension direction along the Y axis, as indicated in the diagram of Figure 1. Figure 2 The contacts 12 of the field plate 5b are formed on one side of the field plate strip (along the Y axis), while the contacts 14 of the conductive gate regions 5a are formed on the opposite side. This solution determines the polarization of the field plate 5b during the switching operation, which starts from one side of the field plate 5b strip (where the contacts 12 are actually present) and reaches, with a time delay, the opposite side of the field plate 5b strip (along the Y axis) (where the contacts 12 are not present). It can be understood that, as the dimension of the field plate 5b strip along the Y axis increases, the dynamic polarization of the field plate 5b can weaken. Under these conditions, the time delay for complete polarization becomes sensitive to the physical and geometric characteristics of the MOS transistor 1.

[0009] To minimize the dynamic polarization time of the field plate 5b, one solution (not necessarily prior art) that can be adopted is to reduce the resistivity of the field plate 5b as much as possible by suitably designing the N-type doping level of the polysilicon of the field plate 5b (i.e. increasing the doping level) and / or by increasing the dimension and depth of the trench 3, which in turn allows a larger and deeper polysilicon field plate 5b to be formed. However, the above possible solution is limited from the point of view of the manufacturing process, since the polysilicon doping cannot exceed the physical limits and the technical possibilities offered by the manufacturing tools used in the production plant, and is also limited from the point of view of the design / functionality, since a larger and deeper trench 3 has a negative impact on the technical performance and efficiency of the MOS transistor 1. SUMMARY

[0010] The present disclosure aims to provide an electronic device to overcome the shortcomings of the prior art.

[0011] According to one aspect of the disclosure, there is provided an electronic device comprising: a semiconductor body having a first side and a second side opposite each other along a first axis; a plurality of trenches extending from the first side towards the second side within the semiconductor body and terminating within the semiconductor body, each of the trenches having a second extension direction along a second axis parallel to a top side and orthogonal to the first axis, and a third extension direction along a third axis parallel to the top side and orthogonal to the first and second axes; a gate insulating region in each of the trenches, the gate insulating region covering a bottom and lateral walls of each of the trenches; a gate conductive region in each of the trenches on the gate insulating region, the gate conductive region being electrically insulated from the semiconductor body by the gate insulating region; a source field plate region in each of the trenches, the source field plate region being electrically insulated from the gate conductive region and the semiconductor body by the gate insulating region, wherein the electronic device further comprises: a protrusion of insulating material protruding from at least a first trench of the plurality of trenches, a through-hole extending through the protrusion towards the source field plate region to the source field plate region; a conductive contact within the through-hole electrically coupled to the source field plate region, wherein the first trench has a variable dimension along the third axis, including a first dimension corresponding to the through-hole and a second dimension at a distance from the through-hole along the second axis, the first dimension being higher than the second dimension; wherein at least a second trench of the plurality of trenches extending transversely to the first trench and directly facing the first trench has a respective variable dimension along the third axis, including a third dimension at a portion of the second trench facing the first trench having the first dimension and the second dimension at a portion of the second trench facing the first trench having the second dimension, the third dimension being lower than the second dimension; and wherein the first trench and the second trench are spaced apart from each other by a constant amount at the facing portions.

[0012] In one embodiment, the gate conductive region in the first trench extends to the outside or around the protrusion.

[0013] In one embodiment, the gate conductive region is electrically continuous along the second axis in each of the plurality of trenches.

[0014] In one embodiment, a respective protrusion of insulating material protrudes from the second trench, and the gate conductive region in the second trench extends outwardly and transversely to the respective protrusion.

[0015] In one embodiment, in the second trench, a respective via extends through a respective protrusion toward the source field plate region, to the source field plate region, and a respective conductive contact extends within the via, electrically coupled to the source field plate region; the second trench has the first dimension along the third axis corresponding to the respective via; the first trench has the third dimension at the portion of the first trench facing the portion of the second trench having the first dimension; and the first trench and the second trench are spaced apart from each other by a constant amount at the facing portions.

[0016] In one embodiment, in a top plan view parallel to the top side, the plurality of trenches extend in a strip-like manner, each trench of the plurality of trenches being spaced apart from an adjacent trench by a constant amount.

[0017] In one embodiment, adjacent trenches are spaced apart from each other by a constant amount for their entire extension along the second axis.

[0018] In one embodiment, the semiconductor body is configured to accommodate, during operation of the electronic device, a conductive channel located along the first axis between the first trench and the second trench.

[0019] In one embodiment, the semiconductor body has a first conductivity type, the electronic device further comprising: a body region extending at the first side between the first trench and the second trench, the body region having a second conductivity type opposite to the first conductivity type; and a source region in the body region.

[0020] In one embodiment, the conductive contact extending within the via is electrically insulated from the gate conductive region by a lateral wall of the protrusion.

[0021] In one embodiment, a further via extends through a protrusion in the first trench toward the source field plate region, to the source field plate region, and the via and the further via in the first trench are aligned with each other along the second axis.

[0022] In one embodiment, a drain terminal is located at a second side of the semiconductor body.

[0023] In one embodiment, the electronic device is of vertical conduction type. BRIEF DESCRIPTION OF DRAWINGS

[0024] For a better understanding of the present disclosure, and to show more clearly how it can be carried into effect, preferred embodiments thereof will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0025] Figure 1A cross-sectional view of a MOS transistor according to known technology is shown;

[0026] Figure 2 Shown in top view Figure 1 MOS transistor;

[0027] Figure 3 and Figure 4 The illustration shows a corresponding top plan view of the same part of an electronic device according to one aspect of the present disclosure;

[0028] Figure 5A The diagram shows... Figure 4 electronic devices along Figure 4 A cross-sectional view of the cutting line VV;

[0029] Figure 5B The diagram shows... Figure 5A A perspective view of an electronic device, in which Figure 5A The cross-section is visible;

[0030] Figure 6A The diagram shows... Figure 4 electronic devices along Figure 4 A cross-sectional view of the cutting line VI-VI;

[0031] Figure 6B The diagram shows... Figure 6A A perspective view of an electronic device, in which Figure 6A The cross-section is visible;

[0032] Figure 7 The illustration shows a method according to another embodiment with... Figure 3 Electronic devices of this disclosure with the same view;

[0033] Figure 8 The illustration shows a cross-sectional view of an electronic device according to another embodiment of the present disclosure; and

[0034] Figures 9A-9K The steps of a method for manufacturing the electronic device disclosed herein are illustrated. Detailed Implementation

[0035] Figure 3 by Figure 2 The same reference frame for axes X, Y, and Z shows a top plan view (on the XY plane) of a portion of an electronic device 20 according to an embodiment of the present disclosure. Figure 3 The shape of the groove 24 (as designed) is shown from the top.

[0036] Figure 4 by Figure 3 The same reference frame for the X, Y, and Z axes is shown. Figure 3the same top plan view (on the plane XY) of the same parts of the electronic device 20. In Figure 4 the gate conductive regions and the source field plate contacts are shown.

[0037] The electronic device 20 is for example a MOS transistor.

[0038] With reference to Figure 3 and Figure 4 , the electronic device 20 comprises a semiconductor body 22 (comprising a substrate and optionally one or more epitaxial layers, as needed) having a top side 22a opposite a bottom side 22b along the Z axis. The semiconductor body 22 has a first conductivity type, for example N-type doping. For example, the semiconductor material is silicon or SiC, the doping concentration being for example between 1-10 16 and 5-10 16 atoms / cm 3 .

[0039] At the top side 22a, a plurality of trenches 24 is formed, for example by etching the semiconductor body 22 by means of standard lithographic techniques or LASER drilling or also other techniques. The trenches extend from the top side 22a towards the bottom side 22b, terminating within the semiconductor body 22.

[0040] In one embodiment, each trench 24 accommodates two conductive gate regions 25a. Below the conductive gate regions 25a, a source field plate 25b extends, similar to the source field plate 5b of Figure 1 . An insulating fill region 26 (for example, SiO2or another electrically insulating material) extends in each trench 24 around the conductive gate regions 25a, thereby electrically insulating the conductive gate regions 25a from the semiconductor body 22 and the source field plate 25b. The source field plate 25b is embedded within the insulating fill region 26.

[0041] In some embodiments, an elongated element 29 (hereinafter also referred to as "protrusion" 29) of insulating material (for example, an oxide such as SiO2) is present above each source field plate 25b and vertically aligned with the source field plate 25b in each trench. The protrusion 29 can extend along the Z direction to a height above the height of the top side 22a and / or to a height above the maximum height of the conductive gate regions 25a (for example, see Figure 5A and Figure 6A ). However, in other embodiments, the protrusion 29 can extend along the Z direction to a height that is the same as or lower than the height of the top side 22a and / or lower than the maximum height of the conductive gate regions 25a (for example, see Figure 8 or Figures 9I-9J ).

[0042] In Figure 5A , Figure 5B , Figure 6A ,Figure 6B In the embodiment of Fig. 2, in each trench 24, the protrusion 29 physically and electrically separates two conductive gate regions 25a. As Figure 5A and Figure 5B better shown in Figs. 3 and 4, the protrusion 29 accommodates or comprises a contact opening 30 configured to provide local electrical access to the source field plate 25b. In particular, for enabling electrical contact, the source field plate 25b locally reaches the top side 22a, or even lies above the top side 22a at the area where the contact opening 30 is present. At least one opening 30 is formed in correspondence of each trench 24, which is surrounded by the protrusion 29, so that the source field plate 25 is exposed to be later contacted by a conductive (e.g. metallic) material. The contact opening 30 and the corresponding conductive contact (not shown) are electrically insulated from the conductive gate regions 25a by the lateral walls of the protrusion 29. The electrical continuity of the conductive gate regions 25a is in any case guaranteed transversally to the protrusion 29, as shown by the continuous gate strip 25a in Figure 4 . At the place where the contact 30 is to be formed, the trench 24 and the corresponding source field plate 25b are locally enlarged; moreover, the source field plate 25b is not recessed, and locally reaches a level above the level or surface 22 of the top side 22a, to facilitate the formation of the electrical contact. The conductive gate regions 25b are curved to externally follow / copy the shape of the locally enlarged source field plate 25b.

[0043] In Figure 3 and Figure 4 , only one trench 24 with a contact opening 30 is shown, and it is labeled with reference number 24' for facilitating the following description. If not specifically designated, the reference number 24 identifies any one or all of the trenches (and thus also the trench 24').

[0044] However, it is clear that each trench 24 accommodates at least one respective contact opening 30 in the corresponding insulating protrusion 29, to contact the corresponding source field plate 25b. It is also clear that, if the trench 24 does not accommodate a source field plate 25b, the contact openings 30 are not necessary, and thus they can not be formed.

[0045] According to an aspect of the present disclosure, the trench 24' has a variable X-axis dimension (in the top plan view) when considered along the Y-axis along which it extends. In the following, the term "width" is used to refer to the extension or dimension along the X-axis; the term "length" is used to refer to the extension or dimension along the Y-axis; and the term "depth" is used to refer to the extension or dimension along the Z-axis.

[0046] Reference is made to Figure 3, the trench 24' has a first width of a first value d1 and a second width of a second value d2. The first value d1 corresponds to the region of the trench 24' that accommodates the contact opening 30. In a top plan view, the contact opening 30 is entirely contained within the protrusion 29 of the trench 24', with the trench 24' having the second width value d2. Before and after the contact opening 30 (along the Y axis), the width of the trench 24' is limited to the first value d1. The protrusion 29 has a corresponding variable width, wider (along the X axis) when the trench has the dimension d2 and narrower (along the X axis) when the trench has the dimension d1.

[0047] In one example, as shown in Figure 3 and Figure 4 , the enlarged trench region having width d2 accommodates two contact openings 30, aligned along the same direction parallel to the Y axis and physically separated from each other. In this case, the enlarged trench region having width d2 has a length d4 higher than 2-d3. The two contact openings 30 are spaced apart from each other along the Y axis direction, for example by an amount d3 / 2.

[0048] In another example, not shown, there is only one contact opening 30; the contact opening 30 has a length of value d3; the length d4 of the enlarged trench region that accommodates such contact opening 30 is d4>d3.

[0049] The trenches 24 extend along respective main directions parallel to each other and also parallel to the Y axis. During use of the electronic device 20, the portion of the semiconductor body 22 between the two parallel trenches 24 accommodates the active region 32 in which the electrically conductive channel is formed.

[0050] In order not to limit the active region 32, the two trenches 24, located on opposite sides of the trench 24' along the X axis and directly facing the trench 24', in particular at the enlarged portion of the trench 24', are designed to have a variable width that mimics the variable width of the trench 24'. More particularly, the trenches 24 that directly face the trench 24', on both sides thereof (opposite each other along the X axis) are designed in such a way that the portion of the active region 32 comprised therebetween has a constant area / constant volume value. The distance between the directly facing trenches 24 is identified in the figures as d5.

[0051] In one example, the trenches 24 arranged transversely to the trench 24' (along the X direction) have a width equal to d1 when the trench 24' has the width d1 and a width equal to d1' when the trench 24 has the width d2. The value of d1' is equal to or lower than the value of d1. In one embodiment, the value of d1' is between 89% and 100% of the value of d1.

[0052] In one example embodiment:

[0053] d1 is in the range of 1.30-1.40µm, especially 1.36µm;

[0054] d1' is in the range of 1.25-1.40µm, especially 1.27µm;

[0055] d2 is in the range of 1.60-2µm, especially 1.70µm;

[0056] d3 is in the range of 1-2µm, especially 1.60µm;

[0057] d5 is in the range of 0.6-1µm, especially 0.74µm.

[0058] Figure 5A The diagram illustrates along Figure 3 and Figure 4 The cutting line VV shown Figure 3 and Figure 4 A cross-sectional view of the electronic device 20. It can be seen that the trench 24' is larger (along the X-axis) than the trench 24 extending transversely to the trench 24'. The protrusion 29 is correspondingly larger. Due to the corresponding "displacement" of the trenches 24 arranged transversely to the trench 24', the active region 32 between any two trenches 24 is not affected by the enlarged portion of the trench 24' in terms of the dimension along the X-axis. In the active region 32, transversely to each trench 24, 24', there exists a body region 40 and a source region 42, similar to... Figure 1 As shown and described with reference to it.

[0059] The drain terminal is located at the bottom side 22b of the semiconductor body 22.

[0060] Figure 5B It shows the section along the XZ plane. Figure 4 and Figure 5A A perspective view of an embodiment to see with Figure 5A The cross section corresponding to the cross section.

[0061] Figure 6A The diagram illustrates along Figure 3 and Figure 4 The cutting line VI-VI shown Figure 3 and Figure 4 A cross-sectional view of the electronic device 20. It can be seen that in this cross-section, the trench 24' has the same width as the trench 24 extending transversely to the trench 24'. The active region 32 between either of the trenches 24, 24' has a constant width over its entire extension along the Y-axis (in the top plan view).

[0062] In the active region 32, transversely to each trench 24, 24', there exists a main region 40 and a source region 42, similar to... Figure 1as shown in the figures and by reference to their description.

[0063] A drain terminal is present at the bottom side 22b of the semiconductor body 22.

[0064] Figure 6B A perspective view of an embodiment of the electronic device 20 is shown, taken along the plane XZ, to see the cross-section corresponding to the cross-section of the semiconductor body 22. Figure 4 and Figure 6A A perspective view of an embodiment of the electronic device 20 is shown, taken along the plane XZ, to see the cross-section corresponding to the cross-section of the semiconductor body 22. Figure 6A A perspective view of an embodiment of the electronic device 20 is shown, taken along the plane XZ, to see the cross-section corresponding to the cross-section of the semiconductor body 22.

[0065] Based on the representation of Figure 3 A perspective view of an embodiment of the electronic device 20 is shown, taken along the plane XZ, to see the cross-section corresponding to the cross-section of the semiconductor body 22. Figure 7 A further embodiment is shown, in which a contact is introduced in the active area 32 to electrically contact the body region 40 and the semiconductor body 22 underneath the body region 40, to reduce the negative impact of the parasitic body-drain diode. Such a contact is formed by forming a further contact opening 46 in the semiconductor body 22 between the trenches 24.

[0066] As mentioned above, in each trench 24, 24', there are two conductive gate regions 25a, which in a top plan view extend transversely to the source field plate 25b buried in the same trench 24, 24'. The two conductive gate regions 25a are physically separated from each other by the protrusion 29. However, in an alternative embodiment, the two conductive gate regions 25a in each trench can be physically and electrically connected to each other by a contact portion 25a' through the protrusion 29. More specifically, in the embodiment of Figure 8 the protrusion 29 is recessed (below the silicon surface) where no contact opening 30 is present. In the presence of a contact opening 30, the protrusion 29 protrudes from the top side 22a of the semiconductor body 22, resulting in a local bifurcation of the conductive gate region 25a, which locally assumes the shape of Figure 4 the embodiment of the electronic device 20. The bifurcated conductive gate region 25a comprises two gate strips coupled together on opposite sides along the Y-axis direction. The bifurcated conductive gate region 25a accommodates one or more contact openings 30 therebetween and between the coupled opposite sides. The protrusion 29 and the contact opening(s) 30 formed at the protrusion 29 form a connection island or connection point for electrically contacting the source field plate 25b without electrically contacting the conductive gate region 25a in the same trench 24, 24'.

[0067] Figures 9A-9K A method for manufacturing the electronic device 20 is illustrated, with specific reference to the embodiment of Figure 8 However, as will be immediately clear to the skilled person, the disclosed steps can be applied to manufacture the electronic device 20 according to any other disclosed embodiment.

[0068] In the embodiment of Figure 9AIn a first embodiment, a semiconductor substrate is provided on which an optional epitaxial layer is grown. The substrate and the epitaxial layer together form a semiconductor body 22. The substrate and the epitaxial layer are, for example, silicon with N-type doping.

[0069] Then, Figure 9B A trench 24 is formed by etching the semiconductor body 22 from the top side 22a. The etching is performed by known techniques, such as RIE (reactive ion etching) or DRIE (deep reactive ion etching). In the figures, the trench 24 has vertical sidewalls; depending on the process used to manufacture the trench, they can also have inclined sidewalls, such as truncated V-shaped or truncated pyramid-shaped in a side view. The teachings of the present disclosure are similarly applicable in the case of sidewalls of the trench 24 that are not entirely parallel to the Z-axis.

[0070] Then, Figure 9C The trench 24 is partially filled with an electrically insulating material, thereby forming an insulating fill region 26. If the semiconductor body 22 is made of silicon, this step is performed, for example, by growing or depositing silicon oxide (SiO2); another insulating material can be grown or deposited based on the material of the semiconductor body 22.

[0071] Then, Figure 9D A step of filling the trench 24 with an electrically conductive material is performed, thereby forming an electrically conductive region 52 in the trench 24 and on the semiconductor body 22. The electrically conductive material is, for example, N-doped polysilicon and completely fills the trench 24.

[0072] Then, Figure 9E A step of removing a selective portion of the electrically conductive region 52 above the top side 22a of the semiconductor body 22 is performed, thereby leaving the electrically conductive region 52 within the trench 24. This step can be performed with the aid of a CMP technique (chemical-mechanical polishing).

[0073] Then, Figure 9F A step of partially etching the electrically conductive region 52 within the trench 24 is performed. Thus, the electrically conductive region 52 is recessed in each trench 24 until the electrically conductive region 52 lies below or coplanar with the top side 22a.

[0074] Then, Figure 9G The insulating fill region 26 is partially etched in correspondence with the top side 22a, thereby forming a recess 54 in each trench. The etching is selective to the material of the insulating fill region 26 and leaves the material of the electrically conductive region 52 in the trench; the etching removes the insulating material until the electrically conductive region 52 protrudes from the insulating fill region 26.

[0075] Then, Figure 9H, an oxidation step is performed (e.g., the wafer is exposed to an O2 environment) to oxidize the portions of the conductive regions 52 that protrude from the insulative fill regions 26 in the trenches 24 and are thus not protected by the insulative fill regions 26. This oxidation step is self-limiting and forms a buried conductive region in the trenches 24. The buried conductive region is the previously discussed source field plate 25b. The upper portions of the conductive regions 52 that protrude from the insulative fill regions 26 form, after oxidation, the previously discussed elongated elements 29 ("protrusions" 29). In this embodiment, the protrusions 29 are located within the trenches 24 and do not actually protrude above the top side 22a; however, it is clear that the protrusions 29 can extend out of the trenches 24 (as in Figure 5A and Figure 6A ), so that, after oxidation, they actually protrude to some extent from the top side 22a.

[0076] Then, Figure 9I , a step of forming the conductive gate regions 25a is performed. The conductive gate regions 25a are formed by depositing a conductive material (e.g., n-doped polysilicon) in the recesses 54. Depending on the shape of the recesses 54 and the form of the protrusions 29, the conductive gate regions 25a of the respective embodiments of Figure 5A , Figure 6A , Figure 8 are formed.

[0077] Then, Figure 9J , between the trenches 24, the body and source regions 40, 42 are formed by respective known P-type and N-type dopant implantations.

[0078] Then, Figure 9K , the semiconductor body 22 is etched between the trenches 24 to form contact openings 58 to provide contact for front metal terminals that, in operation, connect the source and body regions to bias voltages.

[0079] Other steps can be performed to complete the manufacture of the electronic device 20, and since these steps are not part of the present disclosure, they are not described further.

[0080] The advantages of the present disclosure are clear from the present disclosure.

[0081] For example, the present disclosure enables higher speed for dynamic buried source field plate grounding, and it even becomes a more robust solution for larger dies for which grounding is an issue. Low power dissipation and higher efficiency during device turn-off operation are also achieved.

[0082] Finally, it is clear that modifications and variations of the present disclosure described and illustrated herein can be made without departing from the protection scope of the present disclosure as defined in the appended claims.

[0083] In particular, the present disclosure can be applied to any type of vertical conduction device with trench gates, such as but not limited to VDMOS transistors, or trench-based power MOSFET devices.

[0084] According to an aspect of the present disclosure, there is provided a method of manufacturing an electronic device, comprising: providing a semiconductor body having a first side and a second side opposite each other along a first axis; forming, within the semiconductor body, a plurality of trenches from the first side towards the second side and terminating within the semiconductor body, each of the trenches having a second extension direction along a second axis parallel to a top side and orthogonal to the first axis, and a third extension direction along a third axis parallel to the top side and orthogonal to the first and second axes; forming, in each of the trenches, a gate insulating region covering a bottom and lateral walls of each of the trenches; forming, in each of the trenches on the gate insulating region, a gate conductive region electrically insulated from the semiconductor body by the gate insulating region; forming, in each of the trenches, a source field plate region electrically insulated from the gate conductive region and the semiconductor body by the gate insulating region, wherein the method further comprises: forming, in at least a first trench among the plurality of trenches, a protrusion protruding above the top side along a first direction; forming a through-hole through the protrusion towards the source field plate region, reaching the source field plate region; forming, within the through-hole, a conductive contact electrically coupled to the source field plate region; wherein the first trench has a variable dimension along the third axis, including a first dimension corresponding to the through-hole and a second dimension at a distance from the through-hole along the second axis, the first dimension being higher than the second dimension; wherein at least a second trench among the plurality of trenches extending laterally to the first trench and directly facing the first trench has a respective variable dimension along the third axis, including a third dimension at a portion of the second trench facing the first trench having the first dimension and the second dimension at a portion of the second trench facing the first trench having the second dimension, the third dimension being lower than the second dimension; and the first and second trenches are spaced apart from each other by a constant amount at the facing portions.

Claims

1. An electronic device, characterized by comprising: Comprise: a semiconductor body having a first side and a second side opposite each other along a first axis; a plurality of trenches extending from the first side toward the second side within the semiconductor body and terminating within the semiconductor body, each of the trenches having a second extension direction along a second axis parallel to the top side and orthogonal to the first axis and a third extension direction along a third axis parallel to the top side and orthogonal to the first and second axes; a gate insulating region in each of the trenches, the gate insulating region covering a bottom and lateral walls of each of the trenches; a gate conductive region in each of the trenches on the gate insulating region, the gate conductive region being electrically insulated from the semiconductor body by the gate insulating region; a source field plate region in each of the trenches, the source field plate region being electrically insulated from the gate conductive region and the semiconductor body by the gate insulating region, wherein the electronic device further comprises: a protrusion of insulating material, the protrusion protruding from at least a first trench of the plurality of trenches, a through-hole extending through the protrusion toward the source field plate region to the source field plate region; a conductive contact within the through-hole electrically coupled to the source field plate region, wherein the first trench has a variable dimension along the third axis, including a first dimension corresponding to the through-hole and a second dimension at a distance from the through-hole along the second axis, the first dimension being higher than the second dimension; wherein at least a second trench of the plurality of trenches extending transversely to the first trench and directly facing the first trench has a respective variable dimension along the third axis, including a third dimension at a portion of the second trench facing the first trench having the first dimension and the second dimension at a portion of the second trench facing the first trench having the second dimension, the third dimension being lower than the second dimension; and wherein the first trench and the second trench are spaced apart from each other by a constant amount at the facing portions. 2.The electronic device of claim 1, wherein, the gate conductive region in the first trench extends to the outside or around the protrusion.

3. The electronic device of claim 1 or claim 2, wherein, the gate conductive region is electrically continuous along the second axis in each of the plurality of trenches. 4.The electronic device of claim 1, wherein, a respective protrusion of insulating material protrudes from the second trench, and the gate conductive region in the second trench extends outwardly and transversely to the respective protrusion. 5.The electronic device of claim 1, wherein, in the second trench, a respective through-hole extends through the respective protrusion toward the source field plate region to the source field plate region, and a respective conductive contact extends within the through-hole electrically coupled to the source field plate region; the second trench has the first dimension along the third axis corresponding to the respective through-hole; the first trench has the third dimension at a portion of the first trench facing the second trench having the first dimension; and the first trench and the second trench are spaced apart from each other by a constant amount at the facing portions. 6.The electronic device of claim 1, wherein, In a top plan view parallel to the top side, the plurality of trenches extend in a strip-like manner, each trench of the plurality of trenches being spaced apart from an adjacent trench by a constant amount. 7.The electronic device of claim 6, wherein, Adjacent trenches are spaced apart from each other by a constant amount for their entire extension along the second axis. 8.The electronic device of claim 1, wherein, The semiconductor body is configured to accommodate, during operation of the electronic device, a conductive channel located between the first trench and the second trench along the first axis. 9.The electronic device of claim 1, wherein, The semiconductor body has a first conductivity type, the electronic device further comprising: a body region extending at the first side between the first trench and the second trench, the body region having a second conductivity type opposite to the first conductivity type; and a source region in the body region. 10.The electronic device of claim 1, wherein, The conductive contact extending within the through-hole is electrically insulated from the gate conductive region by a lateral wall of the protrusion. 11.The electronic device of claim 1, wherein, A further through-hole extends through the protrusion in the first trench towards the source field plate region, to the source field plate region, and the through-hole and the further through-hole in the first trench are aligned with each other along the second axis. 12.The electronic device of claim 1, wherein, A drain terminal is located at a second side of the semiconductor body. 13.The electronic device of claim 1, wherein, The electronic device is of vertical conduction type.

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