Semiconductor device and manufacturing method, power module, power conversion circuit, and vehicle

Abstract

The application discloses a semiconductor device, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region and a first region; the first surface is further provided with a first trench and a second trench; a voltage-resistant layer is located in the second trench, and the voltage-resistant layer covers a first bottom and a second sidewall of the first trench; a gate structure is located in the first trench; the insulation resistance of the voltage-resistant layer is greater than the insulation resistance of an insulation layer of the gate structure, and the voltage-resistant layer is used for reducing the peak electric field at the bottom of the gate structure; and a source electrode is located on the first surface. The technical scheme provided by the embodiment of the application reduces the specific on-resistance of the semiconductor device and the peak electric field at the bottom of the gate structure, and further improves the electrical performance of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and manufacturing method, a power module, a power conversion circuit and a vehicle. BACKGROUND

[0002] The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) of the third-generation wide-bandgap semiconductor such as silicon carbide or gallium nitride has the characteristics of large critical breakdown field strength, high thermal conductivity, large bandgap and high electron saturation drift speed, so that the third-generation wide-bandgap semiconductor material such as silicon carbide or gallium nitride has become a research hotspot of power semiconductor devices, and in high-power application fields such as high-speed railway, hybrid electric vehicle, smart high-voltage direct current transmission, silicon carbide devices are endowed with high expectations.

[0003] At present, the MOSFET semiconductor device including the trench gate structure cannot reduce the specific on-resistance and the peak electric field at the bottom of the gate structure at the same time, so that the electrical performance of the semiconductor device is poor. SUMMARY

[0004] The present application provides a semiconductor device, a power module, a power conversion circuit and a vehicle to reduce the specific on-resistance and the peak electric field at the bottom of the gate structure, and further improve the electrical performance of the semiconductor device.

[0005] According to a first aspect of the present application, a semiconductor device is provided, comprising:

[0006] A semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region and a first region; the first region is arranged at the first surface, and the well region is arranged at a side of the first region away from the first surface; the first surface is further provided with a first trench and a second trench; the first trench is arranged at the first surface, and the second trench is in communication with the first trench, and the second trench is located between the first trench and the second surface; the first region and the well region have the same and opposite conductivity types; the first trench comprises a first sidewall and a second sidewall arranged opposite to each other; the second trench comprises a third sidewall and a fourth sidewall arranged opposite to each other; the direction in which the first sidewall points to the second sidewall is parallel to the direction in which the third sidewall points to the fourth sidewall;

[0007] A voltage-resistant layer located in the second trench, and covering the surface where the second trench and the first trench meet and the second sidewall;

[0008] a gate structure in the first trench; the gate structure comprises an insulating layer and a gate electrode, the insulating layer is used to insulate and separate the gate electrode and the semiconductor body, the insulating resistance of the voltage-resisting layer is greater than the insulating resistance of the insulating layer, and the voltage-resisting layer is used to reduce the peak electric field at the bottom of the gate structure;

[0009] a source on the first surface;

[0010] a drain on the second surface.

[0011] According to a second aspect of the present application, a manufacturing method of a semiconductor device is provided, comprising:

[0012] providing a semiconductor body comprising a first surface and a second surface arranged oppositely; the semiconductor body further comprises a well region and a first region; the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface;

[0013] forming a first trench on the first surface, the first trench comprising a first sidewall and a second sidewall arranged oppositely;

[0014] forming a second trench in the first trench, wherein the second trench and the first trench are communicated, the second trench is located between the first trench and the second surface; the second trench comprises a third sidewall and a fourth sidewall arranged oppositely; the direction in which the first sidewall points to the second sidewall is parallel to the direction in which the third sidewall points to the fourth sidewall;

[0015] forming a voltage-resisting layer in the second trench and the first trench;

[0016] removing part of the voltage-resisting layer in the first trench, so that the voltage-resisting layer is located in the second trench, and the voltage-resisting layer covers the surface where the second trench and the first trench meet and the second sidewall;

[0017] forming a gate structure in the first trench; the gate structure comprises an insulating layer and a gate electrode, the insulating layer is used to insulate and separate the gate electrode and the semiconductor body, the insulating resistance of the voltage-resisting layer is greater than the insulating resistance of the insulating layer, and the voltage-resisting layer is used to reduce the peak electric field at the bottom of the gate structure;

[0018] forming a source on the first surface;

[0019] forming a drain on the second surface.

[0020] According to a third aspect of the present application, a power module is provided, comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present application, the substrate is used to carry the semiconductor device.

[0021] According to a fourth aspect of the present application, there is provided a power conversion circuit for one or more of current conversion, voltage conversion, power factor correction;

[0022] The power conversion circuit comprises a circuit board and at least one semiconductor device as described in any of the embodiments of the present application, which is electrically connected to the circuit board.

[0023] According to a fifth aspect of the present application, there is provided a vehicle comprising a load and a power conversion circuit as described in any of the embodiments of the present application, which is used to convert AC to DC, convert AC to AC, convert DC to DC or convert DC to AC before inputting to the load.

[0024] The MOSFET semiconductor device provided by the embodiments of the present application has a withstand voltage layer located in the second groove, and the withstand voltage layer covers the surface where the second groove and the first groove meet and the second sidewall, that is, a large part of the bottom of the gate structure is embedded in the withstand voltage layer. Since the insulation resistance of the withstand voltage layer is greater than the insulation resistance of the insulating layer, the maximum electric field is transferred to the withstand voltage layer at the bottom of the gate structure, thereby reducing the peak electric field at the bottom of the gate structure and avoiding breakdown of the gate structure. In the above MOSFET semiconductor device, the source is not required to be set as a trench type source structure to occupy the area of the semiconductor body to reduce the peak electric field at the bottom of the trench type gate structure, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. In the semiconductor device, since the insulation resistance of the withstand voltage layer is greater than the insulation resistance of the insulating layer and the second sidewall covers the first groove, the well region in contact with the first sidewall serves as the channel of the semiconductor device, and the well region in contact with the second sidewall does not serve as the channel of the semiconductor device, thereby enhancing the pressure bearing capacity of the gate structure at the second sidewall and reducing the risk of breakdown of the gate structure.

[0025] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0027] Figure 1 is a structural schematic diagram of a semiconductor device provided by the prior art;

[0028] Figure 2 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0029] Figure 3 is another structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0030] Figure 4 is still another structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0031] Figure 5 is Figure 2 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0032] Figure 6 is Figure 3 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0033] Figure 7 is Figure 4 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0034] Figure 8 is a flow chart of a manufacturing method of a semiconductor device provided by an embodiment of the present application;

[0035] Figures 9-18 is a structural schematic diagram corresponding to each step of a manufacturing method of a semiconductor device provided by an embodiment of the present application;

[0036] Figure 19 is Figure 8 is a flow chart included in S160 in the method;

[0037] Figure 20 is Figure 8 is a flow chart included before S140 in the method;

[0038] Figures 21-22 is Figure 20 is a structural schematic diagram corresponding to each step in the method;

[0039] Figure 23 is Figure 20 is a flow chart included in S1401 in the method;

[0040] Figure 24 is a structural schematic diagram of still another semiconductor device provided by an embodiment of the present application;

[0041] Figure 25 is a structural schematic diagram of still another semiconductor device provided by an embodiment of the present application;

[0042] Figure 26 is a structure diagram of still another semiconductor device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the technical personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0044] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "comprise" and "have" and any variations of the terms "comprise" and "have", are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or elements does not have to be limited to those steps or elements clearly listed, but can include other steps or elements not clearly listed or inherent to these processes, methods, products or devices.

[0045] Figure 1 is a structure diagram of a semiconductor device provided by the prior art. As shown in Figure 1 the semiconductor device includes a semiconductor body 100, which includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 further includes a well region 103, a first region 104 and a third region 105, the first region 104 has a conductivity type opposite to that of the well region 103, the third region 105 has a conductivity type same as that of the well region 103, and the doping concentration of the third region 105 is greater than that of the well region 103. The first surface 101 is provided with a gate trench T1 and a source trench T2. The semiconductor device further includes a gate structure 200, a source structure 300 and a drain 400. The gate structure 200 includes a first insulating layer 201 and a gate electrode 202. The gate structure 200 is located in the gate trench T1. A spacer insulating layer 203 is used to space the gate structure 200 and the source structure 300. The source structure 300 is located in the source trench T2 and includes a source 301, an ohmic contact layer 302, a polysilicon filling layer 303 and a second insulating layer 304.

[0046] Figure 1The MOSFET semiconductor device shown is a dual-trench MOSFET semiconductor device, with the source structure 300 located in the source trench T2. Although the arrangement of the source structure 300 can reduce the peak electric field at the first insulating layer 201 at the bottom of the gate structure 200, the source structure 300 occupies the area of ​​the semiconductor body 100, reducing the specific on-resistance of the semiconductor device and resulting in relatively poor electrical performance of the semiconductor device.

[0047] To reduce the specific on-resistance and peak electric field at the bottom of the gate structure of MOSFET semiconductor devices, thereby improving the electrical performance of semiconductor devices, embodiments of the present invention provide the following technical solutions:

[0048] like Figure 2 As shown, Figure 2 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 further includes a well region 103 and a first region 104; the first region 104 is disposed on the first surface 101, and the well region 103 is disposed on the side of the first region 104 away from the first surface 101; the first surface 101 is also provided with a first trench T3 and a second trench T4, the first trench T3 is disposed on the first surface 101, the second trench T4 is connected to the first trench T3, and the second trench T4 is located between the first trench T3 and the second surface 102; the conductivity type of the first region 104 is the same as that of the well region 103 but opposite; the first trench T3 includes a first sidewall T01 and a second sidewall T02 disposed opposite to each other; the first... The second trench T4 includes a third sidewall T03 and a fourth sidewall T04 disposed opposite to each other; the direction of the first sidewall T01 pointing to the second sidewall T02 is parallel to the direction of the third sidewall T03 pointing to the fourth sidewall T04; a withstand layer 106 is located in the second trench T4, and the withstand layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet and the second sidewall T02; a gate structure 200 is located in the first trench T3; the gate structure 200 includes an insulating layer 201 and a gate electrode 202, the insulating layer 201 is used to insulate the gate electrode 202 and the semiconductor body 100, the insulation resistance of the withstand layer 106 is greater than the insulation resistance of the insulating layer 201, and the withstand layer 106 is used to reduce the peak electric field at the bottom of the gate structure 200; a source 305 is located on the first surface 101; and a drain 400 is located on the second surface 102.

[0049] For example, such as Figure 2As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present application, the semiconductor body 100 can also only include the epitaxial layer 20. In other embodiments of the present application, the semiconductor body 100 can also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 by a one-time epitaxial process, and the epitaxial process includes a chemical vapor phase epitaxial growth (CVE), a molecular beam epitaxy (MBD), an atomic layer epitaxy (ALE), and the like.

[0050] Optionally, in other embodiments, the MOSFET semiconductor device can also include a third region, the third region has the same conductivity type as the well region 103, the third region has a doping concentration greater than that of the well region 103, and the third region is electrically connected to the source 305 to form a good ohmic contact with the source 305. The third region is located on the side of the well region 103 away from the second surface 102.

[0051] The MOSFET semiconductor device provided by the embodiments of the present application has the following advantages. The voltage resistance layer 106 is located in the second trench T4, and the voltage resistance layer 106 covers the face T05 where the second trench T4 and the first trench T3 meet and the second side wall T02, that is, a large part of the bottom of the gate structure 200 is embedded in the voltage resistance layer 106. Since the insulation resistance of the voltage resistance layer 106 is greater than the insulation resistance of the insulation layer 201, the maximum electric field is transferred to the voltage resistance layer 106 at the bottom of the gate structure 200, thereby reducing the peak electric field at the bottom of the trench-type gate structure 200 and avoiding the breakdown of the gate structure 200. In the above MOSFET semiconductor device, the source 305 does not need to be set as a trench-type source structure to occupy the area of the semiconductor body 100 to reduce the peak electric field at the bottom of the trench-type gate structure 200, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. Since the insulation resistance of the voltage resistance layer 106 is greater than the insulation resistance of the insulation layer 201 and the voltage resistance layer 106 covers the second side wall T02 of the first trench T3, in the semiconductor device, the well region 103 in contact with the first side wall T01 serves as the channel of the semiconductor device, and the well region 103 in contact with the second side wall T02 does not serve as the channel of the semiconductor device, thereby enhancing the pressure-bearing capacity of the gate structure 200 at the second side wall T02 and reducing the risk of breakdown of the gate structure 200.

[0052] Optionally, on the basis of the above technical solutions, as Figure 2 As shown, the vertical projection area of the second trench T4 on the first surface 101 is less than the vertical projection area of the first trench T3 on the first surface 101.

[0053] Specifically, the vertical projection area of the second trench T4 on the first surface 101 is less than the vertical projection area of the first trench T3 on the first surface 101, compared with the scheme that the vertical projection area of the second trench T4 on the first surface 101 is equal to the vertical projection area of the first trench T3 on the first surface 101, the area of the semiconductor body 100 occupied by the withstand voltage layer 106 is reduced, and the specific on-resistance of the semiconductor device is reduced.

[0054] Optionally, on the basis of the above technical solutions, as shown in Figure 2 The vertical projection of the second side wall T02 and the fourth side wall T04 on the first surface 101 coincides.

[0055] Specifically, the vertical projection of the second side wall T02 and the fourth side wall T04 on the first surface 101 coincides, the position of the third side wall T03 can be controlled to control the vertical projection area of the second trench T4 on the first surface 101, so that the vertical projection area of the second trench T4 on the first surface 101 is less than the vertical projection area of the first trench T3 on the first surface 101.

[0056] Optionally, on the basis of the above technical solutions, as shown in Figure 2 In the direction perpendicular to the second surface 102 and pointing to the first surface 101, the distance between the two side walls of the second trench T4 is equal to half the distance between the two side walls of the first trench T3. On the one hand, half of the bottom of the gate structure 200 is embedded into the withstand voltage layer 106, and since the insulation resistance of the withstand voltage layer 106 is greater than the insulation resistance of the insulating layer 201, the maximum electric field is transferred to the withstand voltage layer 106 at the bottom of the gate structure 200, thereby reducing the peak electric field at the bottom of the gate structure 200 and avoiding breakdown of the gate structure 200; on the other hand, the scheme that the distance between the two side walls of the second trench T4 is equal to half the distance between the two side walls of the first trench T3 reduces the area of the semiconductor body 100 occupied by the withstand voltage layer 106, and reduces the specific on-resistance of the semiconductor device. The direction perpendicular to the second surface 102 and pointing to the first surface 101 is the X direction in the figure.

[0057] Optionally, on the basis of the above technical solutions, as shown in Figure 2As shown in the figure, the gate structure 200 comprises an insulating layer 201 and a gate electrode 202; the insulating layer 201 is located at least at the bottom T06 and the first sidewall T01 of the first trench T3; the gate electrode 202 is located at the side of the insulating layer 201 and the voltage-resisting layer 106 in the first trench T3 away from the semiconductor body 100. In the direction perpendicular to the second surface 102 and pointing to the first surface 101, the distance between the first sidewall T01 and the gate electrode 202 is smaller than the distance between the gate electrode 202 and the second sidewall T02. Specifically, the insulating layer 201 is located at least at the bottom T06 and the first sidewall T01 of the first trench T3, for insulating the gate electrode 202 and the semiconductor body 100, and the gate electrode 202 is used for accessing the gate signal. In the direction perpendicular to the second surface 102 and pointing to the first surface 101, the distance between the first sidewall T01 and the gate electrode 202 is smaller than the distance between the gate electrode 202 and the second sidewall T02, for increasing the thickness of the voltage-resisting layer 106 at the second sidewall T02, thereby increasing the insulation resistance, to realize the function of the voltage-resisting layer 106 for reducing the peak electric field at the bottom of the gate structure 200, and to enhance the pressure-bearing capacity of the gate structure 200 at the first sidewall T01. In the embodiment of the present application, the direction of the second surface 102 pointing to the first surface 101 is the Y direction in the figure.

[0058] For example, the insulating layer 201 comprises a high-k dielectric layer such as silicon dioxide, aluminum oxide, hafnium oxide, etc. When the insulating layer 201 is silicon dioxide, it can be obtained by oxidizing the semiconductor body 100. The voltage-resisting layer 106 comprises at least one of silicon oxide, silicon nitride and polysilicon.

[0059] For example, the insulating layer 201 comprises silicon dioxide. As shown in the figure, Figure 2 the insulating layer 201 comprises silicon dioxide, and the voltage-resisting layer 106 comprises silicon dioxide. As shown in the figure, Figure 3 Figure 3 is another structure diagram of a semiconductor device provided by the embodiment of the present application, the insulating layer 201 comprises silicon dioxide, and the voltage-resisting layer 106 comprises silicon nitride. As shown in the figure, Figure 4 Figure 4 is another structure diagram of a semiconductor device provided by the embodiment of the present application, the insulating layer 201 comprises silicon dioxide, and the voltage-resisting layer 106 comprises polysilicon.

[0060] For example, the insulating layer 201 comprises silicon dioxide. As shown in the figure, Figure 2 and Figure 3 When the material of the voltage-resisting layer 106 and the material of the insulating layer 201 are the same, or both are insulating materials, the insulating layer 201 is located at the bottom T06 and the first sidewall T01 of the first trench T3.

[0061] Optionally, on the basis of the above technical solution, as shown in the figure, Figure 4 ​​As shown, when the material of the voltage-resisting layer 106 has conductivity, such as polycrystalline silicon with weak conductivity, the insulating layer 201 is located on the first side wall T01, the bottom T06 of the first trench T3, and the surface of the voltage-resisting layer 106 away from the semiconductor body 100, and the insulating layer 201 is located on the surface of the voltage-resisting layer 106 away from the semiconductor body 100 for insulating the gate electrode 202 and the voltage-resisting layer 106.

[0062] Optionally, as shown in the technical scheme, Figure 2 The semiconductor device further includes a spacer insulating layer 203 and an ohmic contact layer 302. The spacer insulating layer 203 is used for spacing the gate structure 200 and the source electrode 305. The ohmic contact layer 302 enables the source electrode 305 to form a good ohmic contact with the first region 104. The ohmic contact layer 302 includes one or more of an alloy or a stack of metal Ni, metal Ti, and metal Ni, an alloy or a stack of metal Ni and metal Pt, an alloy or a stack of metal Co, metal Ti, and metal Al, and a stack of metal Ti and TiN.

[0063] Optionally, based on the technical scheme above, as shown in the technical scheme, Figures 2-4 The semiconductor body 100 further includes a second region 107 surrounding the bottom of the second trench T4 and the third side wall T03. The second region 107 has the same conductivity type as the well region 103, and the doping concentration of the second region 107 is greater than that of the well region 103.

[0064] Specifically, the second region 107 has the same conductivity type as the well region 103, i.e., the conductivity type of the second region 107 is opposite to that of the drift region between the second region 107 and the second surface 102, so that the second region 107 and the drift region between the second region 107 and the second surface 102 form a depletion layer, which can further reduce the peak electric field at the bottom of the trench-type gate structure 200.

[0065] In the embodiment, the MOSFET semiconductor device includes an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. Taking the N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the second region 107 is a P+ doped region, and the well region 103 is a P- well region.

[0066] Optionally, based on the technical scheme above, as shown in the technical scheme, Figures 2-4 The second region 107 includes a first part and a second part. The first part is located on the third side wall T03, and the second part is located on the bottom of the second trench T4.

[0067] Specifically, the second region 107 surrounds the bottom of the second trench T4 and the third sidewall T03, so that the second region 107 includes a part of the second region formed on the third sidewall T03 by the inclined ion implantation process and a part of the second region 107 formed on the bottom of the second trench T4 by the vertical ion implantation process. The above semiconductor device can complete the preparation process of the second region 107 only by the vertical ion implantation process and the single-side inclined ion implantation process.

[0068] Optionally, on the basis of the above technical solutions, as Figures 5-7 Figure 5 Figure 2 A structure diagram of a semiconductor device in which a second trench includes two sub-trenches, Figure 6 Figure 3 A structure diagram of a semiconductor device in which a second trench includes two sub-trenches, Figure 7 Figure 4 A structure diagram of a semiconductor device in which a second trench includes two sub-trenches, and the second trench T4 includes at least two sub-trenches T5; the sub-trench T5 includes a fifth sidewall T07 and a sixth sidewall T08 arranged oppositely; the sixth sidewall T08 of the sub-trench T5 and the second sidewall T02 coincide in the vertical projection on the first surface 101; in the direction in which the first surface 101 points to the second surface 102, the plurality of sub-trenches T5 are arranged adjacently, and the interval between the two sidewalls of the sub-trench T5 decreases successively.

[0069] Exemplarily, Figures 5-7 In the example, the second trench T4 includes two sub-trenches T5. The depths of the sub-trenches T5 can be the same or different. The depth of a single sub-trench T5 is greater than or equal to 0.3 microns and less than or equal to 10 microns.

[0070] Specifically, in the direction in which the first surface 101 points to the second surface 102 (i.e., the direction opposite to the Y direction), Figures 5-7 In the example, in the direction in which the first surface 101 points to the second surface 102 (i.e., the direction opposite to the Y direction),

[0071] Optionally, on the basis of the above technical solutions, as Figures 2-4 Figures 5-7 ​​​​​As shown, the vertical projection of the second region 107 on the first surface 101 is within the vertical projection of the first trench T3 on the first surface 101.

[0072] Specifically, compared with the scheme that the vertical projection of the first trench T3 on the first surface 101 is within the vertical projection of the second region 107 on the first surface 101, the above technical scheme reduces the area of the semiconductor body 100 occupied by the second region 107, and reduces the specific on-resistance of the semiconductor device. The direction perpendicular to the second surface 102 and pointing to the first surface 101 is the X direction in the figure.

[0073] Optionally, on the basis of the above technical scheme, the semiconductor body 100 comprises a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0074] Specifically, the semiconductor body 100 comprises a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 comprises a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device. The silicon carbide MOSFET semiconductor device or the gallium nitride MOSFET semiconductor device has the advantages of high withstand voltage, low on-resistance and high frequency, and can further improve the performance of the semiconductor device.

[0075] The embodiment of the application also provides a manufacturing method of a semiconductor device. Figure 8 As shown, Figure 8 The embodiment of the application provides a flow chart of a manufacturing method of a semiconductor device, and the manufacturing method of the semiconductor device comprises the following steps:

[0076] S110, providing a semiconductor body comprising oppositely arranged first and second surfaces; the semiconductor body further comprises a well region and a first region; the first region is arranged on the first surface, and the well region is arranged on the side of the first region away from the first surface.

[0077] As shown, Figure 9 As shown, a semiconductor body 100 is provided, and the semiconductor body 100 comprises a silicon carbide semiconductor body or a gallium nitride semiconductor body. The semiconductor body 100 comprises oppositely arranged first and second surfaces 101 and 102; the semiconductor body 100 further comprises a well region 103 and a first region 104; the first region 104 is arranged on the first surface 101, and the well region 103 is arranged on the side of the first region 104 away from the first surface 101.

[0078] The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present application, the semiconductor body 100 can only include the epitaxial layer 20. In other embodiments of the present application, the semiconductor body 100 can include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 by an epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBE), atomic layer epitaxy (ALE), etc.

[0079] Optionally, the MOSFET semiconductor device can further include a third region having the same conductivity type as the well region 103 and a doping concentration greater than that of the well region 103, the third region being electrically connected to the source 305 for forming a good ohmic contact with the source 305. The third region is located on the side of the well region 103 away from the second surface 102.

[0080] S120, forming a first trench on the first surface, the first trench including oppositely arranged first and second sidewalls.

[0081] The process of forming the first trench T3 on the first surface 101 is as follows:

[0082] As shown in FIG. 5, a first photoresist 500 is formed on the first surface 101. As shown in FIG. 6, a first trench T3 including oppositely arranged first and second sidewalls T01 and T02 is formed on the first surface 101 by photolithography and etching processes. Figure 10 Figure 11 As shown in FIG. 5, a first photoresist 500 is formed on the first surface 101. As shown in FIG. 6, a first trench T3 including oppositely arranged first and second sidewalls T01 and T02 is formed on the first surface 101 by photolithography and etching processes.

[0083] S130, forming a second trench in the first trench, wherein the second trench is in communication with the first trench and located between the first trench and the second surface; the second trench includes oppositely arranged third and fourth sidewalls; the direction in which the first sidewall points to the second sidewall is parallel to the direction in which the third sidewall points to the fourth sidewall.

[0084] The process of forming the second trench T4 in the first trench T3 is as follows:

[0085] As shown in FIG. 7, a second photoresist 501 is formed in the first trench T3. Then, a second trench T4 is formed in the first trench T3 by photolithography and etching processes. The second trench T4 includes oppositely arranged third and fourth sidewalls T03 and T04; the direction in which the first sidewall T01 points to the second sidewall T02 is parallel to the direction in which the third sidewall T03 points to the fourth sidewall T04; and the well region 103 in contact with the first sidewall T01 serves as the channel of the semiconductor device. Figure 12

[0086] S140, forming a voltage-resistant layer in the second trench and the first trench.​​

[0087] like Figures 13-15 As shown, after removing the second photoresist 501 inside the first trench T3, a pressure-resistant layer 106 is formed in the second trench T4 and the first trench T3 through processes such as oxidation or deposition. Figure 13 As shown, the pressure-resistant layer 106 is silicon dioxide. (As...) Figure 14 As shown, the pressure-resistant layer 106 is silicon nitride. (As...) Figure 15 As shown, the pressure-resistant layer 106 is polycrystalline silicon with weak conductivity.

[0088] S150. Remove part of the pressure-resistant layer in the first trench so that the pressure-resistant layer is located in the second trench and covers the surface where the second trench and the first trench meet, as well as the second sidewall.

[0089] The process of removing part of the pressure-resistant layer 106 within the first trench T3 is as follows:

[0090] like Figure 16 As shown, the withstand voltage layer 106 and the insulating layer 201 of the subsequently formed gate structure 200 are made of the same material. For example, when the withstand voltage layer 106 and the insulating layer 201 are silicon dioxide, a third photoresist 502 is first formed on the first surface 101. Then, through photolithography and etching processes, a portion of the withstand voltage layer 106 within the first trench T3 is removed, so that the withstand voltage layer 106 is located within the second trench T4, and the withstand voltage layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet, and the second sidewall T02. The vertical projection of the surface T05 where the second trench T4 and the first trench T3 meet on the first surface 101 coincides with the vertical projection of the second trench T4 on the first surface 101. It should be noted that when the material of the insulating layer 201 is the same as that of the withstand voltage layer 106, when removing part of the withstand voltage layer 106 in the first trench T3, the withstand voltage layer 106 at the bottom T06 of the first trench T3 can be retained and reused as the insulating layer 201 of the gate structure 200 formed subsequently.

[0091] like Figure 17 and Figure 18 As shown, the materials of the withstand voltage layer 106 and the insulating layer 201 of the subsequently formed gate structure 200 are different. First, a third photoresist 502 is formed on the first surface 101. Then, through photolithography and etching processes, a portion of the withstand voltage layer 106 in the first trench T3 is removed, so that the withstand voltage layer 106 is located in the second trench T4, and the withstand voltage layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet and the second sidewall T02; the vertical projection of the surface T05 where the second trench T4 and the first trench T3 meet on the first surface 101 and the vertical projection of the second trench T4 on the first surface 101 coincide. Figure 17 The intermediate pressure-resistant layer 106 is made of silicon nitride. Figure 18 The medium-pressure layer 106 is made of polycrystalline silicon.

[0092] S160. A gate structure is formed in the first trench. The gate structure includes an insulating layer and a gate electrode. The insulating layer is used to insulate the gate electrode and the semiconductor body. The insulation resistance of the withstand voltage layer is greater than the insulation resistance of the insulating layer. The withstand voltage layer is used to reduce the peak electric field at the bottom of the gate structure.

[0093] like Figures 2-4 As shown, a gate structure 200 is formed in the first trench T3. The gate structure 200 includes an insulating layer 201 and a gate electrode 202. The insulating layer 201 is used to insulate the gate electrode 202 and the semiconductor body 100. The insulation resistance of the withstand voltage layer 106 is greater than the insulation resistance of the insulating layer 201. The withstand voltage layer 106 is used to reduce the peak electric field at the bottom of the gate structure 200.

[0094] S170, the source electrode is formed on the first surface.

[0095] like Figures 2-4 As shown, a source electrode 305 is formed on the first surface 101. The ohmic contact layer 302 enables the source electrode 305 to form good ohmic contact with the first region 104 and the third region 105.

[0096] S180, a drain electrode is formed on the second surface.

[0097] like Figures 2-4 As shown, a drain 400 is formed on the second surface 102. The drain 400 may include a stack of metals Ti, Ni, and Ag.

[0098] In the MOSFET semiconductor device manufactured according to this embodiment of the invention, the withstand layer 106 is located within the second trench T4, and the withstand layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet, as well as the second sidewall T02. That is, a large portion of the bottom of the gate structure 200 is embedded in the withstand layer 106. Because the insulation resistance of the withstand layer 106 is greater than that of the insulating layer 201, the maximum electric field is transferred to the withstand layer 106 at the bottom of the gate structure 200, thereby reducing the peak electric field at the bottom of the gate structure 200 and preventing the gate structure 200 from being broken down. Furthermore, in the above-mentioned MOSFET semiconductor device, it is not necessary to set the source 305 as a trench-type source structure, occupying the area of ​​the semiconductor body 100, to reduce the peak electric field at the bottom of the trench-type gate structure 200, thereby reducing the specific on-resistance of the semiconductor device and improving the electrical performance of the semiconductor device. Since the insulation resistance of the withstand layer 106 is greater than that of the insulation layer 201, and the second sidewall T02 covering the first trench T3 is also present, in this semiconductor device, the well region 103 in contact with the first sidewall T01 serves as the channel of the semiconductor device, while the well region 103 in contact with the second sidewall T02 does not serve as the channel of the semiconductor device. This enhances the pressure-bearing capacity of the gate structure 200 located at the second sidewall T02 and reduces the risk of the gate structure 200 being broken down.

[0099] Optionally, based on the above technical solution, S130 forming a second trench within the first trench includes:

[0100] A second groove is formed within the first groove on the first surface, and its vertical projected area is smaller than that of the first groove on the first surface.

[0101] like Figure 12 As shown, the vertical projection area of ​​the second trench T4 on the first surface 101 is smaller than the vertical projection area of ​​the first trench T3 on the first surface 101. The withstand layer 106 covers the surface T05 where the second trench T4 and the first trench T3 meet. Compared with the scheme where the vertical projection area of ​​the second trench T4 on the first surface 101 is greater than or equal to the vertical projection area of ​​the first trench T3 on the first surface 101, the area of ​​the semiconductor body 100 occupied by the withstand layer 106 is reduced, and the specific on-resistance of the semiconductor device is reduced.

[0102] Optionally, based on the above technical solution, S130 forming a second trench within the first trench includes:

[0103] A second groove is formed within the first groove, where the vertical projections of the fourth and second sidewalls coincide with those of the first surface.

[0104] like Figure 12As shown, the fourth side wall T04 and the second side wall T02 of the second trench T4 are formed in the first trench T3, and the vertical projection of the first surface 101 of the second trench T4 coincides with the vertical projection of the first surface 101 of the first trench T3.

[0105] Specifically, the vertical projection of the second side wall T02 and the fourth side wall T04 on the first surface 101 coincides, and the vertical projection area of the second trench T4 on the first surface 101 can be controlled by controlling the position of the third side wall T03, so that the vertical projection area of the second trench T4 on the first surface 101 is smaller than the vertical projection area of the first trench T3 on the first surface 101.

[0106] Optionally, based on the technical scheme above, in the technical scheme, Figure 19 As shown, Figure 19 is Figure 8 the flowchart included in S160, S160 forms a gate structure in the first trench, which includes:

[0107] S1601, at least form an insulating layer on the bottom and the first side wall of the first trench.

[0108] For example, the insulating layer 201 includes a high-k dielectric layer such as silicon dioxide, aluminum oxide, hafnium oxide, etc. When the insulating layer 201 is silicon dioxide, it can be obtained by oxidizing the semiconductor body 100. The voltage-resistant layer 106 includes at least one of silicon oxide, silicon nitride, and polysilicon.

[0109] For example, the insulating layer 201 includes silicon dioxide. As shown, Figure 2 the insulating layer 201 includes silicon dioxide, and the voltage-resistant layer 106 includes silicon dioxide. As shown, Figure 3 the insulating layer 201 includes silicon dioxide, and the voltage-resistant layer 106 includes silicon nitride. As shown, Figure 4 the insulating layer 201 includes silicon dioxide, and the voltage-resistant layer 106 includes polysilicon.

[0110] As shown, Figure 2 and Figure 3 When the material of the voltage-resistant layer 106 and the material of the insulating layer 201 are the same, or both are insulating materials, the insulating layer 201 is located at the bottom T06 and the first side wall T01 of the first trench T3.

[0111] Optionally, when the voltage-resistant layer 106 has conductivity, S1601 at least forms an insulating layer on the bottom and the first side wall of the first trench, which includes:

[0112] forming an insulating layer on the first side wall, the second bottom, and the surface of the voltage-resistant layer away from the semiconductor body.

[0113] As shown, Figure 4As shown, when the material of the withstand layer 106 is conductive, such as polycrystalline silicon with weak conductivity, the insulating layer 201 is located on the first sidewall T01, the bottom T06 of the first trench T3, and on the surface of the withstand layer 106 away from the semiconductor body 100. The insulating layer 201 on the surface of the withstand layer 106 away from the semiconductor body 100 is used to insulate the spacer gate electrode 202 and the withstand layer 106.

[0114] S1602, a gate electrode is formed on the side of the insulating layer and the withstand voltage layer in the first trench away from the semiconductor body, wherein, in the direction perpendicular to the second surface and pointing to the first surface, the spacing between the first sidewall and the gate electrode is smaller than the spacing between the gate electrode and the second sidewall.

[0115] like Figures 2-4 As shown, a gate electrode 202 is formed on the side of the insulating layer 201 and the withstand voltage layer 106 away from the semiconductor body 100 within the first trench T3. The gate electrode 202 may be made of polycrystalline silicon.

[0116] Specifically, the insulating layer 201 is located at least at the bottom T06 and the first sidewall T01 of the first trench T3 to insulate the gate electrode 202 and the semiconductor body 100. The gate electrode 202 is used to receive the gate electrical signal.

[0117] In a direction perpendicular to the second surface 102 pointing towards the first surface 101, the spacing between the first sidewall T01 and the gate electrode 202 is smaller than the spacing between the gate electrode 202 and the second sidewall T02. This increases the thickness of the withstand voltage layer 106 located on the second sidewall T02, thereby increasing its insulation resistance. This allows the withstand voltage layer 106 to reduce the peak electric field at the bottom of the gate structure 200 and enhances the voltage-bearing capacity of the gate structure 200 located at the first sidewall T01. In this embodiment of the invention, the direction from the second surface 102 to the first surface 101 is the Y direction in the figure.

[0118] Optionally, based on the above technical solutions, such as Figure 20 As shown, Figure 20 yes Figure 8 The process view preceding S140, which includes S140 before the formation of the pressure-resistant layer in the second and first trenches, further includes:

[0119] S1401. A second region is formed at the bottom of the second trench and on the third sidewall, wherein the conductivity type of the second region is the same as that of the well region, and the doping concentration of the second region is greater than that of the well region.

[0120] The process of forming the second region 107 at the bottom of the second trench T4 and the third sidewall T03 is as follows:

[0121] like Figure 21As shown, using the second photoresist 501 as a mask, a suitable ion implantation angle is selected to form a second region 107 at the bottom of the second trench T4 and the third sidewall T03.

[0122] like Figure 22 As shown, after the ion implantation process is completed, the second photoresist 501 is removed.

[0123] Specifically, the conductivity type of the second region 107 is the same as that of the well region 103, that is, the conductivity type of the second region 107 is opposite to that of the drift region between the second region 107 and the second surface 102, so that the second region 107 and the drift region between the second region 107 and the second surface 102 constitute a depletion layer, which can further reduce the peak electric field at the bottom of the trench gate structure 200.

[0124] Among them, MOSFET semiconductor devices include N-type MOSFET semiconductor devices or P-type MOSFET semiconductor devices. Taking an N-type MOSFET semiconductor device as an example, the semiconductor body 100 is an N-type semiconductor body, the first region 104 is an N+ doped region, the second region 107 is a P+ doped region, and the well region 103 is a P-well region.

[0125] Optionally, based on the above technical solutions, such as Figure 23 As shown, Figure 23 yes Figure 20 The process diagram included in S1401 shows that S1401 forms a second region at the bottom of the second trench and on the third sidewall, including:

[0126] S14011, The first part of the second region is formed on the third sidewall by a tilted ion implantation process.

[0127] like Figure 21 As shown, the first part of the second region 107 is formed on the third sidewall T03 by a tilted ion implantation process.

[0128] S14012. A second part of the second region is formed at the bottom of the second trench by a vertical ion implantation process, wherein the conductivity type of the second region is the same as that of the well region, and the doping concentration of the second region is greater than that of the well region.

[0129] like Figure 21 As shown, a second portion of the second region 107 is formed at the bottom of the second trench T4 by a vertical ion implantation process. The conductivity type of the second region 107 is the same as that of the well region 103, and the doping concentration of the second region 107 is greater than that of the well region 103.

[0130] Specifically, the second region 107 surrounds the bottom of the second trench T4 and the third sidewall T03, so that the second region 107 includes a part of the second region formed by the inclined ion implantation process on the third sidewall T03 and a part of the second region 107 formed by the vertical ion implantation process on the bottom of the second trench T4. The above semiconductor device can complete the preparation process of the second region 107 only by the vertical ion implantation process and the single-side inclined ion implantation process.

[0131] Optionally, in the technical scheme, the step of forming the second trench in the first trench comprises:

[0132] forming at least two sub-trenches in the first trench, wherein the sub-trenches comprise oppositely arranged fifth sidewalls and sixth sidewalls; the vertical projections of the sixth sidewalls of the sub-trenches and the second sidewall on the first surface coincide; in the direction in which the first surface points to the second surface, the plurality of sub-trenches are arranged adjacently, and the spacing between the two sidewalls of the sub-trenches decreases successively.

[0133] The process of forming at least two sub-trenches T5 in the part of the bottom of the first trench T3 is as follows:

[0134] As shown in Figure 24 and Figure 25 , the second photoresist 501 is formed in the first trench T3. Then, two sub-trenches T5 are formed in the bottom of the first trench T3 by the photoetching and etching processes. The sub-trenches T5 comprise oppositely arranged fifth sidewalls T07 and sixth sidewalls T08; the vertical projections of the sixth sidewalls T08 of the sub-trenches T5 and the second sidewall T02 on the first surface 101 coincide.

[0135] In the direction in which the first surface 101 points to the second surface 102, the plurality of sub-trenches T5 are arranged adjacently, and the spacing between the two sidewalls of the sub-trenches T5 decreases successively. Exemplarily, Figure 24 and Figure 25 schematically show the scheme of forming two sub-trenches T5 in the part of the bottom of the first trench T3. The fifth sidewalls T07 of the at least two sub-trenches T5 constitute the third sidewall T03 of the second trench T4.

[0136] Specifically, in the direction that the first surface 101 points to the second surface 102, the interval between the two sidewalls of the sub-trench T5 decreases in turn, compared with the technical solution that the interval between the two sidewalls of the sub-trench T5 is equal, the area of the semiconductor body 100 occupied by the voltage resistance layer 106 is reduced, and the specific on-resistance of the semiconductor device is reduced. Moreover, the second trench T4 includes at least two sub-trenches T5, the etching depth of each etching of the second trench T4 is reduced, thereby the etching difficulty is reduced, and the etching precision is improved. Especially for the semiconductor body 100 being a silicon carbide semiconductor body or a gallium nitride semiconductor body, the hardness is relatively large, and the technical solution that the second trench T4 includes at least two sub-trenches T5 has a more significant effect on improving the etching precision of the second trench T4.

[0137] As shown in Figure 26 , the second photoresist 501 is removed.

[0138] Optionally, as shown in Figure 25 , before forming the voltage resistance layer 106 in the second trench T4 and the first trench T3, the method further includes: taking the second photoresist 501 as a mask, forming a first part of a second region 107 on the fifth sidewall T07 by means of an inclined ion implantation process, and forming a second part of the second region 107 on the bottom of the sub-trench T5 by means of a vertical ion implantation process, wherein the conductive type of the second region 107 is the same as that of the well region 103, and the doping concentration of the second region 107 is greater than that of the well region 103.

[0139] Specifically, the second region 107 surrounds the bottom and the third sidewall T03 of the second trench T4, so that the second region 107 includes the part of the second region 107 formed on the fifth sidewall T07 by means of the inclined ion implantation process and the part of the second region 107 formed on the bottom of the sub-trench T5 by means of the vertical ion implantation process. The above semiconductor device can complete the preparation process of the second region 107 only by means of the vertical ion implantation process and the single-side inclined ion implantation process.

[0140] The embodiment of the present application provides a power module, which comprises a substrate and at least one semiconductor device according to any of the embodiments of the present application, and the substrate is used for carrying the semiconductor device. Therefore, the power module has the beneficial effects of the semiconductor device according to any of the embodiments of the present application, which will not be described herein again.

[0141] The embodiment of the present application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device according to any of the embodiments of the present application, and the semiconductor device is electrically connected with the circuit board.

[0142] Therefore, the power conversion circuit includes the advantageous effects of any of the semiconductor devices of the embodiments of the present application, which will not be described herein.

[0143] The embodiments of the present application also provide a vehicle including a load and a power conversion circuit as any of the embodiments of the present application, which is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input to the load. Therefore, the vehicle includes the advantageous effects of any of the power conversion circuits of any of the embodiments of the present application, which will not be described herein.

[0144] It should be understood that the various forms of flow shown above can be reordered, added to, or have steps deleted. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which will not be limited herein.

[0145] The above detailed description does not constitute a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a semiconductor body comprising a first surface and a second surface arranged oppositely; the semiconductor body further comprises a first region and a well region; the first region is arranged on the first surface, and the well region is arranged on a side of the first region away from the first surface; the first surface is further provided with a first trench and a second trench; the first trench is arranged on the first surface, and the second trench is in communication with the first trench and is located between the first trench and the second surface; the first region and the well region have the same and opposite conductive types; the first trench comprises a first sidewall and a second sidewall arranged oppositely; the second trench comprises a third sidewall and a fourth sidewall arranged oppositely; the first sidewall points in a direction parallel to a direction in which the third sidewall points to the fourth sidewall; a voltage-resistant layer located in the second trench and covering a surface where the second trench and the first trench meet and the second sidewall; a gate structure located in the first trench; the gate structure comprises an insulating layer and a gate electrode; the insulating layer is used to insulate and separate the gate electrode and the semiconductor body; the voltage-resistant layer has better insulation performance than the insulating layer; and the voltage-resistant layer is used to reduce the peak electric field at the bottom of the gate structure; a source electrode located on the first surface; a drain electrode located on the second surface.

2. The semiconductor device according to claim 1, wherein The vertical projection area of the second trench on the first surface is smaller than the vertical projection area of the first trench on the first surface.

3. The semiconductor device of claim 2, wherein, The vertical projections of the second sidewall and the fourth sidewall on the first surface coincide.

4. The semiconductor device according to claim 1, wherein: the insulating layer is located at least at the bottom of the first trench and the first sidewall; the gate electrode is located on a side of the insulating layer and the voltage-resistant layer in the first trench facing the gate structure; in a direction perpendicular to the second surface and pointing to the first surface, the distance between the first sidewall and the gate electrode is smaller than the distance between the gate electrode and the second sidewall.

5. The semiconductor device of claim 4, wherein, The voltage-resistant layer is made of high-resistivity material, and has better insulation performance than the insulating layer; the insulating layer is located at the first sidewall, the bottom of the first trench, and a side of the voltage-resistant layer facing the gate structure.

6. The semiconductor device according to any one of claims 1 to 3, wherein The semiconductor body further comprises a second region surrounding the bottom of the second trench and the third sidewall; the second region and the well region have the same conductive type, and the second region has a higher doping concentration than the well region.

7. The semiconductor device according to any one of claims 1 to 3, wherein The second trench comprises at least two sub-trenches; the sub-trenches comprise a fifth sidewall and a sixth sidewall arranged oppositely; the sixth sidewall of the sub-trench and the second sidewall have vertical projections on the first surface that coincide; in a direction from the first surface to the second surface, the sub-trenches are arranged adjacently, and the distance between the two sidewalls of the sub-trenches decreases successively.

8. The semiconductor device of claim 6, wherein, The vertical projection of the second region on the first surface is within the vertical projection of the first trench on the first surface.

9. The semiconductor device of claim 1, wherein The material of the voltage-resistant layer comprises at least one of silicon oxide and silicon nitride.

10. The semiconductor device of claim 1, wherein The semiconductor body comprises a silicon carbide semiconductor body or a gallium nitride semiconductor body.

11. A method of manufacturing a semiconductor device, characterized by Comprising: A semiconductor body is provided, comprising a first surface and a second surface arranged oppositely; the semiconductor body further comprises a well region and a first region; the first region is arranged at the first surface, and the well region is arranged at a side of the first region away from the first surface; A first trench is formed at the first surface, the first trench comprising a first sidewall and a second sidewall arranged oppositely; A second trench is formed in the first trench, wherein the second trench and the first trench are in communication, and the second trench is located between the first trench and the second surface; the second trench comprises a third sidewall and a fourth sidewall arranged oppositely; the direction in which the first sidewall points to the second sidewall is parallel to the direction in which the third sidewall points to the fourth sidewall; A voltage-resisting layer is formed in the second trench and the first trench; Part of the voltage-resisting layer in the first trench is removed, so that the voltage-resisting layer is located in the second trench, and the voltage-resisting layer covers the surface where the second trench and the first trench meet and the second sidewall; A gate structure is formed in the first trench, the gate structure comprising an insulating layer and a gate electrode, the insulating layer being used to insulate and separate the gate electrode and the semiconductor body, the voltage-resisting layer having better insulation performance than the insulating layer, and the voltage-resisting layer being used to reduce the peak electric field at the bottom of the gate structure; A source electrode is formed at the first surface; A drain electrode is formed at the second surface.

12. The method of manufacturing a semiconductor device according to Claim 11, wherein Forming the second trench in the first trench comprises: Forming the second trench in the first trench, the vertical projection area of the second trench on the first surface being smaller than the vertical projection area of the first trench on the first surface.

13. The method of manufacturing a semiconductor device according to Claim 12, wherein Forming the second trench in the first trench comprises: Forming the second trench in the first trench, the fourth sidewall and the second sidewall in the second trench having a vertical projection that coincides on the first surface.

14. The method of manufacturing a semiconductor device according to Claim 11, wherein Forming the gate structure in the first trench comprises: Forming the insulating layer at least at the bottom of the first trench and the first sidewall; Forming the gate electrode on the side of the insulating layer and the voltage-resisting layer in the first trench facing the gate structure, wherein, in the direction perpendicular to the second surface and pointing to the first surface, the distance between the first sidewall and the gate electrode is smaller than the distance between the gate electrode and the second sidewall.

15. The method of manufacturing a semiconductor device according to Claim 14, wherein The voltage-resisting layer is a high-resistivity material, the voltage-resisting layer having better insulation performance than the insulating layer, and forming the insulating layer at least at the bottom of the first trench and the first sidewall comprises: Forming the insulating layer on the side of the first sidewall, the bottom of the first trench, and the voltage-resisting layer facing the gate structure.

16. The method of manufacturing a semiconductor device according to any one of claims 11 to 13, wherein Before forming the voltage-resisting layer in the second trench and the first trench, the method further comprises: Forming a second region at the bottom of the second trench and the third sidewall, wherein the second region has the same conductivity type as the well region, and the doping concentration of the second region is greater than the doping concentration of the well region.

17. The method of manufacturing a semiconductor device according to Claim 16, wherein Forming the second region at the bottom of the second trench and the third sidewall comprises: forming a first part of the second region on the third sidewall by a slanted ion implantation process; forming a second part of the second region on the bottom of the second trench by a vertical ion implantation process.

18. The method of manufacturing a semiconductor device according to any one of claims 11-13, wherein forming a second trench in the first trench comprises: forming at least two sub-trenches in the first trench, wherein the sub-trenches comprise oppositely arranged fifth sidewalls and sixth sidewalls; the sixth sidewalls of the sub-trenches and the second sidewall overlap in the vertical projection on the first surface; in the direction in which the first surface points to the second surface, the sub-trenches are arranged adjacently, and the spacing between the two sidewalls of the sub-trenches decreases successively.

19. A power module, characterized by a substrate for carrying the semiconductor device.

20. A power conversion circuit, comprising: the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device as claimed in any one of claims 1-10, the semiconductor device being electrically connected to the circuit board.

21. A vehicle characterized by a load and the power conversion circuit as claimed in claim 20, the power conversion circuit being used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current, or converting direct current into alternating current before inputting to the load.

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