Display panel mother board, display panel and display device

Abstract

The utility model provides a display panel mother board, a display panel and a display device. The display panel mother board comprises a substrate and a plurality of display units distributed on the substrate in an array mode. The display panel mother board further comprises first common lines which are distributed in a mode of surrounding each display unit and are connected with the adjacent display units, and each display unit comprises a display area and a non-display area surrounding the display area. The display area comprises a plurality of data lines and a plurality of gate lines which intersect with the gate lines in an insulated mode. The non-display area includes: a gate driving circuit coupled to a plurality of gate lines and a gate driving line; a plurality of monitoring output voltage lines distributed around the display area; and a plurality of electrostatic protection structures through which each monitoring output voltage line can be connected with the plurality of data lines or gate driving circuits, and both ends of each monitoring output voltage line are electrically connected to the first common line.

Description

Technical Field

[0001] This utility model relates to the field of liquid crystal displays, and in particular to a display panel motherboard, a display panel, and a display device. Background Technology

[0002] Furthermore, in the manufacturing process of display panels, a single display panel is typically obtained by cutting a motherboard containing multiple display panels. The simultaneous fabrication of multiple display panels on a single motherboard often leads to static electricity buildup. Moreover, static electricity is also generated during the production and transportation of individual display panels. When this static electricity buildup becomes excessive, it can easily cause static electricity phenomena, directly affecting the production yield of each display panel. Therefore, improvements are needed. Utility Model Content

[0003] This utility model was made in view of the above-mentioned problems, and its purpose is to provide a display panel motherboard, a display panel and a display device to solve the above-mentioned problems existing in the prior art.

[0004] One embodiment of this utility model provides a display panel motherboard, which includes a substrate and a plurality of display units arrayed on the substrate. The display panel motherboard includes a first common line distributed around each of the display units and connecting adjacent display units. Each display unit includes a display area and a non-display area surrounding the display area. The display area includes: a plurality of data lines extending along a first direction; and a plurality of gate lines intersecting the data lines insulated from them and extending along a second direction. The non-display area includes: a gate driving circuit coupled to the plurality of gate lines and the gate driving lines; a plurality of monitoring output voltage lines distributed around the display area; and a plurality of electrostatic discharge (ESD) protection structures. Each monitoring output voltage line can be connected to the plurality of data lines or the gate driving circuit through the ESD protection structure, and both ends of each monitoring output voltage line are electrically connected to the first common line, so that static electricity inside the display unit flows to the first common line through the ESD protection structure and the monitoring output voltage lines.

[0005] Preferably, in one embodiment, the plurality of display units are spaced apart from each other and interconnected by the first common line surrounding each of the display units.

[0006] Preferably, in one embodiment, the first common line includes a plurality of vertical common lines, a plurality of horizontal common lines, and a plurality of connecting portions. Two vertical common lines and two horizontal common lines are arranged around each of the display units. The two horizontal common lines of two adjacent display units are connected through the connecting portions, or the two vertical common lines of two adjacent display units are connected through the connecting portions.

[0007] Preferably, in one embodiment, the connecting part is made of a single metal layer and is connected to the horizontal common line and the vertical common line through a transition point; or, the connecting part is a structure in which a first metal layer and a second metal layer of different layers are short-connected.

[0008] One embodiment of this utility model provides a display panel, which includes a display area and a non-display area surrounding the display area. The display area includes: multiple data lines extending along a first direction; multiple gate lines intersecting the data lines insulated from them and extending along a second direction; and the non-display area includes: a gate driving circuit coupled to the multiple gate lines and the gate driving lines; multiple monitoring output voltage lines distributed around the display area; multiple electrostatic discharge (ESD) protection structures; and a first common line surrounding the non-display area. Each monitoring output voltage line can be connected to the multiple data lines or the gate driving circuit through the ESD protection structure, and both ends of each monitoring output voltage line are electrically connected to the first common line, so that static electricity inside the display panel flows to the first common line through the ESD protection structure and the monitoring output voltage lines.

[0009] Preferably, in one embodiment, the plurality of monitoring output voltage lines are not connected to each other.

[0010] Preferably, in one embodiment, the plurality of monitoring output voltage lines include a first monitoring output voltage line and a second monitoring output voltage line extending along the first direction, and a third monitoring output voltage line and a fourth monitoring output voltage line extending along the second direction. The first monitoring output voltage line and the second monitoring output voltage line are located on opposite sides of the display area in the second direction, and the third monitoring output voltage line and the fourth monitoring output voltage line are located on opposite sides of the display area in the first direction. The first monitoring output voltage line and the second monitoring output voltage line can be connected to the gate driving line through the electrostatic discharge protection structure, and the third monitoring output voltage line and the fourth monitoring output voltage line can be connected to each of the plurality of data lines through the electrostatic discharge protection structure.

[0011] Preferably, in one embodiment, a peripheral common line is further included, which is arranged around the display area and connected to the fan-out area located in the non-display area, and the monitoring output voltage line can be connected to the peripheral common line through the electrostatic protection structure.

[0012] Preferably, in one embodiment, solder joints are pre-installed on the plurality of monitoring output voltage lines, at the crossings between the plurality of data lines or the plurality of gate lines, and at the crossings between the plurality of monitoring output voltage lines. After the solder joints are laser-welded, the monitoring output voltage lines can be electrically connected to any one of the plurality of data lines or the plurality of gate lines.

[0013] One embodiment of the present invention also provides a display device, which includes the display panel described above. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of the display panel motherboard involved in this utility model.

[0016] Figure 2 (a) is a structural schematic diagram showing an example of a connecting part in the motherboard of the display panel. Figure 2 (b) is a structural schematic diagram showing another example of a connecting part in the motherboard of the display panel.

[0017] Figure 3 This is a schematic diagram illustrating the structure of the display unit in the display panel motherboard.

[0018] Figure 4 This is a schematic diagram of the structure of the display panel involved in this utility model.

[0019] Figure 5 This is a schematic diagram illustrating an example of a detection gate line on a display panel.

[0020] Figure 6 This is a schematic diagram illustrating an example of detecting a data cable. Detailed Implementation

[0021] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0022] The following disclosure provides numerous different embodiments for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0023] The following description, in conjunction with the accompanying drawings, details the display panel motherboard, display panel, and display device provided by this utility model.

[0024] First, refer to Figures 1 to 3 The present invention will provide a detailed description of the display panel motherboard 100 provided by this utility model. For example... Figure 1 As shown, the display panel motherboard 100 of this utility model includes a substrate 10, a plurality of display units 20 arrayed on the substrate 10, and a plurality of first common lines 30. The substrate 10 may be a glass substrate, on which a plurality of ground terminals (not shown) are provided. In addition, in this embodiment, an example of four display units 20 arranged in 2 rows and 2 columns is shown, but it is not limited to this.

[0025] Multiple first common lines 30 are distributed on the substrate 10 in a manner surrounding each display unit 20 and connected to a ground terminal. Specifically, as Figure 1 and Figure 2 As shown, the multiple first common lines 30 include multiple vertical common lines 31, multiple horizontal common lines 33, and multiple connecting parts 35.

[0026] Multiple vertical common lines 31 and multiple horizontal common lines 33 are arranged perpendicularly to each other. Two adjacent vertical common lines 31 (e.g., vertical common lines 311 and 313 hereinafter) and two adjacent horizontal common lines 33 (e.g., horizontal common lines 331 and 333 hereinafter) surround a display unit 20. These adjacent vertical common lines 31 and adjacent horizontal common lines 33 are electrically connected to other vertical common lines 31 and horizontal common lines 33 via multiple connecting parts 35. This allows static electricity generated during manufacturing to be discharged to the grounding terminal via the first common line 30, thereby ensuring that the display unit 20 on the display panel motherboard 100 is not damaged by static electricity. In this way, when static charge accumulates in a display unit 20 or the display panel motherboard 100, the charge can be safely released to the outside through the first common line 30. Furthermore, when external charge comes into contact with the first common line 30, some of the charge is conducted to the grounding terminal by the first common line 30, reducing the risk of external charge entering the display unit 20.

[0027] like Figure 1 As shown, the plurality of vertical common lines 31 include a first vertical common line 311, a second vertical common line 313, a third vertical common line 315, and a fourth vertical common line 317; the plurality of horizontal common lines 33 include a first horizontal common line 331, a second horizontal common line 333, a third horizontal common line 335, and a fourth horizontal common line 337; the plurality of display units 20 include a first display unit 20a, a second display unit 20b, a third display unit 20c, and a fourth display unit 20d.

[0028] In the first display unit 20a, the adjacent first vertical common line 311 and second vertical common line 313 are located on opposite sides of the first display unit 20a, and the first horizontal common line 331 and second horizontal common line 333 are located on the other two sides of the first display unit 20a and intersect perpendicularly with the first vertical common line 311 and second vertical common line 313.

[0029] Similarly, in the second display unit 20b, the adjacent third vertical common line 315 and fourth vertical common line 317 are located on opposite sides of the second display unit 20b, and the third horizontal common line 335 and fourth horizontal common line 337 are located on the other two sides of the second display unit 20b and intersect perpendicularly with the third vertical common line 315 and fourth vertical common line 317.

[0030] The plurality of connecting parts 35 include a first horizontal connecting part 351, a second horizontal connecting part 353, a first vertical connecting part 355, and a second vertical connecting part 357.

[0031] The first horizontal common line 331 and the third horizontal common line 335 are connected through the first horizontal connecting part 351, and the second horizontal common line 333 and the fourth horizontal common line 337 are connected through the second horizontal connecting part 353, so that the first display unit 20a and the second display unit 20b are electrically connected.

[0032] Similarly, the third display unit 20c is electrically connected to the first display unit 20a via the first vertical connection portion 355 and the second vertical connection portion 357.

[0033] In this embodiment, the connecting part 35 can be a single horizontal line structure, a vertical line structure, or a grid-shaped structure, which can be set according to actual needs.

[0034] In one embodiment, such as Figure 2 As shown in (a), the connection part 35 is made of a single metal layer and is connected to the horizontal common line and the vertical common line through the layer transfer point to prevent static electricity from occurring.

[0035] In other embodiments, such as Figure 2As shown in (b), the connection part 35 can be a structure in which the first metal layer and the second metal layer of different layers are short-circuited to ensure that static electricity can be discharged quickly and effectively.

[0036] Furthermore, such as Figure 3 As shown, the first display unit 20a will be described as an example. The first display unit 20a includes a display area AA and a non-display area NAA surrounding the display area. Multiple gate lines G and multiple data lines D are disposed in the display area AA, and the multiple data lines D and the multiple gate lines G are intersected and insulated from each other. Hereinafter, for ease of explanation, the extending direction of the data lines D will be referred to as the first direction, and the extending direction of the gate lines G will be referred to as the second direction.

[0037] Furthermore, in this embodiment, the non-display area NAA includes a first gate driving circuit 21 and a second gate driving circuit 22. The first gate driving circuit 21 and the second gate driving circuit 22 are used to provide first gate driving signals and second gate driving signals to multiple gate lines G via first gate driving lines 211 and second gate driving lines 221, respectively. The first gate driving circuit 21 and the second gate driving circuit 22 are located on opposite sides of the display area AA in a second direction. In addition, the non-display area NAA also includes a fan-out region 23 for driving multiple data lines D. The fan-out region 23 is distributed along the second direction in the non-display area NAA and is located on the side close to the display area AA.

[0038] The non-display area (NAA) also includes multiple output voltage lines 24 distributed around the display area (AA). These output voltage lines 24 are used to monitor relevant parameters of the output signal of the display unit 20 to ensure the quality and stability of the display effect. Figure 3 As shown in this embodiment, four monitoring output voltage lines 24 are arranged around the display area AA and distributed in a "U" shape, but it is not limited to this.

[0039] The monitoring output voltage line 24 includes a first monitoring output voltage line 241 and a second monitoring output voltage line 242 extending along a first direction, and a third monitoring output voltage line 243 and a fourth monitoring output voltage line 244 extending along a second direction. The first monitoring output voltage line 241 and the second monitoring output voltage line 242 are located on opposite sides of the display area AA in the second direction, while the third monitoring output voltage line 243 and the fourth monitoring output voltage line 244 are located on the other opposite sides of the display area AA in the first direction. More specifically, in the second direction, the first monitoring output voltage line 241 is located between the display area AA and the first gate driving circuit 21, and the second monitoring output voltage line 242 is located between the display area AA and the second gate driving circuit 22. In the first direction, the fourth monitoring output voltage line 244 is located between the display area AA and the fan-out area 23. That is, the first monitoring output voltage line 241 and the second monitoring output voltage line 242 are spaced apart, and the third monitoring output voltage line 243 and the fourth monitoring output voltage line 244 are spaced apart and intersect the first monitoring output voltage line 241 and the second monitoring output voltage line 242 perpendicularly.

[0040] Furthermore, the two ends of the first monitoring output voltage line 241, the second monitoring output voltage line 242, the third monitoring output voltage line 243, and the fourth monitoring output voltage line 244 are electrically connected to the first common line 30. More specifically, one end of the first monitoring output voltage line 241 and the second monitoring output voltage line 242 near the fan-out region 23 is connected to the second horizontal common line 333 of the first common line 30, and the other end is connected to the first horizontal common line 331 of the first common line 30. Additionally, during the manufacturing process of the display panel motherboard 100, the shorting bar 231 located in the fan-out region 23 can short-circuit all data lines D together. Figure 1 and Figure 3 The dashed box shown indicates the part that needs to be cut off during the final packaging process (including the corresponding substrate and shorting bar), so that all data lines D are no longer shorted. At the same time, ACF can be encapsulated at the exposed line locations to achieve electrical connection between the display panel and the external PCB.

[0041] Furthermore, the two ends of the third monitoring output voltage line 243 and the fourth monitoring output voltage line 244 are respectively connected to the first vertical common line 311 and the second vertical common line 313. In addition, the first monitoring output voltage line 241, the second monitoring output voltage line 242, the third monitoring output voltage line 243, and the fourth monitoring output voltage line 244 are not connected to each other.

[0042] In addition, such as Figure 3As shown, the non-display area (NAA) also includes multiple electrostatic discharge (ESD) protection structures 25. Each ESD protection structure 25 consists of two diodes. When both voltage levels are within the normal range, both diodes are in the off state, having virtually no impact on the circuit. When an ESD pulse occurs, one of the diodes will conduct under forward bias. The first monitoring output voltage line 241 and the second monitoring output voltage line 242 can be connected to the first gate drive line 211 and the second gate drive line 221, respectively, through the multiple ESD protection structures 25. The third monitoring output voltage line 243 and the fourth monitoring output voltage line 244 can be connected to each data line D through the multiple ESD protection structures 25. Thus, the monitoring output voltage line 24 can be connected to the gate drive line and each data line D through the ESD protection structures 25.

[0043] Therefore, when static electricity is generated during the manufacturing process of the display panel motherboard 100, the current can be conducted from the gate drive line and the data line D to the monitoring output voltage line 24, and then directly from the monitoring output voltage line 24 to the first common line 30, and conducted to the ground terminal. This reduces the risk of ESD in the display unit 20, strengthens the ESD resistance in the process, and thus increases production efficiency.

[0044] In addition, the display unit 20 also includes a peripheral common line 40. The peripheral common line 40 is disposed in the non-display area NAA and distributed around the display area AA, and is electrically connected to the peripheral common line 40 via a shorting bar 231 on the side closest to the fan-out area 23. Specifically, in the second direction, the peripheral common line 40 is located between the display area AA and the first gate driving circuit 21 or the second gate driving circuit 22; more specifically, it is located between the first monitoring output voltage line 241 and the first gate driving circuit 21, or between the second monitoring output voltage line 242 and the second gate driving circuit 22. Furthermore, in the first direction, the peripheral common line 40 is located between the fourth monitoring output voltage line 244 and the fan-out area 23 on the side closest to the fan-out area.

[0045] Furthermore, the third monitoring output voltage line 243 and the fourth monitoring output voltage line 244 can be connected to the peripheral common line 40 via multiple electrostatic discharge (ESD) protection structures 25. In this embodiment, an example is shown where the third monitoring output voltage line 243 and the fourth monitoring output voltage line 244 are each connected to the peripheral common line 40 via an ESD protection structure 25 near the first gate drive circuit 21 and the second gate drive circuit 22. This further reduces the risk of ESD occurring within the display unit 20.

[0046] Therefore, based on the above, this utility model can provide a display panel motherboard 100 that can guarantee antistatic capability during the manufacturing process.

[0047] Furthermore, after a series of tests are performed on the display panel motherboard 100, it will be cut into multiple display panels 200 along a preset cutting line. The cutting method is similar to existing technology and will not be described in detail here. At this time, the first common line 30 is cut off. Figure 4 As shown, in the display panel 200, the first common line 30 is removed, and the shorting bar 231 is also cut off. The monitoring output voltage line 24 is connected to a pre-set test pad 26. Specifically, the first monitoring output voltage line 241 and the second monitoring output voltage line 242 are connected to the pre-set test pad 26. Other structures are largely the same as before cutting. Furthermore, the monitoring output voltage line 24 is not directly connected to any signal lines (e.g., data lines D, gate lines G, and gate drive lines 211, 221, etc.) in the display panel 200. In addition, on the monitoring output voltage line 24, there are pre-set solderable points W at the crossover points between each gate line G, each data line D, and between the monitoring output voltage lines 24 themselves.

[0048] Figure 5 and Figure 6 This is a schematic diagram illustrating the signal detection process on the display panel. Wherein, Figure 5 This is a schematic diagram illustrating an example of detecting gate line G. Figure 6 A schematic diagram of an example of a detection data line D is shown.

[0049] like Figure 5 When it is necessary to detect, for example, the signal waveform of the gate line G1, which serves as the starting point, laser welding can be performed on the solderable point W corresponding to the gate line G1 on the second monitoring output voltage line 242 to electrically connect the gate line G1 to the second monitoring output voltage line 242. Then, the corresponding signal waveform can be detected using the test pad 26.

[0050] like Figure 6 As shown, when it is necessary to detect the signal waveform of data line D1, which serves as the starting point, laser soldering can be performed on the solderable point W corresponding to data line D1 on the fourth monitoring output voltage line 244 near the test pad 26, electrically connecting data line D1 to the fourth monitoring output voltage line 244. Next, laser soldering is performed on the solderable point W at the junction of the fourth monitoring output voltage line 244 and the first monitoring output voltage line 241, electrically connecting the fourth monitoring output voltage line 244 to the first monitoring output voltage line 241. Thus, the corresponding signal waveform can also be detected using the test pad 26.

[0051] Therefore, with this setting, it is possible to detect the status of any level gate drive signal and any level data signal in the panel in real time without affecting the normal operation of the display panel 200.

[0052] Furthermore, similarly to the display panel motherboard 100, the monitoring output voltage line 24 in the display panel 200 can also function as a floating common electrode to which multiple electrostatic discharge (ESD) protection structures 25 are connected. For example, when static electricity, abnormal voltage spikes, or other unwanted energy accumulation occurs in the circuitry of the display panel 200, such static electricity can be conducted from the gate drive line and data line to the monitoring output voltage line 24, and then flow from the monitoring output voltage line 24 to the peripheral common line 40 and discharge. This reduces the risk of ESD within the display panel 200, preventing damage to sensitive components in the display panel 200. Simultaneously, it saves routing space required for additional discharge paths.

[0053] Therefore, based on the above, this utility model can provide a display panel that can detect the signal status inside the panel in real time and ensure anti-static capability.

[0054] Based on the same concept, this utility model also provides a display device, which includes the aforementioned display panel. Therefore, this display device has the same beneficial effects as the aforementioned display panel, which will not be repeated here.

[0055] Furthermore, in this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0056] All aspects of the embodiments disclosed herein are illustrative and should not be construed as limiting. Therefore, the technical scope of this utility model is not limited to the above embodiments, but is defined based on the claims. Furthermore, all modifications are included within the meaning and scope equivalent to the claims.

Claims

1. A display panel motherboard, comprising a substrate and a plurality of display units arrayed on the substrate, characterized in that, This includes a first common line, which is distributed around each of the display units and connects adjacent display units. Each of the display units includes a display area and a non-display area surrounding the display area. The display area includes: Multiple data cables extend along the first direction; as well as Multiple gate lines, insulated from the data lines, intersect and extend along a second direction. The non-display area includes: A gate driving circuit, which is coupled to the plurality of gate lines and the gate driving lines; Multiple monitoring output voltage lines distributed around the display area; and Multiple electrostatic protection structures, Each of the aforementioned monitoring output voltage lines can be connected to the plurality of data lines or the gate drive circuit through the electrostatic protection structure, and Both ends of each of the monitoring output voltage lines are electrically connected to the first common line, so that the static electricity inside the display unit flows to the first common line through the electrostatic protection structure and the monitoring output voltage lines.

2. The display panel motherboard according to claim 1, characterized in that, The plurality of display units are spaced apart from each other and interconnected by the first common line surrounding each of the display units.

3. The display panel motherboard according to claim 2, characterized in that, The first common line includes multiple vertical common lines, multiple horizontal common lines, and multiple connecting parts. Two vertical common lines and two horizontal common lines are arranged around each of the display units. The two horizontal common lines of two adjacent display units are connected through the connecting part, or the two vertical common lines of two adjacent display units are connected through the connecting part.

4. The display panel motherboard according to claim 3, characterized in that, The connecting part is made of a single metal layer and is connected to the horizontal and vertical common lines through a transition point; or... The connecting part is a structure in which a first metal layer and a second metal layer of different layers are short-connected.

5. A display panel, characterized in that, Includes a display area and a non-display area surrounding the display area. The display area includes: Multiple data cables extend along the first direction. Multiple gate lines, insulated from the data lines, intersect and extend along a second direction; and The non-display area includes: A gate driving circuit, which is coupled to the plurality of gate lines and the gate driving lines; Multiple monitoring output voltage lines distributed around the display area; Multiple electrostatic protection structures; and The first common line surrounds the non-display area. Each of the aforementioned monitoring output voltage lines can be connected to the plurality of data lines or the gate drive circuit through the electrostatic protection structure, and Both ends of each of the monitoring output voltage lines are electrically connected to the first common line, so that static electricity inside the display panel flows to the first common line through the electrostatic protection structure and the monitoring output voltage lines.

6. The display panel according to claim 5, characterized in that, The multiple monitoring output voltage lines are not connected to each other.

7. The display panel according to claim 5, characterized in that, The plurality of monitoring output voltage lines include a first monitoring output voltage line and a second monitoring output voltage line extending along the first direction, and a third monitoring output voltage line and a fourth monitoring output voltage line extending along the second direction. The first monitoring output voltage line and the second monitoring output voltage line are located on opposite sides of the display area in the second direction. The third monitoring output voltage line and the fourth monitoring output voltage line are located on opposite sides of the display area in the first direction. The first monitoring output voltage line and the second monitoring output voltage line can be connected to the gate drive line through the electrostatic protection structure. The third and fourth monitoring output voltage lines can be connected to each of the multiple data lines through the electrostatic protection structure.

8. The display panel according to claim 5, characterized in that, It also includes peripheral common lines, which are arranged around the display area and connected to the fan-out area located in the non-display area. The monitoring output voltage line can be connected to the external common line through the electrostatic protection structure.

9. The display panel according to claim 8, characterized in that, Solder joints are pre-installed on the multiple monitoring output voltage lines, at the crossings between the multiple data lines or the multiple gate lines, and at the crossings between the multiple monitoring output voltage lines. After the welding point is laser welded, the monitoring output voltage line can be electrically connected to any one of the multiple data lines or the multiple gate lines.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 5 to 9.

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