Hardware error detection and correction system for dual-core lockstep processor

Abstract

The utility model discloses a dual-core lockstep processor hardware error detection and correction system, which relates to the technical field of processors and comprises a master processor, a slave processor, an error monitoring module, a backtracking address generation module and an instruction flushing backtracking control module. The error monitoring module is used for comparing and monitoring the main processor and the slave processor, and when the output data of the main processor and the slave processor are different, a dual-core lock step error signal is triggered; the instruction flushing backtracking control module is used for sending an assembly line emptying signal and an instruction backtracking signal when receiving the error signal; the backtracking address generation module is used for generating a backtracking instruction address when receiving the error signal; and when receiving the assembly line emptying signal and the instruction backtracking signal, the main processor and the slave processor are used for emptying the instruction operated by the current assembly line and then obtaining the instruction again according to the address of the backtracking instruction to realize error correction. The scheme does not depend on software, hardware self-inspection and self-correction can be completed, and the recovery time required for detecting and recovering the transient fault is greatly shortened.

Description

Technical Field

[0001] This utility model relates to the field of processor technology, and in particular to a hardware error detection and correction system for a dual-core lockstep processor. Background Technology

[0002] In existing dual-core lockstep technology, the master and slave processors execute the same instructions and monitor their states in real time. When the states of the two processors become inconsistent, a warning signal is issued, and the error controller and interrupt controller fetch instructions from previously stored safety checkpoints in the software to complete system recovery. Current dual-core lockstep technology relies heavily on software, and fault recovery often requires software intervention, resulting in lengthy recovery times when detecting and recovering from transient faults. Utility Model Content

[0003] To address the shortcomings of existing technologies, this invention provides a hardware error detection and correction system for a dual-core lockstep processor. It does not rely on software and can perform hardware self-testing and self-correction, restoring the system to a safe state and significantly reducing the recovery time required for detecting and recovering from transient faults.

[0004] In order to achieve the purpose of this utility model, the following solution is proposed:

[0005] A hardware error detection and correction system for a dual-core lockstep processor includes a master processor and a slave processor, and also includes an error monitoring module, a backtracking address generation module, and an instruction flushing backtracking control module.

[0006] The error monitoring module includes a comparator for comparing and monitoring the main processor and the slave processor. When the output data of the main processor and the slave processor are different, a dual-core lockstep error signal is triggered.

[0007] The instruction flushing and backtracking control module includes a control signal distributor, which is used to issue a pipeline clear signal and an instruction backtracking signal when a dual-core lockstep error signal is received;

[0008] The backtracking address generation module includes a triple-modulus redundant circuit, which is used to generate a backtracking instruction address when a dual-core lockstep error signal is received;

[0009] The master processor and slave processor are used to clear the instructions currently running in the pipeline when they receive pipeline clear signals and instruction backtracking signals, and then re-acquire instructions based on the backtracking instruction address to achieve error correction.

[0010] Furthermore, the error monitoring module is used to compare and monitor the data in the pipeline registers of the main processor and the slave processor.

[0011] The beneficial effects of this utility model are as follows:

[0012] 1. Error correction is completed by instruction backtracking of the dual-core lockstep processor. The recovery process only requires hardware and does not rely on other software, which reduces the error detection and correction time and enhances the reliability of the processor.

[0013] 2. It is accomplished by comparing the registers of each pipeline stage within the dual-core lockstep processor, thus achieving high real-time performance. Attached Figure Description

[0014] Figure 1 A schematic diagram of the connection relationship of the dual-core lockstep processor hardware error detection and correction system is shown. Detailed Implementation

[0015] like Figure 1 As shown, this embodiment provides a hardware error detection and correction system for a dual-core lockstep processor, including a main processor, a slave processor, an error monitoring module, a backtracking address generation module, and an instruction flushing backtracking control module.

[0016] The master processor and slave processor are in dual-core lockstep mode. The error monitoring module includes a comparator and is connected to the master processor and slave processor. It is used to compare and monitor the data in the pipeline registers of the master processor and slave processor. When the output data of the master processor and slave processor are different, a dual-core lockstep error signal is triggered. The error monitoring module is used to send the dual-core lockstep error signal to the instruction flushing backtracking control module and the backtracking address generation module.

[0017] The instruction flushing and backtracking control module includes a control signal distributor. An error monitoring module is connected to the instruction flushing and backtracking control module. The instruction flushing and backtracking control module is connected to the master processor and the slave processor. When the instruction flushing and backtracking control module receives a dual-core lockstep error signal, it sends a pipeline clear signal and an instruction backtracking signal to the master processor and the slave processor.

[0018] The backtracking address generation module includes a triple-modular redundancy circuit. The error monitoring module is connected to the backtracking address generation module, which is connected to the master processor and the slave processor. When the backtracking address generation module receives a dual-core lockstep error signal, it generates a backtracking instruction address and sends the backtracking instruction address to the master processor and the slave processor.

[0019] When the main processor and slave processor receive pipeline clear signals and instruction backtracking signals, they are used to clear the instructions currently running in the pipeline, and then re-acquire instructions based on the backtracking instruction address to achieve hardware error correction in the dual-core lockstep system.

[0020] This system can perform hardware self-testing and self-correction without relying on software, restoring the system to a safe state. This significantly reduces the recovery time required for detecting and recovering from transient faults, and improves the reliability of the processor.

[0021] The above embodiments are only used to illustrate the technical concept and features of this utility model, and are not intended to be unique or to limit this utility model. Those skilled in the art should understand that various changes or equivalent substitutions made to this utility model without departing from its scope are all within the protection scope of this utility model.

Claims

1. A hardware error detection and correction system for a dual-core lockstep processor, comprising a main processor and a slave processor, characterized in that, It also includes an error monitoring module, a backtracking address generation module, and an instruction flushing backtracking control module; The error monitoring module is connected to the master processor and the slave processor, and is also connected to the backtrack address generation module and the instruction flushing backtrack control module; The backtracking address generation module is connected to the master processor and the slave processor; The instruction flushing and backtracking control module connects the main processor and the slave processor; The error monitoring module includes a comparator for comparing and monitoring the main processor and the slave processor. When the output data of the main processor and the slave processor are different, a dual-core lockstep error signal is triggered. The instruction flushing and backtracking control module includes a control signal distributor, which is used to issue a pipeline clear signal and an instruction backtracking signal when a dual-core lockstep error signal is received; The backtracking address generation module includes a triple-modulus redundant circuit, which is used to generate a backtracking instruction address when a dual-core lockstep error signal is received; The master processor and slave processor are used to clear the instructions currently running in the pipeline when they receive pipeline clear signals and instruction backtracking signals, and then re-acquire instructions based on the backtracking instruction address to achieve error correction.

2. The dual-core lockstep processor hardware error detection and correction system according to claim 1, characterized in that, The error monitoring module is used to compare and monitor the data in the pipeline registers of the main processor and the slave processor.

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