Semiconductor device

Abstract

The present disclosure provides a semiconductor device including: a semiconductor layer having a first main surface and a second main surface opposite the first main surface; a first metal layer on the first main surface; and a second metal layer on the second main surface; the semiconductor layer includes: a base layer; a first doped silicon layer located between the base layer and the first metal layer; the second doped silicon layer is positioned between the base electrode layer and the second metal layer; the grid electrode layer extends from the first doped silicon layer, penetrates through the base electrode layer and extends to the second doped silicon layer; and the first insulating dielectric layer at least isolates the gate layer from the base layer, the first doped silicon layer and the second doped silicon layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device technology, and more particularly to a bidirectional semiconductor device with self-protection function. Background Technology

[0002] Traditional semiconductor devices have limitations in current control and voltage blocking, especially in high-voltage and high-power applications where device stability and reliability become critical considerations.

[0003] Common unidirectional blocking devices, as BDS (Bidirectional Switches), require a large chip area to achieve bidirectional current control and voltage blocking. This not only increases manufacturing costs but also limits the development of miniaturization and integration of the devices.

[0004] Existing semiconductor devices suffer from problems such as large chip area (traditional unidirectional blocking devices need to be used in pairs to achieve bidirectional blocking function, which leads to a significant increase in chip area), difficulty in balancing resistance and withstand voltage performance (while pursuing high withstand voltage, it is often difficult to take into account low resistance characteristics, which affects the overall performance of the device), and lack of self-protection function (the device is easily damaged under instantaneous high voltage or abnormal conditions, and there is a lack of effective self-protection mechanism). Utility Model Content

[0005] This disclosure provides a semiconductor device, including:

[0006] A semiconductor layer having a first main surface and a second main surface opposite to the first main surface;

[0007] The first metal layer located on the first main surface;

[0008] A second metal layer located on the second main surface;

[0009] The semiconductor layer includes:

[0010] Base layer;

[0011] A first doped silicon layer located between the base layer and the first metal layer;

[0012] A second doped silicon layer located between the base layer and the second metal layer;

[0013] A gate layer extends from the first doped silicon layer, through the base layer, and to the second doped silicon layer;

[0014] The first insulating dielectric layer isolates at least the gate layer from the base layer, the first doped silicon layer, and the second doped silicon layer.

[0015] According to at least one embodiment of the semiconductor device of the present disclosure, in an extension direction from a first main surface to a second main surface, a gate layer is at least partially located within a first doped silicon layer and / or at least partially located within a second doped silicon layer.

[0016] According to at least one embodiment of the semiconductor device disclosed herein, the first doped silicon layer includes a first doped region and a second doped region, wherein the doping concentration of the first doped region is greater than the doping concentration of the second doped region, and the first doped region is closer to the first metal layer than the second doped region.

[0017] According to at least one embodiment of the semiconductor device disclosed herein, the second doped silicon layer includes a third doped region and a fourth doped region, wherein the doping concentration of the third doped region is greater than that of the fourth doped region, and the third doped region is closer to the second metal layer than the fourth doped region.

[0018] According to at least one embodiment of the semiconductor device of the present disclosure, the base layer is a doped silicon layer, and the doping concentration of the base layer is greater than the doping concentration of the first doped silicon layer and the doping concentration of the second doped silicon layer.

[0019] According to at least one embodiment of the semiconductor device of the present disclosure, the base layer includes a fifth doped region and two sixth doped regions, the fifth doped region being located between the two sixth doped regions, and the two sixth doped regions being adjacent to a second doped region and a fourth doped region, respectively; the doping concentration of the fifth doped region is greater than the doping concentration of the sixth doped region.

[0020] According to at least one embodiment of the semiconductor device of the present disclosure, the first doped silicon layer and the second doped silicon layer have the same doping type.

[0021] According to at least one embodiment of the semiconductor device of the present disclosure, the doping type of the base layer is opposite to the doping type of the first doped silicon layer and the second doped silicon layer.

[0022] According to at least one embodiment of the semiconductor device of the present disclosure, the second doped region has a uniform doping distribution or a linear doping distribution.

[0023] In a semiconductor device according to at least one embodiment of the present disclosure, the fourth doped region has a uniform doping distribution or a linear doping distribution.

[0024] In a semiconductor device according to at least one embodiment of the present disclosure, the gate layer is a polycrystalline silicon layer.

[0025] A semiconductor device according to at least one embodiment of the present disclosure further includes a gate potential lead-out structure;

[0026] The gate potential lead-out structure includes a first lead-out layer in contact with the gate layer and a second lead-out layer in contact with the first lead-out layer;

[0027] The first insulating dielectric layer isolates the first lead-out layer from the first doped silicon layer and the first metal layer, or the first insulating dielectric layer isolates the first lead-out layer from the second doped silicon layer and the second metal layer;

[0028] Both the first lead-out layer and the second lead-out layer are made of metal.

[0029] A semiconductor device according to at least one embodiment of the present disclosure further includes a second insulating dielectric layer;

[0030] The second lead-out layer is located on the same layer as the first metal layer or the second metal layer, and the second insulating dielectric layer at least isolates the second lead-out layer from the first metal layer or the second metal layer.

[0031] According to at least one embodiment of the semiconductor device of the present disclosure, the first metal layer and / or the second metal layer include a via-filling metal layer and a surface metal layer, the first lead-out layer includes at least a portion located in the same layer as the via-filling metal layer, and the second lead-out layer is located in the same layer as the surface metal layer.

[0032] A semiconductor device according to at least one embodiment of the present disclosure further includes a base potential lead-out structure;

[0033] The base potential lead-out structure includes a third lead-out layer in contact with the base layer, a fourth lead-out layer in contact with the third lead-out layer, and a third insulating dielectric layer.

[0034] The third insulating dielectric layer isolates the third lead-out layer from the first doped silicon layer and the first metal layer, or the third insulating dielectric layer isolates the third lead-out layer from the second doped silicon layer and the second metal layer;

[0035] Both the third lead-out layer and the fourth lead-out layer are made of metal.

[0036] According to at least one embodiment of the semiconductor device of the present disclosure, the base potential lead-out structure further includes a fourth insulating dielectric layer;

[0037] The fourth lead-out layer is located on the same layer as the first metal layer or the second metal layer, and the fourth insulating dielectric layer at least isolates the fourth lead-out layer from the first metal layer or the second metal layer.

[0038] According to at least one embodiment of the semiconductor device of the present disclosure, the third lead-out layer extends from the base layer and through the first doped silicon layer or through the second doped silicon layer to contact the fourth lead-out layer.

[0039] According to at least one embodiment of the semiconductor device of the present disclosure, the first metal layer and / or the second metal layer includes a via-filling metal layer and a surface metal layer, the third lead-out layer includes at least a portion located in the same layer as the via-filling metal layer, and the fourth lead-out layer is located in the same layer as the surface metal layer.

[0040] A semiconductor device according to at least one embodiment of the present disclosure further includes a base potential lead-out structure;

[0041] The base potential lead-out structure includes a PN junction isolation structure extending from the base layer, a fifth lead-out layer in contact with the PN junction isolation structure, and a sixth lead-out layer in contact with the fifth lead-out layer;

[0042] Both the fifth and sixth lead-out layers are made of metal.

[0043] According to at least one embodiment of the semiconductor device of the present disclosure, the first metal layer and / or the second metal layer includes a hole-filling metal layer and a surface metal layer, the fifth lead-out layer is located in the same layer as the hole-filling metal layer, and the sixth lead-out layer is located in the same layer as the surface metal layer;

[0044] The fifth lead-out layer is isolated from the hole-filling metal layer by an insulating medium, and the sixth lead-out layer is isolated from the surface metal layer by an insulating medium.

[0045] According to at least one embodiment of the semiconductor device of the present disclosure, the gate layer has a continuous structure in the extension direction from the first main surface to the second main surface.

[0046] According to at least one embodiment of the semiconductor device of the present disclosure, the gate layer includes a plurality of separate portions in the extension direction from the first main surface to the second main surface. Attached Figure Description

[0047] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0048] Figure 1 This is a schematic diagram of the cell structure of a semiconductor device according to one embodiment of the present disclosure.

[0049] Figures 2 to 9 It shows Figure 1 The diagram shows a derived structure of the cellular structure.

[0050] Figure 10 This is a schematic diagram of the cell structure of a semiconductor device according to yet another embodiment of this disclosure.

[0051] Figure 11 This is a color diagram illustrating each layer of one embodiment of the present disclosure.

[0052] Figure 12 A cross-sectional schematic diagram of the gate potential lead-out location of a semiconductor device according to one embodiment of the present disclosure is shown.

[0053] Figure 13 It shows the corresponding Figure 10 A three-dimensional view of the cellular structure cross-section.

[0054] Figure 14 A three-dimensional schematic diagram of the cell region of the base potential lead-out location of a semiconductor device according to one embodiment of the present disclosure is shown.

[0055] Figure 15 A three-dimensional schematic diagram of the cell region of the base potential lead-out location of a semiconductor device according to another embodiment of the present disclosure is shown.

[0056] Figures 16 to 19 yes Figure 13 A schematic cross-sectional view of the derived structure of the three-dimensional structure of the cell region is shown.

[0057] Figure 20 It shows Figure 10 When the semiconductor device is in the on state (on state), the cell region forms a channel. Detailed Implementation

[0058] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0059] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0060] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0061] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0062] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0063] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0064] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0065] Figure 1 This is a schematic diagram of the cell structure of a semiconductor device according to one embodiment of the present disclosure. Figure 1 This is a sectional view.

[0066] refer to Figure 1 The semiconductor device disclosed herein includes: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface; a first metal layer 101 located on the first main surface; a second metal layer 102 located on the second main surface; the semiconductor layer includes: a base layer 200; a first doped silicon layer 310 located between the base layer 200 and the first metal layer 101; a second doped silicon layer 320 located between the base layer 200 and the second metal layer 102; a gate layer 400 extending from the first doped silicon layer 310, through the base layer 200, and extending to the second doped silicon layer 320; and a first insulating dielectric layer 510 that at least isolates the gate layer 400 from the base layer 200, the first doped silicon layer 310, and the second doped silicon layer 320.

[0067] Based on the above structure, the semiconductor device disclosed herein has bidirectional conduction capability and self-protection function.

[0068] refer to Figure 1 Since the first metal layer and the second metal layer are disposed on the top and bottom of the semiconductor device, and the base layer 200 and the gate layer 400 are disposed inside the semiconductor layer, when the semiconductor device of this disclosure is in the conducting state (i.e., the on state), the current can flow from the first metal layer through the semiconductor layer to the second metal layer, and also from the second metal layer through the semiconductor layer to the first metal layer, thereby having bidirectional conduction capability.

[0069] Due to the arrangement of the first metal layer (i.e., the first source) and the second metal layer (i.e., the second source), a first source region is formed in the region of the semiconductor layer adjacent to the first metal layer, and a second source region is formed in the region of the semiconductor layer adjacent to the second metal layer.

[0070] Explanation of the conduction state (on state) of semiconductor devices:

[0071] refer to Figure 1 When a high level is applied to the gate layer and the base layer is floating or a low level is applied, the first source (or the second source) is connected to a high level and the second source (or the first source) is connected to a low level. A channel is formed between the first doped silicon layer and the second doped silicon layer near the gate layer. Current will flow from the first source (or the second source) through the first doped silicon layer (or the second doped silicon layer), the channel, the second doped silicon layer (or the first doped silicon layer) to the second source (or the first source).

[0072] Explanation of semiconductor device blocking state (off state):

[0073] refer to Figure 1 When the gate layer is floating or is applied with a low level, and the base layer is floating or is applied with a low level, the first source (or the second source) is connected to a high level, and the second source (or the first source) is connected to a low level. The first doped silicon layer / second doped layer serves as the main withstand voltage layer, and the base layer partially withstands the voltage (that is, after the main withstand voltage layer bears the main part of the blocking voltage, the base layer bears the remaining part of the blocking voltage).

[0074] In some embodiments of this disclosure, the base layer is led out to the first or second main surface through a trench oxide layer isolation structure or a PN junction isolation structure (described in detail below), thereby providing a self-protection function for the semiconductor device.

[0075] In the off state, if there is a momentary high voltage between the first source and the second source, and the base layer is in an open circuit state, the current generated by the momentary high voltage will be discharged through the NPN structure (or PNP structure) formed by the base layer and the doped layers on both sides to the source set voltage range (i.e. the voltage range in which the field-effect transistor can operate safely in the circuit), and then the base layer will be switched to a low potential, thereby clamping the voltage between the first source and the second source and realizing the self-protection of the semiconductor device.

[0076] Figures 2 to 9 It shows Figure 1 The diagram shows a derived structure of the cellular structure.

[0077] like Figure 2 As shown, with Figure 1 The difference is that the gate layer 400 extends downward to the upper edge of the second doped silicon layer 320, and the first insulating dielectric layer 510 extends into the second doped silicon layer 320 by a smaller portion (relative to...). Figure 1 ).

[0078] like Figure 3 As shown, with Figure 1 The difference is that the gate layer 400 extends downward to the upper edge of the second doped silicon layer 320.

[0079] like Figure 4 As shown, with Figure 3 The difference is that the gate layer 400 extends upward to the lower edge of the first doped silicon layer 310.

[0080] like Figure 5 As shown, with Figure 2 The difference is that the gate layer 400 adopts a split gate structure.

[0081] like Figure 6 As shown, with Figure 1 The difference is that the gate layer 400 adopts a split gate structure.

[0082] like Figure 7 As shown, with Figure 6 The difference is that the gate layer 400 uses a different form of split gate structure.

[0083] like Figure 8 As shown, with Figure 7 The difference is that the gate layer 400 adopts another form of split gate structure.

[0084] like Figure 9 As shown, with Figure 1 The difference is that the gate layer 400 adopts a split gate structure.

[0085] Other derived structures obtained by those skilled in the art through adjustments to the cellular structure based on the technical solutions disclosed herein all fall within the protection scope of this disclosure.

[0086] In some embodiments of this disclosure, the gate layer 400 may be made of polysilicon, wherein the polysilicon may be N-type doped.

[0087] In some embodiments of this disclosure, the first insulating dielectric layer 510 may be silicon dioxide (polycrystalline silicon and silicon isolation dielectric, dielectric layer on silicon), borosilicate glass (dielectric layer on silicon dioxide), silicon oxynitride, silicon nitride (passivation layer), etc. The material of the insulating dielectric layer is prior art, and this disclosure does not impose any special restrictions on it.

[0088] In some embodiments of this disclosure, the base layer 200 may be highly doped P-type silicon or highly doped N-type silicon, where highly doped refers to a high doping concentration.

[0089] In some embodiments of this disclosure, reference is made to Figures 1 to 9In the extension direction from the first main surface (or the second main surface) to the second main surface (or the first main surface), the gate layer 400 can at least completely cover the base layer 200.

[0090] In a preferred embodiment of this disclosure, in the extension direction from the first main surface (or the second main surface) to the second main surface (or the first main surface), the gate layer 400 is at least partially located within the first doped silicon layer and / or at least partially located within the second doped silicon layer.

[0091] Figure 10 This is a schematic diagram of the cell structure of a semiconductor device according to yet another embodiment of this disclosure. Figure 10 This is a sectional view.

[0092] Figure 11 This is a color diagram illustrating each layer of one embodiment of the present disclosure.

[0093] Each doping region in this disclosure can be a specific doping distribution such as uniform doping, linear variable doping, or Gaussian distribution doping. Any adjustments made to the doping method by those skilled in the art fall within the protection scope of this disclosure.

[0094] refer to Figure 10 and Figure 11 In some embodiments of this disclosure, the first doped silicon layer 310 includes a first doped region 311 and a second doped region 312. The doping concentration of the first doped region 311 is greater than that of the second doped region 312. The first doped region 311 is closer to the first metal layer 101 than the second doped region 312.

[0095] Preferably, the second doped silicon layer 320 includes a third doped region 323 and a fourth doped region 324, the doping concentration of the third doped region 323 is greater than the doping concentration of the fourth doped region 324, and the third doped region 323 is closer to the second metal layer 102 than the fourth doped region 324.

[0096] Continue to refer to Figure 10 and Figure 11 In a preferred embodiment of this disclosure, the base layer 200 is a doped silicon layer, and the doping concentration of the base layer 200 is greater than the doping concentration of the first doped silicon layer 310 and greater than the doping concentration of the second doped silicon layer 320.

[0097] Continue to refer to Figure 10 and Figure 11 In a preferred embodiment of this disclosure, the base layer 200 includes a fifth doped region 205 and two sixth doped regions 206, with the fifth doped region 205 located between the two sixth doped regions 206. The two sixth doped regions 206 are adjacent to the second doped region 312 and the fourth doped region 324, respectively. The doping concentration of the fifth doped region 205 is greater than the doping concentration of the sixth doped region 206.

[0098] The doping concentration relationship described above for different doping regions represents the preferred scheme.

[0099] Those skilled in the art, inspired by the technical solutions disclosed herein, can adjust the relationship between the doping concentrations of the different doping regions described above, and set specific values ​​for the doping concentrations, all of which fall within the protection scope of this disclosure.

[0100] In a preferred embodiment of this disclosure, the first doped silicon layer 310 and the second doped silicon layer 320 have the same doping type, which can both be N-type doped (or both can be P-type doped).

[0101] Preferably, the first doping region 311 and the second doping region 312 are both N-type doped (or both can be P-type doped), and the third doping region 323 and the fourth doping region 324 are both N-type doped (or both can be P-type doped).

[0102] Continue to refer to Figure 10 The doping type of the base layer 200 disclosed herein is opposite to the doping type of the first doped silicon layer 310 and the second doped silicon layer 320.

[0103] Preferably, both the fifth doping region 205 and the sixth doping region 206 are P-type doped (or both can be N-type doped).

[0104] The metal (hole filling) can refer to tungsten plug holes; the surface metal (e.g., the surface metal layer of the first metal layer 101) can be aluminum or an aluminum-copper alloy or an aluminum-silicon-copper alloy; the bottom metal (e.g., the second metal layer 102) can be a titanium-nickel-silver alloy.

[0105] for Figure 10 The site of P-type doping can be N-type doping, and the site of N-type doping can be P-type doping.

[0106] Any adjustments made by those skilled in the art to the thickness, doping concentration, doping type, material, etc. of each layer of the semiconductor layer based on the technical solutions disclosed herein fall within the protection scope of this disclosure.

[0107] refer to Figures 1 to 10 The first insulating dielectric layer 510 also isolates the gate layer 500 from the first metal layer 101 and / or the second metal layer 102.

[0108] The semiconductor device disclosed herein utilizes reduced surface field (RESURF) technology in vertical devices by configuring the gate layer as a bulk field plate. This transforms the one-dimensional depletion of the drift region (first doped silicon layer and second doped silicon layer) during device breakdown into two-dimensional depletion. By providing an additional electric field to assist in the depletion of the drift region, the device breakdown voltage is extended. The auxiliary depletion effect of the field plate on the drift region allows for a higher impurity concentration in the drift region, thereby reducing the drift region resistance.

[0109] Both the first doped silicon layer 310 and the second doped silicon layer 320 utilize the field plate's auxiliary depletion to increase the drift region concentration and achieve low resistance under high voltage.

[0110] By adjusting the doping concentration of the drift region (first doped silicon layer 310 and second doped silicon layer 320), the doping concentration of the base region (base layer 200), and the thickness of the drift region, the withstand voltage of the semiconductor device can be controlled.

[0111] Since the gate layer 400 adopts a bulk field plate structure, the semiconductor device of this disclosure needs to bring out the gate potential. Therefore, in the preferred embodiment of this disclosure, the semiconductor device of this disclosure further includes a gate potential lead-out structure.

[0112] Figure 12 A cross-sectional schematic diagram of the gate potential lead-out location of a semiconductor device according to one embodiment of the present disclosure is shown.

[0113] In some embodiments of this disclosure, Figure 10 The cellular structure shown can be located in Figure 12 The two sides of the gate potential lead-out location shown ( Figure 12 (The front and back sides of the middle).

[0114] refer to Figure 12 Preferably, the gate potential lead-out structure includes a first lead-out layer 601 in contact with the gate layer 400 and a second lead-out layer 602 in contact with the first lead-out layer 601.

[0115] The first insulating dielectric layer 510 isolates the first lead-out layer 601 from the first doped silicon layer 310 and the first metal layer 101, or the first insulating dielectric layer 510 isolates the first lead-out layer 601 from the second doped silicon layer 320 and the second metal layer 102 (i.e., Figure 12 Replacement implementation method: The first lead-out layer 601 and the second lead-out layer 602 are formed in Figure 12 In the lower part of the structure, the gate potential is led out from the second doped silicon layer 320 (not shown).

[0116] Both the first lead-out layer 601 and the second lead-out layer 602 are made of metal.

[0117] Continue to refer to Figure 12 In a preferred embodiment of this disclosure, the semiconductor device further includes a second insulating dielectric layer 520.

[0118] Wherein, the second lead-out layer 602 is located on the same layer as the first metal layer 101 or the second metal layer 102, and the second insulating dielectric layer 520 at least isolates the second lead-out layer 602 from the first metal layer 101 or the second metal layer 102.

[0119] More preferably, the first metal layer 101 and / or the second metal layer 102 include a hole-filling metal layer (red, for example, tungsten plug holes) and a surface metal layer (light gray), the first lead-out layer 601 includes at least a portion located in the same layer as the hole-filling metal layer, and the second lead-out layer 602 is located in the same layer as the surface metal layer.

[0120] Figure 10 and Figure 12 An exemplary diagram shows a hole-filling metal layer 1011 and a surface metal layer 1012 of the first metal layer 101.

[0121] Figure 13 It shows the corresponding Figure 10 A three-dimensional view of the cellular structure cross-section, with reference numerals and... Figure 10 same.

[0122] Figure 13 In the middle, the gate layer 400 and the first insulating dielectric layer 510 are both along the direction of the arrow. Figure 13 The left surface extends to the right surface (the right surface is not shown).

[0123] In a preferred embodiment of this disclosure, the first insulating metal layer 510 extends upward to the boundary position between the hole-filling metal layer 1011 and the surface metal layer 1012 of the first metal layer 101.

[0124] Since the base layer 200 of this disclosure is located in the middle of the semiconductor device, in a preferred embodiment of this disclosure, the semiconductor device further includes a base potential lead-out structure.

[0125] Figure 14 A three-dimensional schematic diagram of the cell region of the base potential lead-out location of a semiconductor device according to one embodiment of the present disclosure is shown.

[0126] In one embodiment of this disclosure, reference is made to Figure 14 Semiconductor devices also include base potential lead-out structures.

[0127] The base potential lead-out structure includes a third lead-out layer 703 in contact with the base layer 200, a fourth lead-out layer 704 in contact with the third lead-out layer 703, and a third insulating dielectric layer 530.

[0128] The third insulating dielectric layer 530 isolates the third lead-out layer 703 from the first doped silicon layer 310 and the first metal layer 101 (e.g., Figure 14 (as shown), or the third insulating dielectric layer 530 isolates the third lead-out layer 703 from the second doped silicon layer 320 and the second metal layer 102 (not shown).

[0129] Both the third lead-out layer 703 and the fourth lead-out layer 704 are made of metal.

[0130] In some embodiments of this disclosure, during the manufacturing process of a semiconductor device, the third insulating dielectric layer 530 may be formed in the same manufacturing step (e.g., oxidation) as the first insulating dielectric layer 510 of the semiconductor device.

[0131] Continue to refer to Figure 14 Preferably, the base potential lead-out structure further includes a fourth insulating dielectric layer 540.

[0132] The fourth lead-out layer 704 is located on the same layer as the first metal layer 101 or the second metal layer 102, and the fourth insulating dielectric layer 540 at least isolates the fourth lead-out layer 704 from the first metal layer 101 or the second metal layer 102.

[0133] refer to Figure 14 Preferably, the third lead-out layer 703 is led out from the base layer 200 and passes through the first doped silicon layer 310 or the second doped silicon layer 320 to contact the fourth lead-out layer 704. Figure 14 The diagram shows the path through the first doped silicon layer 310.

[0134] The third lead-out layer 703 can be led out upward (or downward) from the upper boundary of the base layer 200, or upward (or downward) from the lower boundary of the base layer 200, or upward (or downward) from between the upper and lower boundaries of the base layer 200, all of which fall within the protection scope of this disclosure.

[0135] More preferably, the third lead-out layer 703 extends from the contact surface with the sixth doped region 206 of the base layer 200 and passes through the fifth doped region 205 and the first doped silicon layer 310 to contact the fourth lead-out layer 704.

[0136] More preferably, the third insulating dielectric layer 530 isolates the third lead-out layer 703 from the sixth doped region 206 of the base layer 200, the first doped silicon layer 310, and the hole-filling metal layer 1011 of the first metal layer 101 (e.g., Figure 14 (As shown).

[0137] Preferably, refer to Figure 13 and Figure 14 The first metal layer 101 (and / or the second metal layer 102) includes a hole-filling metal layer 1011 (e.g., a tungsten plug hole) and a surface metal layer 1012. The third lead-out layer 703 includes at least a portion located in the same layer as the hole-filling metal layer 1011. The fourth lead-out layer 704 is located in the same layer as the surface metal layer 1012.

[0138] In some embodiments of this disclosure, during the manufacturing process of a semiconductor device, the fourth insulating dielectric layer 540 may be formed in the same manufacturing step (e.g., oxidation) as the second insulating dielectric layer 520 of the semiconductor device.

[0139] It should be noted that, Figure 13 and Figure 14 The cell regions shown are all substructures of the semiconductor devices disclosed herein.

[0140] Figure 13 The illustrated cellular three-dimensional structure can be configured in Figure 14 On the left and / or right surfaces (not shown) of the three-dimensional structure of the cellular region shown, in other words, Figure 13 The three-dimensional structure of the cell region shown is similar to Figure 14 The three-dimensional structure of the cell region shown can be arranged in the direction of the first arrow.

[0141] Those skilled in the art should understand that Figure 12 The corresponding three-dimensional structure of the cell region (not shown) and Figure 13 The three-dimensional structure of the cell region shown Figure 14 The three-dimensional structure of the cell region shown can be arranged in the direction of the first arrow.

[0142] Figure 12 The corresponding 3D structure of the cell region (not shown) can be located in Figure 13 The three-dimensional structure of the cell region shown is similar to Figure 14 The three-dimensional structure of the cell region is shown.

[0143] Figure 14 The gate layer 400 and the first insulating dielectric layer 510 shown can extend along the direction of the first arrow to the aforementioned base potential lead-out structure.

[0144] Figure 14The base potential lead-out structure shown can extend along the direction of the second arrow to the back surface (not shown) opposite the front surface of the semiconductor device.

[0145] The direction of the first arrow is perpendicular to the direction of the second arrow.

[0146] Figure 15 A three-dimensional schematic diagram of the cell region of the base potential lead-out location of a semiconductor device according to another embodiment of the present disclosure is shown.

[0147] In one embodiment of this disclosure, reference is made to Figure 15 Semiconductor devices also include base potential lead-out structures.

[0148] refer to Figure 15 The base potential lead-out structure includes a PN junction isolation structure 210 extending from the base layer 200, a fifth lead-out layer 805 in contact with the PN junction isolation structure 210, and a sixth lead-out layer 806 in contact with the fifth lead-out layer 805.

[0149] Both the fifth lead-out layer 805 and the sixth lead-out layer 806 are made of metal.

[0150] Preferably, the first metal layer 101 (and / or the second metal layer 102) includes a hole-filling metal layer 1011 (tungsten plug hole) and a surface metal layer 1012, the fifth lead-out layer 805 is located in the same layer as the hole-filling metal layer 1011, and the sixth lead-out layer 806 is located in the same layer as the surface metal layer 1011.

[0151] Preferably, the base potential lead-out structure includes a fifth insulating dielectric layer 550 and a sixth insulating dielectric layer 560. The fifth lead-out layer 805 is isolated from the hole-filling metal layer 1011 by the fifth insulating dielectric layer 550, and the sixth lead-out layer 806 is isolated from the surface metal layer 1012 by the sixth insulating dielectric layer 560.

[0152] It should be noted that, Figure 13 and Figure 15 The shown cell regions can all be substructures of the semiconductor devices disclosed herein.

[0153] Figure 13 The illustrated cellular three-dimensional structure can be configured in Figure 15 On the left and / or right surfaces (not shown) of the three-dimensional structure of the cellular region shown, in other words, Figure 13 The three-dimensional structure of the cell region shown is similar to Figure 15 The three-dimensional structure of the cell region shown can be arranged in the direction of the first arrow.

[0154] Those skilled in the art should understand that Figure 12 The corresponding three-dimensional structure of the cell region (not shown) and Figure 13 The three-dimensional structure of the cell region shown Figure 15 The three-dimensional structure of the cell region shown can be arranged in the direction of the first arrow.

[0155] Figure 12 The corresponding 3D structure of the cell region (not shown) can be located in Figure 13 The three-dimensional structure of the cell region shown is similar to Figure 15 The three-dimensional structure of the cell region is shown.

[0156] Figure 15 The gate layer 400 and the first insulating dielectric layer 510 shown can extend along the direction of the first arrow to Figure 15 The base potential extraction structure is shown.

[0157] Figure 15 The base potential lead-out structure shown can extend along the direction of the second arrow to the back surface (not shown) opposite the front surface of the semiconductor device.

[0158] The direction of the first arrow is perpendicular to the direction of the second arrow.

[0159] It should be noted that in the various embodiments described above in this disclosure, the gate layer 400 can be a continuous structure (i.e., a trench gate) in the extension direction from the first main surface to the second main surface, or the gate layer 400 can include multiple separate portions (i.e., trench separation gates) in the extension direction from the first main surface to the second main surface, both of which fall within the protection scope of this disclosure.

[0160] Figures 16 to 19 yes Figure 13 A schematic cross-sectional view of the derived structure of the three-dimensional structure of the cell region is shown (the cross-section extends along the direction of the second arrow).

[0161] refer to Figure 16 ,and Figure 13 The difference is that the base layer 200 has a larger size in the extension direction from the first main surface to the second main surface and has only one doped region. The first doped silicon layer 310 and the second doped silicon layer 320 have smaller sizes in the extension direction from the first main surface to the second main surface and both have one doped region.

[0162] refer to Figure 17 ,and Figure 16 Unlike the trench gate, the gate layer 400 is in the form of a trench-separated gate.

[0163] refer to Figure 18 ,and Figure 17The difference is that the base layer 200 is divided into two parts by the third doped silicon layer 330. The third doped silicon layer 330 has the same doping type as the first doped silicon layer 310 and the second doped silicon layer 320, but the opposite doping type to that of the base layer 200.

[0164] refer to Figure 19 ,and Figure 17 The difference is that a fourth doped silicon layer 340 is formed in the middle of the base layer 200. The fourth doped silicon layer 340 has the same doping type as the first doped silicon layer 310 and the second doped silicon layer 320, but the opposite doping type to that of the base layer 200.

[0165] exist Figures 16 to 19 In the derived structure shown, the doping concentration of the gate layer 200 is preferably greater than the doping concentration of the first doped silicon layer, the second doped silicon layer, the third doped silicon layer, and the fourth doped silicon layer.

[0166] Those skilled in the art, inspired by the technical solutions disclosed herein, may also design the doping concentration of the gate layer 200 to be equal to or less than the doping concentration of the first doped silicon layer, the second doped silicon layer, the third doped silicon layer, and the fourth doped silicon layer, all of which fall within the protection scope of this disclosure.

[0167] Those skilled in the art, inspired by the technical solutions disclosed herein, will find that... Figure 13 Any three-dimensional structure of the shown cell region that is modified into other derived structures falls within the protection scope of this disclosure.

[0168] Figure 20 It shows Figure 10 ( Figure 13 When the semiconductor device is in the on state (on state), the cell region of the semiconductor device forms a channel.

[0169] refer to Figure 20 When a high level is applied to the gate layer and the base layer is either floating or low, the first source 101 (or the second source 102) is connected to a high level and the second source 102 (or the first source 101) is connected to a low level. A drift region 1 is formed in the first doped silicon layer and a second drift region 2 is formed in the second doped layer. A channel is formed between the drift region 1 and the second drift region 2. Current will flow from the first source 101 (or the second source 102) through the drift region 1 (or drift region 2), the channel, and the drift region 2 (or drift region 1) to the second source 102 (or the first source 101).

[0170] Continue to refer to Figure 20When the gate layer is floating or is applied with a low level, and the base layer is floating or is applied with a low level, the first source 101 (or the second source 102) is connected to a high level, and the second source 102 (or the first source 101) is connected to a low level. Drift region 1 / drift region 2 serves as the main withstand voltage layer (i.e., the drift region bears the main part of the blocking voltage), and the base layer partially withstands the voltage (i.e., after the drift region bears the main part of the blocking voltage, the base region bears the remaining part of the blocking voltage).

[0171] As can be seen from the above description of the semiconductor device of this disclosure, since the structure of the semiconductor device of this disclosure has bidirectional blocking characteristics, the chip area formed by the semiconductor device of this disclosure will be greatly reduced compared with the existing unidirectional blocking device as a BDS (Bidirectional Switch).

[0172] Assuming the resistance of a unidirectional blocking device is R0, its specific conductivity is Rsp0, and its area is A0 = Rsp0 / R0; when using a set of these unidirectional blocking devices in a BDS application, the resistance is 2R0 and the area is 2A0. Based on the device structure of this disclosure, assuming the resistance of the semiconductor device is R1 and its specific conductivity is Rsp1, then the area is A1 = Rsp1 / R1. If the semiconductor device of this disclosure replaces a set of unidirectional blocking devices in a BDS application, 2R0 = R1, and Rsp1 < 2Rsp0, A1 < 2Rsp0 / 2R0 = A0 < 2A0, the chip area will be reduced by more than 50%.

[0173] Refer again Figure 14 and Figure 15 This disclosure uses a trench oxide layer to isolate the structure ( Figure 14 ) or through a PN junction isolation structure ( Figure 15 The base potential is led out to the first or second main surface, thus exhibiting the self-protection function of the semiconductor device.

[0174] In the off state, if there is a momentary high voltage between the first source and the second source, and the base layer is in an open circuit state, the current generated by the momentary high voltage will be discharged through the NPN structure (or PNP structure) formed by the base layer and the doped layers on both sides to the source set voltage range (i.e. the voltage range in which the field-effect transistor can operate safely in the circuit), and then the base layer will be switched to a low potential, thereby clamping the voltage between the first source and the second source and realizing the self-protection of the semiconductor device.

[0175] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0176] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0177] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor layer having a first main surface and a second main surface opposite to the first main surface; The first metal layer located on the first main surface; as well as A second metal layer located on the second main surface; The semiconductor layer includes: Base layer; A first doped silicon layer located between the base layer and the first metal layer; A second doped silicon layer located between the base layer and the second metal layer; A gate layer extending from the first doped silicon layer, through the base layer, and to the second doped silicon layer; and The first insulating dielectric layer isolates at least the gate layer from the base layer, the first doped silicon layer, and the second doped silicon layer.

2. The semiconductor device according to claim 1, characterized in that, In the extension direction from the first main surface to the second main surface, the gate layer is at least partially located within the first doped silicon layer and / or at least partially located within the second doped silicon layer.

3. The semiconductor device according to claim 1, characterized in that, The first doped silicon layer includes a first doped region and a second doped region. The doping concentration of the first doped region is greater than that of the second doped region. The first doped region is closer to the first metal layer than the second doped region.

4. The semiconductor device according to claim 1, characterized in that, The second doped silicon layer includes a third doped region and a fourth doped region. The doping concentration of the third doped region is greater than that of the fourth doped region, and the third doped region is closer to the second metal layer than the fourth doped region.

5. The semiconductor device according to claim 1, characterized in that, The base layer is a doped silicon layer, and the doping concentration of the base layer is greater than the doping concentration of the first doped silicon layer and the doping concentration of the second doped silicon layer.

6. The semiconductor device according to claim 1, characterized in that, The base layer includes a fifth doped region and two sixth doped regions, with the fifth doped region located between the two sixth doped regions. The two sixth doped regions are adjacent to the second doped region and the fourth doped region, respectively. The doping concentration of the fifth doped region is greater than that of the sixth doped region.

7. The semiconductor device according to claim 1, characterized in that, The first doped silicon layer and the second doped silicon layer have the same doping type.

8. The semiconductor device according to claim 1, characterized in that, The doping type of the base layer is opposite to that of the first doped silicon layer and the second doped silicon layer.

9. The semiconductor device according to claim 3, characterized in that, The second doped region has a uniform doping distribution or a linear doping distribution.

10. The semiconductor device according to claim 4, characterized in that, The fourth doping region has a uniform doping distribution or a linear doping distribution.

11. The semiconductor device according to claim 1, characterized in that, The gate layer is a polysilicon layer.

12. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a gate potential lead-out structure; The gate potential lead-out structure includes a first lead-out layer in contact with the gate layer and a second lead-out layer in contact with the first lead-out layer; The first insulating dielectric layer isolates the first lead-out layer from the first doped silicon layer and the first metal layer, or the first insulating dielectric layer isolates the first lead-out layer from the second doped silicon layer and the second metal layer; Both the first lead-out layer and the second lead-out layer are made of metal.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes a second insulating dielectric layer; The second lead-out layer is located on the same layer as the first metal layer or the second metal layer, and the second insulating dielectric layer at least isolates the second lead-out layer from the first metal layer or the second metal layer.

14. The semiconductor device according to claim 13, characterized in that, The first metal layer and / or the second metal layer include a via-filling metal layer and a surface metal layer, the first lead-out layer includes at least a portion located in the same layer as the via-filling metal layer, and the second lead-out layer is located in the same layer as the surface metal layer.

15. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a base potential lead-out structure; The base potential lead-out structure includes a third lead-out layer in contact with the base layer, a fourth lead-out layer in contact with the third lead-out layer, and a third insulating dielectric layer. The third insulating dielectric layer isolates the third lead-out layer from the first doped silicon layer and the first metal layer, or the third insulating dielectric layer isolates the third lead-out layer from the second doped silicon layer and the second metal layer; Both the third lead-out layer and the fourth lead-out layer are made of metal.

16. The semiconductor device according to claim 15, characterized in that, The base potential lead-out structure also includes a fourth insulating dielectric layer; The fourth lead-out layer is located on the same layer as the first metal layer or the second metal layer, and the fourth insulating dielectric layer at least isolates the fourth lead-out layer from the first metal layer or the second metal layer.

17. The semiconductor device according to claim 15, characterized in that, The third lead-out layer extends from the base layer and passes through the first doped silicon layer or through the second doped silicon layer to contact the fourth lead-out layer.

18. The semiconductor device according to claim 15, characterized in that, The first metal layer and / or the second metal layer include a via-filling metal layer and a surface metal layer, the third lead-out layer includes at least a portion located in the same layer as the via-filling metal layer, and the fourth lead-out layer is located in the same layer as the surface metal layer.

19. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a base potential lead-out structure; The base potential lead-out structure includes a PN junction isolation structure extending from the base layer, a fifth lead-out layer in contact with the PN junction isolation structure, and a sixth lead-out layer in contact with the fifth lead-out layer; Both the fifth and sixth lead-out layers are made of metal.

20. The semiconductor device according to claim 19, characterized in that, The first metal layer and / or the second metal layer include a via-filling metal layer and a surface metal layer, the fifth lead-out layer is located in the same layer as the via-filling metal layer, and the sixth lead-out layer is located in the same layer as the surface metal layer; The fifth lead-out layer is isolated from the hole-filling metal layer by an insulating medium, and the sixth lead-out layer is isolated from the surface metal layer by an insulating medium.

21. The semiconductor device according to claim 1, characterized in that, The gate layer has a continuous structure in the direction of extension from the first main surface to the second main surface.

22. The semiconductor device according to claim 1, characterized in that, The gate layer includes multiple separate portions along the extension direction from the first main surface to the second main surface.

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