Semiconductor packaging structure, semiconductor device and electronic equipment

Abstract

The utility model relates to a semiconductor packaging structure, a semiconductor device and electronic equipment, the semiconductor packaging structure comprises a substrate and a capacitor, and the substrate comprises a glass substrate body with a cavity; the capacitor is embedded in the cavity. According to the semiconductor packaging structure, the capacitor is mounted in the cavity of the glass substrate body, so that the thickness of the glass substrate body can be reduced without warping, and a large-size packaging structure is met.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor design and fabrication technology, specifically to a semiconductor packaging structure, semiconductor device, and electronic device. Background Technology

[0002] Currently, to reduce equivalent series inductance and resistance, silicon capacitors are embedded in the cavity of the substrate before encapsulation. In related technologies, to control substrate warpage, the substrate thickness is typically greater than 1000 micrometers, while the thickness of a typical silicon capacitor is usually less than 775 micrometers. The position of the silicon capacitor within the substrate cavity may shift. In addition, since the coefficient of thermal expansion of the substrate is usually higher than that of the silicon capacitor, the silicon capacitor experiences high stress, posing a reliability risk during temperature cycling. Utility Model Content

[0003] The purpose of this disclosure is to provide a semiconductor packaging structure, semiconductor device, and electronic device. This semiconductor packaging structure mounts capacitors within a cavity of a glass substrate body, which can reduce the thickness of the glass substrate body without warping, thereby meeting the requirements of large-size packaging structures.

[0004] To achieve the above objectives, according to a first aspect of this disclosure, a semiconductor package structure is provided, comprising:

[0005] The substrate includes a glass substrate body having a cavity; and

[0006] The capacitor is embedded inside the cavity.

[0007] Optionally, the thickness of the glass substrate body is adapted to the thickness of the capacitor.

[0008] Optionally, the thickness of the glass substrate body is less than or equal to 770 μm.

[0009] Optionally, the capacitor may include a DTC capacitor and / or a 3D MIM capacitor.

[0010] Optionally, the glass substrate body further includes a through-hole, and the semiconductor packaging structure further includes a first metal layer located within the through-hole.

[0011] Optionally, the substrate further includes at least one laminate disposed on each side of the glass substrate body.

[0012] Optionally, the substrate further includes an isolation layer formed on the side of the laminate away from the glass substrate body;

[0013] The semiconductor package structure further includes a second metal layer formed between the stacked layers, and the isolation layer has pads connected to the second metal layer.

[0014] Optionally, the semiconductor packaging structure may further include a chip located above the substrate.

[0015] According to a second aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising the semiconductor packaging structure described above.

[0016] According to a third aspect of this disclosure, an electronic device is also provided, which includes the semiconductor packaging structure or the semiconductor device described above.

[0017] The above-described technical solution, namely the semiconductor packaging structure disclosed herein, includes a substrate and a capacitor. The substrate includes a glass substrate body with a cavity, and the capacitor is mounted in the cavity. Since the glass substrate body has a high elastic modulus and good strength, it will not produce large warping when using a small thickness, such as less than or equal to 1000 micrometers. Therefore, this structure can meet the requirements of a large packaging structure.

[0018] Furthermore, the capacitor can be a DTC capacitor and / or a 3D MIM capacitor, with a coefficient of thermal expansion close to that of the glass substrate, thereby reducing the stress on the capacitor and increasing its reliability.

[0019] Furthermore, since the capacitor is directly embedded inside the cavity of the glass substrate body of the substrate, it has low ESL / ESR characteristics and can also reduce high-frequency power noise.

[0020] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the accompanying drawings...

[0022] Figure 1 This is a structural diagram of a semiconductor packaging structure in related technologies.

[0023] Figure 2 This is a structural diagram of a semiconductor packaging structure provided in some embodiments of this disclosure.

[0024] Figures 3 to 16 This is a flowchart illustrating the fabrication process of a semiconductor packaging structure provided in some embodiments of this disclosure.

[0025] Explanation of reference numerals in the attached figures

[0026] 11-Substrate body; 12-Layer stack; 20-Silicon capacitor;

[0027] 100 - Substrate; 110 - Glass substrate body; 111 - Cavity; 112 - Through-hole; 120 - Stacked layers; 130 - Isolating layer; 131 - Pad window; 140a - First copper plating layer; 140b - Second copper plating layer; 141 - First metal layer; 142 - Second metal layer; 150 - Pad; 160 - Insulating layer;

[0028] 200 - Capacitor components;

[0029] 300-chip components;

[0030] 400-Carrier. Detailed Implementation

[0031] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0032] In this disclosure, unless otherwise stated, directional terms such as "upper," "lower," "left," and "right" generally refer to the upper, lower, left, and right of the corresponding figures; "inner" and "outer" refer to the outline of the corresponding component itself. The terms "first," "second," etc., used in this disclosure are for distinguishing one element from another and do not have sequential or importance. When the following description refers to the figures, unless otherwise indicated, the same numbers in different figures represent the same or similar elements.

[0033] like Figure 1 The diagram shown is a schematic of a semiconductor packaging structure in related technologies. The semiconductor packaging structure includes a substrate and a chip device 300 (e.g., a SOC chip) connected to the substrate via pads. The substrate includes a substrate body 11 and multiple stacked layers 12 formed on the upper and lower sides of the substrate body 11. Through-holes and cavities are formed on the substrate body 11. A silicon capacitor 20 is bonded to the cavity of the substrate body 11 with adhesive. To prevent substrate warping, the thickness H1 of the substrate body 11 is typically greater than 1000 micrometers, while the thickness of a typical silicon capacitor 20 is typically less than 775 micrometers. The position of the silicon capacitor within the cavity may shift. Furthermore, since the coefficient of thermal expansion of the substrate body 11 is typically higher than that of the silicon capacitor 20, the silicon capacitor 20 experiences high stress, posing a reliability risk during temperature cycling.

[0034] Based on this, the purpose of this disclosure is to provide a semiconductor packaging structure and its preparation method. The substrate body of the semiconductor packaging structure adopts a glass substrate body 110, and the capacitor 200 is installed in the cavity 111 of the glass substrate body 110. This can reduce the thickness of the glass substrate body 110 without warping, thus satisfying the requirements of a larger packaging structure.

[0035] To achieve the above objectives, such as Figures 2 to 12 As shown, according to a first aspect of this disclosure, a semiconductor package structure is provided, the semiconductor package structure including a substrate 100 and a capacitor 200. The substrate 100 includes a glass substrate body 110 having at least one cavity 111, and the capacitor 200 is embedded inside the cavity 111.

[0036] The semiconductor package structure disclosed herein includes a substrate 100 and a capacitor 200. The substrate 100 includes a glass substrate body 110 having a cavity 111, and the capacitor 200 is mounted in the cavity 111. Since the glass substrate body 110 has a high elastic modulus, its thickness can be arranged to be smaller. For example, when it uses a smaller thickness dimension, such as less than or equal to 1000 micrometers, it can also be used in a larger package structure without causing large warpage.

[0037] The glass substrate body 110 can be a doped glass fiber substrate 100, on which at least one laminate 120, such as an ABF layer (Ajinomoto Build-up Film Layer), is typically formed. In this structure, the glass substrate body 110 needs to have higher mechanical strength than the ABF layer. For large package structures, the thickness of the conventional substrate body 100 is increased to about 1000 μm or more (typically more than 1200 μm) to increase the mechanical strength of the substrate body 100 and reduce warpage. However, in actual fabrication, it is difficult to embed the capacitor 200 into a substrate 100 with a thickness of more than 800 μm without displacement.

[0038] It should be noted that the capacitor 200 may include a DTC capacitor and / or a 3D MIM capacitor. Since the DTC capacitor and / or 3D MIM capacitor used have a coefficient of thermal expansion close to that of the glass substrate 110, the stress on the capacitor 200 can be reduced, the risk of cracking can be decreased, and reliability can be increased.

[0039] In some embodiments, the capacitor 200 embedded in the cavity 111 may include, for example, a DTC capacitor and a 3D MIM capacitor. A DTC capacitor is one type of capacitor 200, which can be formed by creating a cavity 111 or a groove in the glass substrate body 110. Meanwhile, for portions of the glass substrate body 110 that do not meet the conditions for forming a DTC capacitor, other forms of capacitor 200 may be used.

[0040] like Figure 2As shown, in some embodiments, the thickness H2 of the glass substrate body 110 is adapted to the thickness of the capacitor element 200. For example, the thickness H2 of the glass substrate body 110 can be comparable to the thickness of the capacitor element 200. Considering that the thickness of the capacitor element 200 to be embedded may be between 50-760 μm, a glass substrate body 110 of comparable thickness can be configured accordingly. For example, the thickness H2 of the glass substrate body 110 is less than 1000 μm or less than 800 μm. In some preferred embodiments, the thickness H2 of the glass substrate body 110 is less than or equal to 770 μm. It is understood that the thickness H2 of the glass substrate body 110 can be appropriately adjusted to meet the embedding requirements of DTC capacitors and / or 3DMIM capacitors of different thicknesses.

[0041] Therefore, the thickness H2 of the glass substrate body 110, the thickness of the applied laminate 120, the thickness of the capacitor 200 to be embedded, or a combination of the above adjustments, can be used to adapt the capacitor 200 to the laminate 120 or the capacitor 200 to the glass substrate body 110. This avoids the problem of a smaller thickness capacitor 200 being incompatible with a thicker substrate 100, which could lead to easy displacement of the silicon capacitor and affect reliability. It should be noted that because the glass substrate body 110 has a high elastic modulus, it can meet the strength requirements even with a smaller thickness. At the same time, because the thickness H2 of the glass substrate body 110 is reduced, the thickness of the entire semiconductor packaging structure substrate 100 can also be reduced accordingly, achieving miniaturization of the packaging structure and reducing space occupation.

[0042] To achieve Vdd, Vss, and signal connections with the printed circuit board, in some embodiments, the glass substrate body 110 further includes multiple through-holes 112. These through-holes 112 can penetrate both sides of the glass substrate body 110 in the thickness direction. The semiconductor packaging structure also includes a first metal layer 141 located within the through-holes 112. Multiple through-holes 112 are included, such as... Figure 2 As shown, this disclosure takes three through holes 112 and three first metal layers 141 respectively disposed in the three through holes 112 as an example. One through hole 112 and the first metal layer 141 in the through hole 112 are located on the left side of the capacitor 200. The upper part is used to connect with the chip 300 and the capacitor 200, and the lower part is used to connect with the Vdd pad 150. Another through hole 112 and the first metal layer 141 in the through hole 112 are located on the right side of the capacitor 200. The upper part is used to connect with the chip 300 and the capacitor 200, and the lower part is used to connect with the Vss pad 150. The leftmost through hole 112 and the first metal layer 141 in the through hole 112 are used to connect the chip 300 and the signal pad 150.

[0043] In some embodiments, the semiconductor packaging structure further includes at least one stacked layer 120 disposed on each side of the glass substrate body 110. Typically, multiple stacked layers 120 are formed on both sides of the glass substrate body 110, and multiple second metal layers 142 are sequentially connected between the multiple stacked layers 120 to achieve electrical connection with the pads 150 at the outermost stacked layer 120.

[0044] It should be noted that one or more cavities 111 can be formed by multiple layers 120, and a portion of the capacitor 200 can be embedded in the one or more cavities 111. It should be noted that at this time, the thickness of the capacitor 200 embedded needs to be adapted to the thickness of the cavity 111 to be embedded.

[0045] The stacked layer 120 can employ structural layers and arrangements known in related technologies. For example, the stacked layer 120 can be an ABF layer (Ajinomoto Build-up Film Layer) to achieve connection with the chip device 300. Figure 2 As shown, in some embodiments, the substrate 100 further includes an isolation layer 130 formed on the side of the stacked layers 120 away from the glass substrate body 110; the semiconductor package structure further includes a second metal layer 142 formed between the stacked layers 120, and the isolation layer 130 has pads 150 connected to the second metal layer 142. The stacked layers 120 can be a multilayer structure, and there can be multiple second metal layers 142 distributed among the stacked layers 120. Electrical connection of the multiple second metal layers 142 is achieved by arranging vias 112 in each stacked layer 120 and forming a conductive metal layer within the vias 112.

[0046] It is understandable that the isolation layer 130 can also be constructed using a structure known in the related art. The isolation layer 130 is used to isolate the pads 150 and the stacked layer 120 to prevent solder from penetrating into the interior of the semiconductor package structure.

[0047] like Figure 2 As shown, in some embodiments, the semiconductor package structure further includes a chip 300 located above the substrate 100. The chip 300 can be connected by soldering to pads 150 above the substrate 100. It is understood that the capacitor 200 is located below the chip 300, for example, directly below it. This arrangement allows the chip 300 to be vertically connected to the capacitor 200, resulting in significantly lower ESL and ESR from the capacitor 200 to the pads 150 of the chip 300 above it, while also reducing high-frequency AC noise.

[0048] refer to Figures 3 to 16In order to prepare the above-mentioned semiconductor packaging structure, this disclosure also provides a method for preparing a semiconductor packaging structure, the method comprising: providing a glass substrate body 110.

[0049] A cavity 111 is formed on the glass substrate body 110.

[0050] A capacitor 200 is installed inside the cavity 111. The capacitor 200 includes a DTC capacitor and / or a 3D MIM capacitor.

[0051] The fabrication method disclosed herein involves forming a cavity 111 on a glass substrate body 110 and embedding a capacitor 200 into the cavity 111. Because the glass substrate body 110 has a high elastic modulus, it can accommodate the thickness of the capacitor 200, i.e., the thickness can be less than or equal to 1000 μm. Preferably, the thickness of the glass substrate body 110 is less than or equal to 770 μm. The thickness of the glass substrate body 110 can be adaptively adjusted according to the thickness of the capacitor. For example, the thickness of the capacitor 200 may be between 50 and 760 μm, and the corresponding thickness of the glass substrate body 110 can also be set accordingly. When the glass substrate body 110 is used in a smaller size, warping will not occur, meeting the requirements of large-size packaging structures.

[0052] It should be noted that the capacitor 200 can be a DTC capacitor and / or a 3D MIM capacitor. Since the coefficient of thermal expansion of the DTC capacitor and / or the 3D MIM capacitor is close to that of the glass substrate body 110, the stress of the capacitor 200 can be reduced and the reliability can be increased.

[0053] To enable the connection of the printed circuit board to the chip 300 located on the substrate 100 via Vdd, Vss, and signal, the method further includes forming a through hole 112 on the glass substrate body 110.

[0054] A first metal layer 141 is formed inside the through hole 112.

[0055] like Figure 9 , Figure 10 and Figure 11 As shown, for example, a through hole 112 can be formed on one side of the cavity 111, and the first metal layer 141 in the through hole 112 is used to realize the connection with the Vdd pad 150 and the chip 300; two through holes 112 are formed on the other side at intervals, one through hole 112 and the first metal layer 141 therein are used to realize the connection between the Vss pad 150 and the chip 300; the other through hole 112 and the first metal layer 141 therein are used to realize the connection between the chip 300 and the signal pad 150.

[0056] In order to form the first metal layer 141 and the embedded capacitor 200, in some embodiments, the first metal layer 141 is formed in the through hole 112, including: forming the first metal layer 141 on the surface of the glass substrate body 110, the sidewall of the cavity 111, and the sidewall of the through hole 112; wherein, the first metal layer 141 includes, but is not limited to, copper, and can be achieved by plating copper on the glass substrate body 110 that forms the cavity 111 and the through hole 112.

[0057] A carrier 400 layer is provided at the bottom of the glass substrate body 110. The carrier 400 layer can be tape, blue tape or other carrier 400, and is used to form a support at the bottom of the glass substrate body 110 to prepare for the subsequent mounting of capacitor 200 and filling of insulating layer 160.

[0058] The capacitor 200 is mounted in the cavity 111, wherein the capacitor 200 can be a DTC capacitor and / or a 3D MIM capacitor.

[0059] An insulating layer 160 is filled in the through hole 112 and the cavity 111. The insulating layer 160 in the cavity 111 is located between the capacitor 200 and the first metal layer 141, while the insulating layer 160 in the through hole 112 is located inside the first metal layer 141.

[0060] Remove the carrier 400 layer and the first metal layer 141 on the surface of the glass substrate body 110. The first metal layer 141 on the surface of the glass substrate body 110 can be removed by any suitable method, such as photolithography and etching, thereby protecting the first metal layer 141 located in the cavity 111 and the through hole 112.

[0061] In some embodiments, the method further includes forming one or more layers 120 on the surface of the glass substrate body 110.

[0062] At least one second metal layer 142 is formed in the stack 120 to be connected to the capacitor 200 and / or the first metal layer 141.

[0063] First, a laminate 120, such as an ABF layer, can be pressed onto the upper and lower surfaces of the glass substrate body 110. A metal layer is then formed on the laminate 120 by laser drilling and copper plating to achieve connection with the first metal layer 141 of the via 112 and the capacitor 200. Next, a second metal layer 142 is obtained by photolithography and etching of this metal layer. Finally, the steps of forming the laminate 120 and the second metal layer 142 are repeated for multiple layers.

[0064] In some embodiments, the method further includes forming an isolation layer 130 on the side of the outermost stacked layer 120 away from the glass substrate body 110; wherein the isolation layer 130 is mainly for preventing the pads 150 formed in subsequent steps from penetrating into the stacked layer 120, and can be made of any suitable material known in the related art.

[0065] A substrate 100 is formed by forming pads 150 connected to the second metal layer 142 in the isolation layer 130. Then, the isolation layer 130 is photolithographically and etched to form pad 150 windows 131, and pads 150 are formed at the corresponding pad 150 windows 131 by pre-soldering printing and reflow soldering.

[0066] In some embodiments, the method further includes: providing a chip device 300 and connecting the chip device 300 to a pad 150 above the substrate 100. The chip device 300 may be a System-on-a-Chip (SOC) chip, and connecting the chip device 300 to the pad 150 above the substrate 100 enables chip assembly.

[0067] It should be noted that the pads 150 on the other side of the glass substrate body 110 away from the chip 300 are used for connection to the PCB board, including but not limited to core power supply, grounding and signal connection.

[0068] refer to Figures 3 to 16 As shown, this disclosure describes in detail the manufacturing process of a semiconductor packaging structure using a specific embodiment.

[0069] like Figure 3 As shown, a glass substrate body 110 is provided, and a cavity 111 and a through hole 112 are formed on the glass substrate body 110.

[0070] like Figure 4 As shown, a first copper plating layer 140a is formed by copper plating on the upper and lower surfaces of the glass substrate body 110, as well as on the sidewalls of the cavity 111 and the through hole 112.

[0071] like Figure 5 As shown, the glass substrate body 110 is placed on the blue tape or the carrier 400 formed by other support members, and the DTC capacitor is embedded in the cavity 111.

[0072] like Figure 6 As shown, an insulating layer 160 is formed in the through hole 112 and the cavity 111.

[0073] like Figure 7 As shown, remove carrier 400, including blue tape or support.

[0074] like Figure 8 As shown, copper circuits are formed by photolithography and etching of copper plating on the surface of the glass substrate body 110.

[0075] like Figure 9 As shown, an ABF layer, namely a stacked layer 120, is formed on the upper and lower surfaces of the glass substrate body 110.

[0076] like Figure 10 As shown, an opening corresponding to the through hole 112 and the DTC capacitor is formed in the ABF layer by laser drilling, and a second copper plating layer 140b is formed in the ABF layer and the opening.

[0077] like Figure 11 As shown, copper plating on the surface of the ABF layer is formed by photolithography and etching to create a copper circuit, including a second metal layer 142.

[0078] like Figure 12 As shown, ABF layers and copper circuits are repeatedly formed, cycling through multiple layers.

[0079] like Figure 13 As shown, an isolation layer (SR Coating) 130 is formed on the surface of the outermost ABF layer.

[0080] like Figure 14 As shown, the photolithography and etching isolation layer (SR Coating) 130 forms the pad 150 and window 131.

[0081] like Figure 15 As shown, pad 150 is formed at window 131 of corresponding pad 150 by pre-soldering printing and reflow soldering.

[0082] like Figure 16 As shown, chip component 300 (SOC chip) is soldered to pad 150.

[0083] According to a second aspect of this disclosure, a semiconductor device is provided, which includes the semiconductor packaging structure described above. Therefore, the semiconductor device also possesses all the advantages of the semiconductor packaging structure described above, which will not be elaborated here.

[0084] According to a third aspect of this disclosure, an electronic device is also provided, which includes the semiconductor packaging structure or the semiconductor device described above. Since the semiconductor device also includes the semiconductor packaging structure described above, the electronic device also possesses all the advantages of the semiconductor packaging structure described above, which will not be elaborated here.

[0085] Electronic devices include, but are not limited to, desktop computers, laptops, tablets, and wearable devices.

[0086] The semiconductor packaging structure, semiconductor device, and electronic device disclosed herein embed a capacitor 200 within the cavity 111 of the glass substrate body 110. Because the glass substrate body 110 has a high elastic modulus, it can be used in larger packaging structures even with a relatively small thickness, such as less than or equal to 1000 micrometers, avoiding significant warpage. The capacitor 200 can be a DTC capacitor and / or a 3D MIM capacitor with a coefficient of thermal expansion close to that of the glass substrate body 110, thereby reducing stress on the capacitor 200 and increasing reliability. Since the capacitor 200 is embedded in the glass substrate body 110, it exhibits low ESL / ESR characteristics, reducing high-frequency power noise.

[0087] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0088] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0089] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A semiconductor packaging structure, characterized in that, include: The substrate includes a glass substrate body having a cavity; and The capacitor is embedded inside the cavity; The thickness of the glass substrate body is adapted to the thickness of the capacitor.

2. The semiconductor packaging structure according to claim 1, characterized in that, The thickness of the glass substrate body is less than or equal to 770 μm.

3. The semiconductor packaging structure according to claim 1, characterized in that, The capacitors include DTC capacitors and / or 3D MIM capacitors.

4. The semiconductor packaging structure according to any one of claims 1-3, characterized in that, The glass substrate body also includes a through-hole, and the semiconductor packaging structure also includes a first metal layer located within the through-hole.

5. The semiconductor packaging structure according to any one of claims 1-3, characterized in that, The substrate further includes at least one laminate disposed on each side of the glass substrate body.

6. The semiconductor packaging structure according to claim 5, characterized in that, The substrate further includes an isolation layer formed on the side of the laminate away from the glass substrate body; The semiconductor package structure further includes a second metal layer formed between the stacked layers, and the isolation layer has pads connected to the second metal layer.

7. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor packaging structure also includes a chip located on top of the substrate.

8. A semiconductor device, characterized in that, Includes the semiconductor packaging structure described in any one of claims 1-7.

9. An electronic device, characterized in that, It includes the semiconductor packaging structure according to any one of claims 1-7 or the semiconductor device according to claim 8.

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