Test fixture and test system

By integrating the test base and test board into a single design, the problems of high-speed signal distortion and space occupation in existing chip test fixtures are solved, resulting in more efficient testing.

CN223977316UActive Publication Date: 2026-03-06SHENZHEN SHICHUANGYI ELECTRONICS CO LTD
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Patent Information

Application Number
CN202520425156.8
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-03-10
Publication Date
2026-03-06
Estimated Expiration
2035-03-10

AI Technical Summary

Technical Problem

Existing chip test fixtures suffer from high losses and weak impedance matching of BTB connectors, leading to high-speed signal distortion and affecting test results. Furthermore, their large size makes it impossible to place test boards, resulting in significant space consumption.

Method used

The test board and test baseboard are integrated into one design. The test board includes a bottom connection board and a top connection board that are fixedly connected. The chip is set on the top connection board and connected to the pad area on the test baseboard through the bottom connection board. The test socket is eliminated, the space occupied by the test board is reduced, and the wiring structure is optimized.

Benefits of technology

It reduces the space occupied by the test board, improves the integrity of high-speed signal transmission and test efficiency, and enhances the test results.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a test fixture and a test system, and relates to the technical field of chip testing. The test fixture comprises a test bottom plate and a test plate, the test plate is arranged on the test bottom plate, a first connection bonding pad area is arranged on the test bottom plate, and the test fixture is characterized in that the test plate comprises a bottom connection plate and a top connection plate which are fixedly connected; the top connecting plate is arranged on one side, far away from the testing bottom plate, of the bottom connecting plate, and the chip is arranged on the top connecting plate and is connected to the first connecting bonding pad area through the top connecting plate and the bottom connecting plate for testing; wherein the size of the orthographic projection of the bottom connecting plate on the test bottom plate is equal to the size of the orthographic projection of the top connecting plate on the test bottom plate, and the size of the orthographic projection of the chip on the test bottom plate is equal to the size of the orthographic projection of the chip on the test bottom plate; through the above design, the space occupation is reduced, and the test efficiency is improved.
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Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a test fixture and a test system. Background Technology

[0002] Before a chip can be used, it needs to undergo various tests to remove potential defects. These tests include applying voltage to it or making it work or storing it in high-temperature environments corresponding to thermal and mechanical environmental tests, thereby screening out qualified and defective products. In these tests, a test device such as a chip test fixture is required.

[0003] like Figure 1 As shown, existing chip test fixtures consist of a test baseboard, a BTB connector (not shown), a test board, and a test socket stacked sequentially. The test board needs to connect to the test baseboard via the BTB connector for routine signal testing. However, the test baseboard typically contains other electronic components, and these components are quite dense, making it impossible to accommodate a large test board and test socket. Furthermore, the internal circuitry of a large test board is relatively long. Consequently, issues such as high loss and weak impedance matching of the BTB connector cause high-speed signal distortion, affecting test results. Therefore, these problems urgently need to be addressed. Utility Model Content

[0004] The purpose of this application is to provide a test fixture and test system that reduces space occupation and improves test efficiency.

[0005] This application discloses a test fixture for testing chips. The test fixture includes a test base plate and a test board. The test board is disposed on the test base plate and includes a bottom connecting plate and a top connecting plate fixedly connected thereto. The top connecting plate is disposed on the side of the bottom connecting plate away from the test base plate. The chip is disposed on the top connecting plate and connected to a first connection pad area for testing via the top connecting plate and the bottom connecting plate. The size of the orthographic projection of the bottom connecting plate on the test base plate is equal to the size of the orthographic projection of the top connecting plate on the test base plate and is the same as the size of the orthographic projection of the chip on the test base plate.

[0006] Optionally, a second connection pad area is provided on the side of the bottom connection plate near the test base plate, and a third connection pad area is provided on the side of the top connection plate away from the bottom connection plate. The first connection pad area is electrically connected to the third connection pad area through the second connection pad area. The chip is placed in the third connection pad area. The size of the first connection pad area is equal to the size of the second connection pad area and the size of the third connection pad area.

[0007] Optionally, the first connection pad area, the second connection pad area, and the third connection pad area are all rectangular structures; the test fixture further includes an extension plate, which is disposed on at least one side of the top connection plate and is horizontally disposed with the top connection plate. The extension plate is provided with test pads. The first connection pad area is provided with a plurality of first connection pads, the second connection pad area is provided with a plurality of second connection pads, the third connection pad area is provided with a plurality of third connection pads, and the fourth connection pad area is provided with a plurality of fourth connection pads. The fourth connection pads are connected to the first connection pads through the third connection pads and the third connection pads. The test pads are electrically connected to the third connection pads.

[0008] Optionally, the top connecting plate has a rectangular structure, and the extension plate includes a first extension plate, a second extension plate, a third extension plate, and a fourth extension plate. The first extension plate, the second extension plate, the third extension plate, and the fourth extension plate surround the top connecting plate. The first extension plate and the third extension plate are arranged opposite to each other, and the second extension plate and the fourth extension plate are arranged opposite to each other. The test pad includes a plurality of sub-pads, and the plurality of sub-pads are respectively arranged on the first extension plate, the second extension plate, the third extension plate, and the fourth extension plate.

[0009] Optionally, the sub-pad has a hole-like structure with a plug hole in the middle.

[0010] Optionally, the four corners of the first connecting pad area are respectively provided with a first marking portion, a second marking portion, a third marking portion, and a fourth marking portion. The first extension plate and the second extension plate are connected to form a first arc-shaped portion, the second extension plate and the third extension plate are connected to form a second arc-shaped portion, the third extension plate and the fourth extension plate are connected to form a third arc-shaped portion, and the fourth extension plate and the first extension plate are connected to form a fourth arc-shaped portion. The first arc-shaped portion corresponds to the first marking portion, the second arc-shaped portion corresponds to the second marking portion, the third arc-shaped portion corresponds to the third marking portion, and the fourth arc-shaped portion corresponds to the fourth marking portion.

[0011] Optionally, the area of ​​the orthographic projection of the second extension plate onto the test base plate is smaller than the area of ​​the orthographic projection of the fourth extension plate onto the test base plate; and the number of sub-pads on the second extension plate is less than the number of sub-pads on the fourth extension plate.

[0012] Optionally, the thickness of the bottom connecting plate is 1.8mm-2mm, and the thickness of the top connecting plate is 1mm-1.5mm.

[0013] Optionally, the number of the first connection pad, the number of the second connection pad, the number of the third connection pad, and the number of the fourth connection pad are all equal.

[0014] This application also discloses a testing system, including a test fixture and a display as described above, wherein the display is disposed on one side of the test fixture and is electrically connected to the test fixture.

[0015] Compared to traditional test boards that require connection to a test baseboard via BTB connectors for routine signal testing, and which are often densely packed with electronic components and cannot accommodate large test boards and test sockets, the test fixture of this application includes a test baseboard and a test board. The test board is mounted on the test baseboard and has a first connection pad area. The test board includes a bottom connecting plate and a top connecting plate that are fixedly connected. The top connecting plate is located on the side of the bottom connecting plate away from the test baseboard. The chip is mounted on the top connecting plate and connected to the first connection pad area through the top and bottom connecting plates. The orthographic projection size of the bottom connecting plate on the test baseboard is equal to the orthographic projection size of the top connecting plate on the test baseboard and equal to the orthographic projection size of the chip on the test baseboard. This allows for testing of the corresponding chip by connecting only one test board of similar size to the chip on the test baseboard, greatly reducing the space occupied by the test board. Furthermore, the smaller test board results in shorter internal wiring, thereby enhancing the integrity of high-speed signal transmission and improving testing efficiency. Attached Figure Description

[0016] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0017] Figure 1 This is a schematic diagram of the structure of the test fixture used in the prior art;

[0018] Figure 2 This is a block diagram of the testing system provided in the embodiments of this application;

[0019] Figure 3 This is a schematic diagram of the structure of the test fixture provided in the embodiments of this application;

[0020] Figure 4 This is a schematic diagram of the structure of the test base plate provided in the embodiments of this application;

[0021] Figure 5 This is a schematic diagram of the chip structure provided in the embodiments of this application;

[0022] Figure 6 yes Figure 3 A magnified schematic diagram of a portion of region A in the middle;

[0023] Figure 7 yes Figure 4 A magnified schematic diagram of a portion of region B in the middle;

[0024] Figure 8 This is a top view of the test board provided in the embodiments of this application;

[0025] Figure 9 This is a bottom view of the test board provided in the embodiments of this application;

[0026] Figure 10 This is a side view of the test board provided in an embodiment of this application.

[0027] Wherein: 10, Test System; 100, Test Fixture; 110, Test Base Plate; 111, First Connecting Pad Area; 112, Current Detection Module; 113, PMU Module; 114, SOC Module; 115, eMMC Module; 120, Test Board; 121, Bottom Connecting Board; 122, Top Connecting Board; 123, Second Connecting Pad Area; 124, Third Connecting Pad Area; 125, First Connecting Pad; 126, Second Connecting Pad; 127, Third Connecting Pad; 128, First 129. Identification section; 130. Second identification section; 131. Third identification section; 132. Fourth identification section; 140. Extension board; 141. Test pad; 142. Sub-pad; 143. First extension board; 144. Second extension board; 145. Third extension board; 146. Fourth extension board; 147. First arc-shaped section; 148. Second arc-shaped section; 149. Third arc-shaped section; 150. Fourth arc-shaped section; 160. Chip; 161. Fourth connection pad; 200. Display; 300. Test socket. Detailed Implementation

[0028] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0029] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of indicated technical features. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean a non-exclusive inclusion, which may include or add one or more other features, integers, steps, operations, units, components, and / or combinations thereof. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0030] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Figure 2 This is a block diagram of the test system 10 provided in this application embodiment, as shown below. Figure 1 As shown, this application discloses a testing system 10 for chip testing, including a test fixture 100 and a display 200. The display 200 is disposed on one side of the test fixture 100 and electrically connected to the test fixture 100. When the chip is placed on the test fixture 100 and connected to the test fixture 100, the chip can be tested, and the test results can be displayed on the display 200.

[0032] Figure 3 This is a schematic diagram of the structure of the test fixture 100 provided in the embodiments of this application. Figure 4 This is a schematic diagram of the structure of the test base plate 110 provided in the embodiments of this application, as shown below. Figures 3-4 As shown, the test fixture 100 includes a test base plate 110 and a test board 120. The test board 120 is disposed on the test base plate 110. The test base plate 110 is provided with a first connection pad area 111. The test board 120 includes a bottom connection plate 121 and a top connection plate 122 fixedly connected. The top connection plate 122 is disposed on the side of the bottom connection plate 121 away from the test base plate 110. The chip 160 is disposed on the top connection plate 122 and connected to the first connection pad area 111 through the top connection plate 122 and the bottom connection plate 121. The size of the orthographic projection of the bottom connection plate 121 on the test base plate 110 is equal to the size of the orthographic projection of the top connection plate 122 on the test base plate 110 and equal to the size of the orthographic projection of the chip 160 on the test base plate 110.

[0033] Compared to traditional test boards 120, which require connection to test base plates 110 via BTB connectors for routine signal testing and have densely packed electronic components, making it impossible to accommodate the large test board 120 and test socket, the test fixture 100 of this application includes a test base plate 110 and a test board 120. The test board 120 is mounted on the test base plate 110, which has a first connection pad area 111. The test board 120 includes the test base plate 110 and the test board 120, and includes a bottom connection plate 121 and a top connection plate 122 fixedly connected. The top connection plate 122 is located on the side of the bottom connection plate 121 away from the test base plate 110. The chip 160 is mounted on the top connection plate 122 and connected to the first connection pad area 121 via the top connection plate 122 and the bottom connection plate 121. The pad area 111 is connected to the circuit on the test base plate 110 to realize the performance testing of the chip 160. The size of the orthographic projection of the bottom connecting plate 121 on the test base plate 110 is equal to the size of the orthographic projection of the top connecting plate 122 on the test base plate 110, and is also equal to the size of the orthographic projection of the chip 160 on the test base plate 110. That is, the use of test sockets is eliminated, and the board-to-board connection method is changed to an integrated test board. In this way, only one test board 120 of the same size as the chip 160 needs to be connected to the test base plate 110 to test the corresponding chip 160, which greatly reduces the space occupied by the test board 120. Moreover, the internal wiring of the smaller test board 120 is also much shorter, thereby enhancing the integrity of high-speed signal transmission and improving test efficiency.

[0034] The chip 160 was verified by the test board 120, which showed that the test board 120 could correctly capture data during the write operation and ensure that the data could be properly latched and the write operation completed. Specifically, Figure 5 This is a schematic diagram of the chip structure provided in the embodiments of this application. Figure 6 yes Figure 3 A magnified schematic diagram of a portion of region A in the middle; Figure 7 yes Figure 4 A magnified schematic diagram of a portion of region B. Figure 8 This is a top view of the test board 120 provided in this embodiment of the application. Figure 9 This is a bottom view of the test board 120 provided in the embodiments of this application, combined with... Figures 6-9 It can be seen that the bottom connecting plate 121 has a second connecting pad area 123 on the side near the test base plate 110, and the top connecting plate 122 has a third connecting pad area 124 on the side away from the bottom connecting plate 121. The first connecting pad area 111 is electrically connected to the third connecting pad area 124 through the second connecting pad area 123; combined with Figure 5-6It can be seen that the chip 160 can be directly placed in the third connection pad area 124; wherein, the size of the first connection pad area 111 is equal to the size of the second connection pad area 123 and the size of the third connection pad area 124. Therefore, the bottom connection plate 121 and the top connection plate 122 are of similar structural size.

[0035] Furthermore, the number of the first connection pad 125, the number of the second connection pad 126, the number of the third connection pad 127, and the number of the fourth connection pad can all be equal. That is, using the test fixture 100, only one type of chip can be tested. The chip 160 can be LPDDR4X. Of course, it can also be designed according to the type of chip to be tested, and can be used for testing other types of chips. Moreover, it can be designed to test multiple types of chips. The specific design depends on the requirements, and no limitation is made here.

[0036] The first connection pad area 111, the second connection pad area 123, and the third connection pad area 124 are all rectangular structures; for example Figures 7-8 As shown, the test fixture 100 further includes an extension plate 140, which is disposed on at least one side of the top connecting plate 122 and is horizontally disposed with the top connecting plate 122. The extension plate 140 is provided with test pads 141. The first connecting pad area 111 is provided with a plurality of first connecting pads 125, the second connecting pad area 123 is provided with a plurality of second connecting pads 126, the third connecting pad area 124 is provided with a plurality of third connecting pads 127, and the fourth connecting pad area is provided with a plurality of fourth connecting pads. The fourth connecting pads are connected to the first connecting pads 125 through the third connecting pads 127. The test pads 141 are electrically connected to the third connecting pads 127. In this way, after connecting the fourth connecting pads 161 and the third connecting pads 127 on the chip 160, the test status of the chip 160 can be directly obtained by connecting the test pads 141 to the corresponding test tools, which is convenient to operate.

[0037] Of course, the third connection pad 127 is connected to the second connection pad 126 through a connection circuit, and the third connection pad 127 is connected to the test pad 141 through a test circuit. The test base plate 110 also has a connection circuit inside, which connects the first connection pad 125 to other electronic components. The other electronic components include a current detection module 112, a PMU module, a SOC module, and an eMMC module. The current detection module can monitor the operating current of LPDDR4X in real time. The PMU module can provide precise voltage management for LPDDR4X to ensure that it can still operate efficiently in low power mode. The SOC determines the overall data processing capability and bus bandwidth of the system. Its interface bandwidth and protocol standard with LPDDR4X directly affect the data transmission rate of LPDDR4X. During system operation, eMMC is mainly responsible for storing a large amount of data and programs, while LPDDR4X is used as memory to temporarily store running programs and data. When the CPU needs to read data or instructions, the eMMC reads the data from the storage medium and transmits it to the LPDDR4X. Then the CPU quickly reads the data from the LPDDR4X for processing in order to test the chip 160. The various connection circuits or test circuits are not part of the main invention of this application and will not be described in detail here.

[0038] Figure 10 This is a side view of the test board 120 provided in an embodiment of this application, as shown below. Figure 10 As shown, the thickness of the bottom connecting plate 121 is 1.8mm-2mm, and the thickness of the top connecting plate 122 is 1mm-1.5mm. In this way, after the second connecting pad 126 is soldered to the first connecting pad 125, it can avoid covering other electronic components around the test base plate 110 and affecting the use of other electronic components. At the same time, it can also avoid the bottom connecting plate 121 being affected by the height of the electronic components around the test base plate 110, which would lead to unstable soldering, thereby improving the testing stability.

[0039] like Figures 8-9As shown, the top connecting plate 122 has a rectangular structure. The extension plate 140 includes a first extension plate 143, a second extension plate 144, a third extension plate 145, and a fourth extension plate 146. The first extension plate 143, the second extension plate 144, the third extension plate 145, and the fourth extension plate 146 surround the top connecting plate 122. The first extension plate 143 and the third extension plate 145 are arranged opposite to each other, and the second extension plate 144 and the fourth extension plate 146 are arranged opposite to each other. The test pads 141 include multiple sub-pads 142, which are respectively arranged on the first extension plate 143, the second extension plate 144, the third extension plate 145, and the fourth extension plate 146. That is, test pads 141 are provided around the top connecting plate 122, which can also be used to add special signals that need to be tested by the chip 160, so as to realize the detection of special signals and the test effect is better and more comprehensive.

[0040] The sub-pad 142 is a hole-shaped structure with a plug hole in the middle, so that the pin can be inserted into the plug hole to transmit the signal. The insertion is stable and ensures that the test signal is uninterrupted.

[0041] In addition, combined Figures 8-9 It can be seen that the second extension board 144 is significantly smaller than the fourth extension board 146. Specifically, the area of ​​the orthographic projection of the second extension board 144 onto the test base plate 110 is smaller than the area of ​​the orthographic projection of the fourth extension board 146 onto the test base plate 110. Furthermore, the number of sub-pads 142 on the second extension board 144 is less than the number of sub-pads 142 on the fourth extension board 146. Because the wiring is based on the signal lines of the internal connection circuit, important signal lines need to be lengthened. Some signal lines are relatively short, requiring the test pads 141 to be placed further away to lengthen them; others are relatively long, requiring the test pads 141 to be placed closer to shorten them. Therefore, this arrangement prevents the internal signal lines from intersecting, overlapping, or pulling against each other, thereby extending the lifespan of the signal lines.

[0042] Combination Figures 6-7The first connecting pad area 111 has a first marking portion 128, a second marking portion 129, a third marking portion 130, and a fourth marking portion 131 at its four corners, respectively, indicating copper leakage at the four corners of the first connecting pad area 111. The first extension plate 143 and the second extension plate 144 are connected to form a first arc-shaped portion 147; the second extension plate 144 and the third extension plate 145 are connected to form a second arc-shaped portion 148; the third extension plate 145 and the fourth extension plate 146 are connected to form a third arc-shaped portion 149; and the fourth extension plate 146 and the first extension plate 143 are connected to form a fourth arc-shaped portion 150. The first arc-shaped portion 147 and the first marking portion... The second arc-shaped portion 148 corresponds to the second marking portion 129, the third arc-shaped portion 149 corresponds to the third marking portion 130, and the fourth arc-shaped portion 150 corresponds to the fourth marking portion 131. When the bottom connecting plate 121 is soldered to the test base plate 110, by observing whether at least two arc-shaped portions on the top, bottom, left, or right are aligned with the corresponding marking portions, it can be confirmed that the second connecting pad area 123 on the bottom connecting plate 121 is aligned with the first connecting pad area 111 on the test base plate 110, and all connecting pads are also aligned, so as to avoid open circuits caused by the test plate 120 blocking the view and making it impossible to confirm the package position when soldering the test plate 120 to the test base plate 110.

[0043] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0044] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A test fixture for testing of a chip, the test fixture comprising a test board and a test plate, the test plate being arranged on the test board, a first connection pad area being arranged on the test board, characterized in that, The test board comprises a fixedly connected bottom connecting plate and a top connecting plate, the top connecting plate is arranged on the side of the bottom connecting plate away from the test base plate, the chip is arranged on the top connecting plate, and the chip is connected to the first connecting pad area for testing through the top connecting plate and the bottom connecting plate; The size of the orthographic projection of the bottom connecting plate on the test base plate is equal to the size of the orthographic projection of the top connecting plate on the test base plate, and is equal to the size of the orthographic projection of the chip on the test base plate.

2. The test fixture of claim 1, wherein, The side of the bottom connecting plate close to the test base plate is provided with a second connecting pad area, the side of the top connecting plate away from the bottom connecting plate is provided with a third connecting pad area, the first connecting pad area is electrically connected with the third connecting pad area through the second connecting pad area; the side of the chip close to the top connecting plate is provided with a fourth connecting pad area, the chip is placed on the third connecting pad area, and the fourth connecting pad area is electrically connected with the third connecting pad area. The size of the first connecting pad area is equal to the size of the second connecting pad area and the size of the third connecting pad area.

3. The test fixture of claim 2, wherein, The first connecting pad area, the second connecting pad area and the third connecting pad area are all rectangular structures. The test fixture further comprises an extension plate, the extension plate is arranged on at least one side of the top connecting plate and is arranged horizontally with the top connecting plate, the extension plate is provided with a test pad, the first connecting pad area is provided with a plurality of first connecting pads, the second connecting pad area is provided with a plurality of second connecting pads, the third connecting pad area is provided with a plurality of third connecting pads, the fourth connecting pad area is provided with a plurality of fourth connecting pads, the fourth connecting pad is connected to the first connecting pad through the third connecting pad and the third connecting pad, and the test pad is electrically connected with the third connecting pad.

4. The test fixture of claim 3, wherein, The top connecting plate is a rectangular structure, the extension plate comprises a first extension plate, a second extension plate, a third extension plate and a fourth extension plate, the first extension plate, the second extension plate, the third extension plate and the fourth extension plate are arranged around the top connecting plate, the first extension plate and the third extension plate are arranged opposite to each other, the second extension plate and the fourth extension plate are arranged opposite to each other, and the test pad comprises a plurality of sub-pads, and the plurality of sub-pads are arranged on the first extension plate, the second extension plate, the third extension plate and the fourth extension plate respectively.

5. The test fixture of claim 4, wherein, The sub-pad is a hole structure with a plug hole in the middle.

6. The test fixture of claim 4, wherein, The first connecting pad area is provided with a first identification part, a second identification part, a third identification part and a fourth identification part at four corners respectively, a first arc-shaped part is formed by connecting the first extension plate and the second extension plate, a second arc-shaped part is formed by connecting the second extension plate and the third extension plate, a third arc-shaped part is formed by connecting the third extension plate and the fourth extension plate, and a fourth arc-shaped part is formed by connecting the fourth extension plate and the first extension plate. The first arc-shaped part corresponds to the first identification part, the second arc-shaped part corresponds to the second identification part, the third arc-shaped part corresponds to the third identification part, and the fourth arc-shaped part corresponds to the fourth identification part.

7. The test fixture of claim 4, wherein, The area of the orthographic projection of the second extension plate on the test board is less than the area of the orthographic projection of the fourth extension plate on the test board; and the number of the sub-pads on the second extension plate is less than the number of the sub-pads on the fourth extension plate.

8. The test fixture of claim 1, wherein, The thickness of the bottom connecting plate is 1.8mm-2mm, and the thickness of the top connecting plate is 1mm-1.5mm.

9. The test fixture of claim 3, wherein, The number of the first connecting pads, the number of the second connecting pads, the number of the third connecting pads and the number of the fourth connecting pads are equal.

10. A test system, characterized by The test fixture comprises a display, and the display is arranged on one side of the test fixture and is electrically connected with the test fixture.