Semiconductor package

Abstract

Some embodiments of the present disclosure provide a semiconductor package including an interposer, a first semiconductor wafer disposed over the interposer and having a first surface and a second surface opposite each other, and a second semiconductor wafer disposed over the first semiconductor wafer and having a top surface and a bottom surface opposite each other. The semiconductor package further includes a dielectric sidewall disposed along a side of the first semiconductor wafer and over the interposer, wherein at least one first via structure is disposed vertically through the dielectric sidewall of the first semiconductor wafer and electrically connected to a power distribution network.

Description

Technical Field

[0001] This disclosure relates to semiconductor packaging. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the iterative reduction in the smallest feature size (e.g., shrinking semiconductor process nodes towards sub-nanometer nodes), thus allowing more components to be integrated into a given area. With the recent growth in demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and lower latency, the need for smaller and more innovative packaging technologies for semiconductor chips is also increasing. Utility Model Content

[0003] According to some embodiments of this disclosure, a semiconductor package includes an interposer, a first semiconductor wafer disposed above the interposer and having a first surface and a second surface opposite to each other, a second semiconductor wafer disposed above the first semiconductor wafer and having a top surface and a bottom surface opposite to each other, and a dielectric sidewall disposed along one side of the first semiconductor wafer and above the interposer, wherein at least one first via structure perpendicularly passes through the dielectric sidewall and is electrically connected to a power distribution network.

[0004] According to some embodiments of the present disclosure, a semiconductor package includes a first semiconductor wafer disposed above an interposer and having a first surface and a second surface opposite to each other, and at least one dielectric sidewall disposed along one side of the first semiconductor wafer and above the interposer, wherein at least one first via structure passes perpendicularly through the dielectric sidewall and is electrically connected to a power distribution network via the interposer.

[0005] According to some embodiments of this disclosure, a semiconductor package includes a first semiconductor wafer having a first surface and a second surface opposite to each other, wherein the first semiconductor wafer includes a dielectric sidewall along one side of the first semiconductor wafer and at least one first via structure perpendicularly passing through the dielectric sidewall. The semiconductor package also includes metal wiring on the back side of the first semiconductor wafer and connected to the first via structure, a plurality of first hybrid bonds between the first surface of the first semiconductor wafer and the top surface of an interposer below the first semiconductor wafer, and a plurality of second hybrid bonds between the second surface of the first semiconductor wafer and the bottom surface of a second semiconductor wafer above the first semiconductor wafer, wherein the first semiconductor wafer is bonded to the interposer via the first hybrid bonds and to the second semiconductor wafer via the second hybrid bonds. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A schematic illustration of a cross-sectional view of an example semiconductor package according to some embodiments;

[0008] Figure 2 This illustration illustrates an example semiconductor package according to an embodiment.

[0009] Figure 3 This illustration illustrates another example of a semiconductor package according to another embodiment;

[0010] Figure 4 A more detailed schematic illustration of a cross-sectional view of an example semiconductor package according to some embodiments;

[0011] Figure 5 This illustration shows a cross-sectional view of an example hybrid bonding structure including a first interface structure and a second interface structure according to some embodiments.

[0012] Figure 6 This is an example flowchart of a method for manufacturing a semiconductor package according to some embodiments.

[0013] [Symbol Explanation]

[0014] 100, 200, 300, 400: Semiconductor packages

[0015] 101: Dielectric sidewall

[0016] 102: Stacking of Dies / Chips / Memory

[0017] 103: Dielectric sidewall

[0018] 104: Die / Wafer

[0019] 104B: Second surface / back surface / back side

[0020] 104F: First surface / front surface / front side

[0021] 106: Redistributed Structure / Intermediate Layer

[0022] 108: Microbumps

[0023] 109: Metal Cap

[0024] 110: Packaging substrate

[0025] 112: Conductive connector

[0026] 116: Silicon portion

[0027] 118: Redistribution layer section

[0028] 122: Memory Layer

[0029] 122A: Memory Layer / First Layer

[0030] 122B: Memory Layer / Second Layer

[0031] 122C: Memory Layer

[0032] 124: Logical Foundation Layer

[0033] 132: First through-hole structure / dielectric via

[0034] 134: Second Through-Hole Structure / Silicon Vias

[0035] 136: Metal wiring

[0036] 142: Bonding pad metal

[0037] 144: Bonding pad metal

[0038] 152: Bonding pad metal

[0039] 154: Bonding pad metal

[0040] 162: Bonding pad metal

[0041] 164: Bonding pad metal

[0042] 500: Hybrid Joint Structure

[0043] 502: First Interface Structure

[0044] 502F: Bottom surface / Front surface

[0045] 504: Second Interface Structure

[0046] 504F: Top surface / Front surface

[0047] 522: Bonding pad metal

[0048] 524: Bonding pad metal

[0049] 600: Method

[0050] 602, 604, 606, 608: Steps

[0051] L1, L2: Length

[0052] W1, W2: Width Detailed Implementation

[0053] To achieve the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0054] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly. The reference to “or” may be interpreted inclusively, such that any term described using “or” may refer to a single, more than one, or any of the terms described.

[0055] With the further development of semiconductor technology, stacked semiconductor devices, such as 3D integrated circuits (3DICs or 3D-ICs), have become an effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic circuits, memory circuits, processor circuits, and the like are fabricated on different semiconductor wafers (or substrates), thereby forming corresponding semiconductor wafers (or dies). Two or more semiconductor wafers can be arranged on top of each other to further reduce the form factor of the stacked semiconductor device.

[0056] Two or more semiconductor wafers or dies (such as bottom dies, top dies, and intermediate dies) can be bonded together using suitable bonding techniques, such as hybrid bonding, microbump bonding, direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, and / or similar techniques. Electrical connections can be provided between stacked semiconductor dies based on multiple through-hole structures, such as through-substrate vias (TSVs) (e.g., through-silicon vias) or similar techniques.

[0057] This disclosure relates to a semiconductor package for a three-dimensional integrated circuit. The semiconductor package includes an interposer, a first semiconductor wafer disposed on the interposer and having a first surface and a second surface opposite to each other, a second semiconductor wafer disposed on the first semiconductor wafer and having a top surface and a bottom surface opposite to each other, and a dielectric sidewall disposed along one side of the first semiconductor wafer and above the interposer. At least one first via structure, such as a through dielectric via (TDV), is disposed perpendicularly through the dielectric sidewall of the first semiconductor wafer and electrically connected to a power distribution network (PDN).

[0058] In some embodiments, a first semiconductor wafer and an interposer are bonded to each other by a plurality of first hybrid bonds formed between their opposing surfaces. In some embodiments, a first semiconductor wafer and a second semiconductor wafer are bonded to each other by a plurality of second hybrid bonds formed between their opposing surfaces. In some embodiments, the second semiconductor wafer is a memory stack comprising a plurality of memory layers stacked on top of each other and subsequently stacked on a logic baselayer. In some embodiments, the first and second layers of the plurality of memory layers of the memory stack are bonded to each other by a plurality of third hybrid bonds formed between their opposing surfaces. In some embodiments, the first semiconductor wafer is a graphics processing unit (GPU) wafer. In some embodiments, the memory stack is a high bandwidth memory (HBM) stack.

[0059] Using such schemes and structures, such as dielectric vias that pass vertically through the dielectric sidewalls of the first semiconductor wafer and are electrically connected to the power distribution network, and direct hybrid bonding structures, the required interface layers are reduced, the interface thermal resistance is decreased, and an independent power distribution network is provided, thereby advantageously improving the system integration and power integration of semiconductor packaging for three-dimensional integrated circuits.

[0060] Figure 1 Cross-sectional views of a semiconductor package 100 (or semiconductor device) according to various embodiments of the present disclosure are illustrated. In one embodiment, the semiconductor package 100 may sometimes be referred to as a three-dimensional integrated circuit (sometimes referred to as a "3D integrated circuit"), wherein multiple semiconductor devices (sometimes referred to as "wafers" or "dies") of two or more layers are stacked on top of each other. It should be understood that the semiconductor package 100 is simplified for illustrative purposes, and therefore the configuration of the elements or devices of the semiconductor package 100 may be configured in a variety of other ways, and / or the semiconductor package 100 may include any other elements or devices while remaining within the scope of this disclosure.

[0061] In some embodiments of this disclosure, the semiconductor package 100 includes a first die 102 (or wafer) and a second die 104 (or wafer) stacked on top of each other. The first die 102 and the second die 104 may be joined to each other by suitable bonding techniques, such as hybrid bonding, microbumping, direct bonding, chemically activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, or similar combinations thereof.

[0062] In one embodiment of this disclosure, the top die 102 may include multiple active circuits, devices, elements, or loads, such as system-on-chip (SoC) devices, high-bandwidth memory devices, or the like, while the bottom die 104 may include one or more passive circuits, devices, and / or loads, such as integrated active devices, integrated voltage regulators, or the like. In another embodiment of this disclosure, the top die 102 may include both active and passive circuits, devices, and / or loads, and the bottom die 104 may also include both active and passive circuits, devices, and / or loads. In yet another embodiment of this disclosure, the top die 102 may include passive circuits, devices, and / or loads, while the bottom die 104 may also include active circuits, devices, and / or loads.

[0063] In some embodiments of this disclosure, the semiconductor package 100 further includes a redistribution structure 106 connected to the bottom wafer 104. It should be understood that... Figure 1The redistribution structure 106 shown is merely schematic. The redistribution structure 106 may include multiple redistribution lines (RDLs), such as metal traces (or metal connections), and vias located above or below the metal traces and connected to them; all such vias are sometimes referred to as RDL wiring. Such RDL wiring may be shown later in one or more of the figures below. In some embodiments, the redistribution structure 106 may be a semiconductor interposer, which may be a thin semiconductor substrate located between two or more wafers or dies, allowing the wafers or dies to communicate and work together, thereby providing, for example, signal routing, power distribution, or even thermal management.

[0064] In some embodiments of this disclosure, the redistribution structure 106 RDL is formed by an electroplating process, wherein each of the RDLs includes a seed layer (not shown) and an electroplated metal material above the seed layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or the like. Subsequently, a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to allow for patterning. The pattern of the photoresist corresponds to the RDL. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by electroplating, such as electroplating or electroless plating or the like. The seed layer and the electroplated metal material can be formed from the same material or different materials. The conductive material can be a metal, such as copper, titanium, tungsten, aluminum, or the like. Subsequently, the photoresist and the portion of the seed layer on which no conductive material is formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as wet and / or dry etching. Thus, the remaining portion of the seed layer and conductive material forms the redistribution structure 106 RDL.

[0065] In some embodiments of this disclosure, the semiconductor package 100 further includes a plurality of microbumps 108 connecting (e.g., electrically connecting) the redistribution structure 106 to the package substrate 110. The microbumps 108 may be metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using an electroless nickel-electroless palladium-immersion gold technique (ENEPIG), ball grid array (BGA) bumps, or the like. In one embodiment, the microbump 108 is a C4 bump. The microbumps 108 may be formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition (CVD), or the like. The microbumps 108 may be solderless and have substantially vertical sidewalls. In some embodiments, a plurality of metal caps 109 are formed on top of the microbumps 108. In some embodiments, the metal cap 109 may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like or combinations thereof, and may be formed by an electroplating process.

[0066] In some embodiments of this disclosure, the package substrate 110 may be, for example, a printed circuit board (PCB) or the like, and may be electrically connected to intermediate packages (e.g., top die 102 and bottom die 104 bonded to redistribution structure 106) using microbumps 108. The package substrate 110 may be made of semiconductor materials such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium phosphide indium, combinations thereof, and the like may also be used as semiconductor materials for the package substrate 110. Additionally, the package substrate 110 may be a silicon on insulator (SOI) substrate. Typically, an SOI substrate comprises a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SiGe on insulator, SGOI), or combinations thereof. In an alternative embodiment, the package substrate 110 is based on an insulating core, such as a glass fiber reinforced resin core. One example core material is a glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or alternatively, other PCB materials or films. Stacked films such as Ajinomoto Build-up (ABF) film or other layers can be used for encapsulating substrate 110.

[0067] In some embodiments of this disclosure, the package substrate 110 may include a metallization layer and vias, as well as bonding pads (not shown) above the metallization layer and vias. The metallization layer is designed to connect various devices to form a functional circuit system, sometimes referred to as package wiring. The metallization layer may be formed of alternating layers of dielectric (e.g., a low-dielectric-constant dielectric material) and conductive material (e.g., copper), with vias interconnecting the conductive material layers, and may be formed by any suitable process, such as deposition, damascene, dual damascene, or the like. Such package wiring may be shown later in one or more of the figures below.

[0068] In some embodiments of this disclosure, such as Figure 1 As shown, the semiconductor package 100 further includes a plurality of conductive connectors 112 disposed on the back side of a package substrate 110, wherein the back side of the package substrate 110 is opposite to the front side of the package substrate 110 facing the redistribution structure 106. In some embodiments, the conductive connectors 112 may be formed of a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive connectors 112 are formed by first forming a solder layer using methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer is formed on the structure, reflow can be performed to shape the conductive connectors 112 into a desired bump shape. In some embodiments, such conductive connectors 112 may operate as package pins of the semiconductor package 100 for receiving one or more power supply voltages. In some embodiments, some of the conductive connectors 112 are electrically connected to a power distribution network (not shown).

[0069] Further details regarding the components or devices and bonding structures of the semiconductor package 100 will be provided in this disclosure. Figures 2 to 6 To describe. Figure 2 The layout and configuration of an example semiconductor package 200 according to embodiments of the present disclosure are schematically illustrated. In some embodiments, such as Figure 2As shown in the top and cross-sectional views, the semiconductor package 200 includes an interposer 106, a plurality of (e.g., 3×3) first semiconductor wafers 104 (such as a GPU) disposed on the interposer 106, and a plurality of (e.g., 3×3) second semiconductor wafers 102 (such as 3×3 memory stacks 102) disposed on the plurality of (e.g., 3×3) first semiconductor wafers 104 respectively. In some embodiments, the memory stacks 102 are high-bandwidth memory. In some embodiments, each of the memory stacks 102 includes a plurality of memory layers 122 (such as memory layer 122A, memory layer 122B, memory layer 122C, etc.) stacked on top of each other. Figure 4 (As shown). In some embodiments, the plurality of memory layers 122 of each of the memory stacks 102 include a plurality of high-bandwidth memory layers and / or a dynamic random access memory (DRAM) stack. In some embodiments, the memory stack 102 may include a DRAM stack. In some embodiments, a plurality of first semiconductor wafers 104 are laterally separated from each other by a plurality of their first dielectric sidewalls 103. In some embodiments, a plurality of second semiconductor wafers 102 are laterally separated from each other by a plurality of their second dielectric sidewalls 101. In some embodiments, the area of ​​each of the plurality of first semiconductor wafers 104 is in the range of about 14.5 mm (length L1) × 14.5 mm (width W1) to about 20.5 mm (length L1) × 20.5 mm (width W1), and the area of ​​each of the plurality of second semiconductor wafers 102 is in the range of about 13 mm (length L2) × 13 mm (width W2) to about 19 mm (length L2) × 19 mm (width W2). In some embodiments, the ratio of the area of ​​each of the first semiconductor wafers 104 to the area of ​​each of the second semiconductor wafers 102 is in the range of about 0.6 to about 2.5.

[0070] Figure 3 A schematic illustration shows another example semiconductor package 300 according to another embodiment of the present disclosure. In some embodiments, such as Figure 3 As shown in the top view and cross-sectional view, the semiconductor package 300 includes an interposer 106, a first semiconductor wafer 104 disposed on the interposer 106, and a plurality of (e.g., 2×2) second semiconductor wafers 102 disposed on the first semiconductor wafer 104. Figure 3 As shown, different Figure 2As shown, in some embodiments, a plurality of smaller second semiconductor wafers 102 may rest on the top surface of a single first semiconductor wafer 104. In some embodiments, the first semiconductor wafer 104 is a GPU, and the second semiconductor wafers 102 are memory stacks. In some embodiments, each of the memory stacks 102 includes a plurality of memory layers 122 (such as memory layer 122A, memory layer 122B, memory layer 122C, etc.) stacked on top of each other (e.g., ...). Figure 4 (As shown). In some embodiments, each of the memory layers 122 in the memory stack 102 includes a plurality of high-bandwidth memory layers and / or DRAM stacks. In some embodiments, the first semiconductor wafer 104 includes a plurality of first dielectric sidewalls 103 that laterally separate the first semiconductor wafer 104 from other adjacent first semiconductor wafers 104. In some embodiments, the plurality of second semiconductor wafers 102 include a plurality of second dielectric sidewalls 101 that laterally separate adjacent second semiconductor wafers 102 from each other.

[0071] Figure 4 More detailed schematic illustrations are provided for some embodiments corresponding to this disclosure. Figure 1 A cross-sectional view of an example semiconductor package 400, shown in the example semiconductor package 100. It should be noted that... Figure 4 The cross-sectional views are for illustrative purposes only and should not be construed as limiting the scope of this disclosure. For example, the relative configurations of the apparatus illustrated in the cross-sectional views may be reconfigured while remaining within the scope of this disclosure.

[0072] In some embodiments of this disclosure, the semiconductor package 400 includes an interposer 106, a first semiconductor wafer 104 disposed on the interposer 106 and having a first surface 104F (e.g., on the front side) and a second surface 104B (e.g., on the back side) opposite each other, a second semiconductor wafer 102 (such as a memory stack) disposed on the first semiconductor wafer 104 and having a top surface and a bottom surface opposite each other, and a dielectric sidewall 103 disposed along the side of the first semiconductor wafer 104 and above the interposer 106.

[0073] In some embodiments, one or more first via structures 132 (such as dielectric vias) are disposed vertically through the dielectric sidewalls 103 of the first semiconductor wafer 104. In some embodiments, the dielectric vias 132 are electrically connected to a power distribution network (not shown) via an interposer 106, thereby vertically delivering power through the first semiconductor wafer 104 to other devices of the semiconductor package 400 (such as a second semiconductor wafer 102). In some embodiments, the first semiconductor wafer 104 is a GPU wafer. In some embodiments, the second semiconductor wafer 102 is a memory stack. In some embodiments, the memory stack 102 is a high-bandwidth memory stack. In some embodiments, the high-bandwidth memory stack 102 includes a logic base layer 124 and a plurality of high-bandwidth memory layers 122 (such as memory layer 122A, memory layer 122B, memory layer 122C, etc.) disposed above the logic base layer 124 and stacked on top of each other.

[0074] In some embodiments, the first semiconductor wafer 104 is flipped such that its front side 104F faces the top surface of the interposer 106, and its back side 104B faces the bottom surface of the second semiconductor wafer 102. In some embodiments, the first semiconductor wafer 104 includes a silicon portion 116, a redistribution layer portion 118, and a second via structure 134 (such as a through-silicon via or TSV) through the silicon portion 116. In some embodiments, the dielectric via 132 extends a greater vertical distance than the through-silicon via 134. In some embodiments, the first semiconductor wafer 104 includes a metal wiring 136 on its back side 104B. In some embodiments, the metal wiring 136 is electrically connected to the dielectric via 132 and the through-silicon via 134. In some embodiments, the metal wiring 136 is made of a metallic material such as copper, titanium, tungsten, aluminum, or the like.

[0075] In some embodiments of this disclosure, a first semiconductor wafer 104 and an interposer 106 are bonded together by a plurality of first hybrid bonds formed between a front surface 104F of the first semiconductor wafer 104 and a top surface of the interposer 106. In some embodiments of this disclosure, the plurality of first hybrid bonds are formed by a plurality of first bonding pad metals (BPMs) 142 embedded in and flush with the front surface 104F of the first semiconductor wafer 104 and a plurality of second bonding pad metals 144 embedded in and flush with the top surface of the interposer 106. The plurality of first bonding pad metals 142 and the plurality of second bonding pad metals 144 are aligned and contacting each other, and thus attached to each other, thereby eliminating any space or gap between the front surface 104F of the first semiconductor wafer 104 and the top surface of the interposer 106. Thus, the thermal resistance between the front surface 104F of the first semiconductor wafer 104 and the top surface of the interposer 106 is significantly reduced.

[0076] Figure 5 A cross-sectional view of an example hybrid bonding structure 500 including a first interface structure 502 and a second interface structure 504 according to some embodiments of the present disclosure is illustrated. In some embodiments, the first interface structure 502 and the second interface structure 504 are made of a dielectric material, and a flat bottom surface 502F (e.g., a front surface) of the first interface structure 502 is configured to face a flat top surface 504F (e.g., a front surface) of the second interface structure 504. In some embodiments, a plurality of first bonding pad metals 522 are embedded in and flush with the flat bottom surface 502F of the first interface structure 502, and a plurality of second bonding pad metals 524 are embedded in and flush with the flat top surface 504F of the second interface structure 504. When the plurality of first bonding pad metals 522 and the plurality of second bonding pad metals 524 are aligned and attached to each other, a (face-to-face) direct hybrid bond is formed between the first interface structure 502 and the second interface structure 504 through the plurality of first bonding pad metals 522 on the flat front surface 502F of the first interface structure 502 and the plurality of second bonding pad metals 524 on the flat front surface 504F of the second interface structure 504.

[0077] like Figure 5 The direct hybrid bonding structure shown can be implemented between the flat surface of the first semiconductor wafer 104 and the interposer 106 as described above. Figure 5 The direct hybrid bonding structure shown can also be used in, for example... Figure 4The first semiconductor wafer 104 and the second semiconductor wafer 102 shown are implemented between flat surfaces. In some embodiments, the second semiconductor wafer 102 is a memory stack, wherein the memory stack includes, for example, Figure 4 The diagram shows multiple memory layers 122 (such as memory layer 122A, memory layer 122B, memory layer 122C, etc.) stacked on top of each other and subsequently stacked on the logic base layer 124. Figure 5 The direct hybrid bonding structure shown can also be implemented between the flat surfaces of adjacent layers of memory stack 102. (See below for reference.) Figure 4 Let's explain more details.

[0078] like Figure 4 As shown, in some embodiments, a first semiconductor wafer 104 and a second semiconductor wafer 102 are bonded to each other by a direct hybrid bonding, which is formed between the back surface 104B of the first semiconductor wafer 104 and the bottom surface of the second semiconductor wafer 102. In some embodiments, the direct hybrid bonding is formed by a plurality of third bonding pad metals 154 embedded in and flush with the back surface 104B of the first semiconductor wafer 104 and a plurality of fourth bonding pad metals 152 embedded in and flush with the bottom surface of the second semiconductor wafer 102. In some embodiments, the plurality of third bonding pad metals 154 and the plurality of fourth bonding pad metals 152 are aligned and in contact with each other, thereby forming a direct hybrid bonding between the back surface 104B of the first semiconductor wafer 104 and the bottom surface of the second semiconductor wafer 102. Therefore, there is no space or gap between the back surface 104B of the first semiconductor wafer 104 and the bottom surface of the second semiconductor wafer 102.

[0079] Similarly, as Figure 4As shown, in some embodiments, the second semiconductor wafer 102 is a memory stack 102 (e.g., a DRAM stack). In some embodiments, the memory stack 102 is a high-bandwidth memory stack 102. In some embodiments, the memory stack 102 includes a plurality of memory layers 122 (such as memory layer 122A, memory layer 122B, memory layer 122C, etc.) stacked on top of each other and a logic base layer 124, with the plurality of memory layers 122 stacked on the logic base layer 124. The logic base layer 124 provides space for one or more logic circuits primarily involved in performing logical operations on input signals, while the memory stack 102 provides another space for one or more memory circuits focused on storing and retrieving digital information. In an embodiment, a plurality of fourth bonding pad metals 152 are embedded in and flush with the bottom surface of the logic base layer 124. In some embodiments, the first layer 122A and the second layer 122B of the memory stack 102 are adjacent to each other and have a fifth surface and a sixth surface facing each other, respectively. The first layer 122A and the second layer 122B are joined by a direct hybrid bonding, which is formed between the fifth surface of the first layer 122A and the sixth surface of the second layer 122B of the memory stack 102. In some embodiments, the direct hybrid bonding is formed by a plurality of bonding pad metals 164 embedded in and flush with the top surface of the first layer 122A and a plurality of bonding pad metals 162 embedded in and flush with the bottom surface of the adjacent second layer 122B. The plurality of bonding pad metals 164 and the plurality of bonding pad metals 162 are aligned and in contact with each other, thereby forming a direct hybrid bonding between the top surface of the first layer 122A and the bottom surface of the second layer 122B of the memory stack 102. Thus, there is no space or gap between the top surface of the first layer 122A of the memory stack 102 and the bottom surface of the adjacent second layer 122B.

[0080] Figure 6 This is an example flowchart of a method 600 for manufacturing a semiconductor package 400 according to some embodiments of the present disclosure. It should be noted that, as Figure 6 The method 600 shown is merely an example and is not intended to limit this disclosure. Therefore, it should be understood that... Figure 6 The order of steps in method 600 shown can be changed, for example, in Figure 6 Additional steps may be provided before, during, and after Method 600, and some other steps can be described only briefly in this document.

[0081] For example, refer to Figure 4The semiconductor package 400 manufactured by method 600 may include at least an interposer 106, a first semiconductor wafer 104 disposed above the interposer 106 and having a first surface 104F (e.g., a front surface) and a second surface 104B (e.g., a back surface) facing each other, a second semiconductor wafer 102 disposed above the first semiconductor wafer 104 and having a top surface and a bottom surface facing each other, and a dielectric sidewall 103 disposed along one side of the first semiconductor wafer 104 and above the interposer 106. In some embodiments, at least one dielectric via 132 is disposed vertically through the dielectric sidewall 103 and electrically connected to a power grid (not shown) through the interposer 106. Therefore, references will be made to... Figure 4 The steps of method 600 are described using the components or devices discussed.

[0082] refer to Figure 4 and Figure 6 Method 600 begins at step 602, forming a first semiconductor wafer 104, wherein the first semiconductor wafer 104 has a first surface 104F (e.g., a front surface) and a second surface 104B (e.g., a back surface) opposite each other. For example, the first semiconductor wafer 104 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium phosphide indium, combinations thereof, and the like may also be used. Additionally, the first semiconductor wafer 104 may be an SOI substrate. Typically, an SOI substrate comprises a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof.

[0083] For example, such as Figure 4 As shown, the first semiconductor wafer 104 includes a dielectric sidewall 103 along one side of the first semiconductor wafer 104 and above the top surface of the interposer layer 106. In some embodiments, one or more dielectric vias 132 perpendicularly pass through the dielectric sidewall 103 of the first semiconductor wafer 104. In some embodiments, the first semiconductor wafer 104 is a GPU wafer. Specifically, the dielectric vias 132 can be formed by semiconductor manufacturing processes such as lithography, etching, metal filling, chemical mechanical polishing (CMP) processes, and similar or combinations thereof.

[0084] Subsequently, the first semiconductor wafer 104 is flipped so that its first surface 104F (front side) faces down and its second surface 104B (back side) faces up. In some embodiments, after flipping the first semiconductor wafer 104, one or more silicon vias 134 are formed through the silicon portion 116 of the first semiconductor wafer 104. Specifically, the silicon vias 134 can be formed by semiconductor manufacturing processes such as lithography, etching, metal filling, chemical mechanical polishing, and similar or combinations thereof.

[0085] Next, refer to Figure 4 and Figure 6 Method 600 proceeds to step 604, where a metal wiring 136 is formed on the back side 104B of the first semiconductor wafer 104. For example, the metal wiring 136 is connected to the dielectric via 132 and the silicon via 134. Specifically, the metal wiring 136 can be formed by semiconductor manufacturing processes such as lithography, etching, metal filling, chemical mechanical polishing, and similar or combinations thereof.

[0086] Next, refer to Figure 4 and Figure 6 Method 600 proceeds to step 606, whereby a first semiconductor wafer 104 is bonded to an interposer 106 disposed beneath the first semiconductor wafer 104 via a first direct hybrid bonding. The first direct hybrid bonding is formed between a first surface 104F (e.g., the front surface) of the first semiconductor wafer 104 and the top surface of the interposer 106. For example, as... Figure 4 As shown, the first direct hybrid bonding is formed by a plurality of first bonding pad metals 142 embedded in and flush with the first surface 104F of the first semiconductor wafer 104 and a plurality of second bonding pad metals 144 embedded in and flush with the top surface of the interposer 106.

[0087] Next, refer to Figure 4 and Figure 6 In step 608 of method 600, the first semiconductor wafer 104 is bonded to the second semiconductor wafer 102 disposed above the first semiconductor wafer 104 by a second direct hybrid bonding. The second direct hybrid bonding is formed between the second surface 104B (e.g., the back surface) of the first semiconductor wafer 104 and the bottom surface of the second semiconductor wafer 102. For example, the second direct hybrid bonding is formed by a plurality of third bonding pad metals 154 embedded in and flush with the second surface 104B (e.g., the back surface) of the first semiconductor wafer 104 and a plurality of fourth bonding pad metals 152 embedded in and flush with the bottom surface of the second semiconductor wafer 102.

[0088] In some embodiments of this disclosure, the second semiconductor wafer 102 includes a memory stack. In some embodiments, the memory stack 102 includes a high-bandwidth memory stack. In some embodiments, the high-bandwidth memory stack 102 includes a logic base layer 124 and a plurality of high-bandwidth memory layers 122 (such as memory layer 122A, memory layer 122B, memory layer 122C, etc.), which are stacked on top of each other and disposed above the logic base layer 124. In some embodiments, the first layer 122A and the second layer 122B of the high-bandwidth memory stack 102 are adjacent to each other and have a third surface and a fourth surface facing each other, respectively, wherein the first layer 122A and the second layer 122B are joined by a third direct hybrid bonding, which is formed between the third surface of the first layer 122A and the fourth surface of the second layer 122B of the high-bandwidth memory stack 102. In some embodiments, a third direct hybrid bond is formed by a plurality of fifth bonding pad metals 164 embedded in and flush with the third surface of the first layer 122A of the high bandwidth memory stack 102 and a plurality of sixth bonding pad metals 162 embedded in and flush with the fourth surface of the second layer 122B of the high bandwidth memory stack 102.

[0089] By utilizing these stacking configurations and bonding structures, such as dielectric vias through the sidewalls of the bottom semiconductor wafer and direct hybrid bonding structures between various adjacent surfaces in a 3D semiconductor package, the interface layers of the 3D semiconductor package are reduced, the interface thermal resistance is reduced, and an independent power distribution network is also achieved, thereby advantageously improving the system and power integration of the 3D semiconductor package.

[0090] In one embodiment of this disclosure, a semiconductor package is disclosed. The semiconductor package may include an interposer, a first semiconductor wafer disposed above the interposer and having a first surface and a second surface opposite to each other, a second semiconductor wafer disposed above the first semiconductor wafer and having a top surface and a bottom surface opposite to each other, and a dielectric sidewall disposed along one side of the first semiconductor wafer and above the interposer. At least one dielectric via is disposed perpendicularly through the dielectric sidewall and electrically connected to a power distribution network.

[0091] In some embodiments, a first semiconductor wafer and an interposer are joined together by a plurality of first hybrid bonds between a first surface of the first semiconductor wafer and a top surface of the interposer. In some embodiments, the first hybrid bonds are formed by a plurality of first bonding pad metals embedded in and flush with the first surface of the first semiconductor wafer and a plurality of second bonding pad metals embedded in and flush with the top surface of the interposer. In some embodiments, the first semiconductor wafer and a second semiconductor wafer are joined together by a plurality of second hybrid bonds between a second surface of the first semiconductor wafer and a bottom surface of the second semiconductor wafer. In some embodiments, the second hybrid bonds are formed by a plurality of third bonding pad metals embedded in and flush with the second surface of the first semiconductor wafer and a plurality of fourth bonding pad metals embedded in and flush with the bottom surface of the second semiconductor wafer. In some embodiments, the second semiconductor wafer is a high-bandwidth memory stack, wherein the high-bandwidth memory stack includes a logic base layer and a plurality of high-bandwidth memory layers stacked on top of the logic base layer. In some embodiments, the first and second layers of the high-bandwidth memory stack each have a third surface and a fourth surface facing each other, and the first and second layers are joined by a plurality of third hybrid bonds between the third surface of the first layer and the fourth surface of the second layer. In some embodiments, the third hybrid bonds are formed by a plurality of fifth bonding pad metals embedded in and flush with the third surface of the first layer of the high-bandwidth memory stack and a plurality of sixth bonding pad metals embedded in and flush with the fourth surface of the second layer of the high-bandwidth memory stack. In some embodiments, the first semiconductor wafer includes a graphics processing unit wafer. In some embodiments, the back side of the first semiconductor wafer faces the bottom surface of the second semiconductor wafer, wherein the first semiconductor wafer includes metal wiring on the back side and electrically connected to a first via structure. In some embodiments, the first semiconductor wafer includes at least one second via structure that passes through a silicon portion of the first semiconductor wafer and is electrically connected to the metal wiring.

[0092] In another embodiment of this disclosure, a semiconductor package is disclosed. The semiconductor package may include a first semiconductor wafer disposed above an interposer, the first semiconductor wafer having a first surface and a second surface opposite to each other, and including at least one dielectric sidewall disposed along one side of the first semiconductor wafer and above the interposer. At least one dielectric via is disposed perpendicularly through the dielectric sidewall and electrically connected to a power distribution network via the interposer.

[0093] In some embodiments, a first semiconductor wafer includes a metal connection on the back side of the first semiconductor wafer and electrically connected to a first via structure. In some embodiments, the first semiconductor wafer includes at least one second via structure passing through a silicon portion of the first semiconductor wafer, wherein the second via structure is electrically connected to the metal connection. In some embodiments, the first semiconductor wafer and an interposer are bonded to each other via a plurality of first hybrid bonds between a first surface of the first semiconductor wafer and a top surface of the interposer. In some embodiments, the semiconductor package further includes a second semiconductor wafer disposed above the first semiconductor wafer and having a top surface and a bottom surface opposite to each other, wherein the second semiconductor wafer is a high-bandwidth memory stack, the high-bandwidth memory stack including a logic base layer and a plurality of high-bandwidth memory layers stacked on the logic base layer. In some embodiments, the first semiconductor wafer and the second semiconductor wafer are bonded to each other via a plurality of second hybrid bonds between a second surface of the first semiconductor wafer and a bottom surface of the second semiconductor wafer.

[0094] In another embodiment of this disclosure, a method for manufacturing a semiconductor package is disclosed, the method comprising the following steps: forming a first semiconductor wafer having a first surface and a second surface opposite to each other, wherein the first semiconductor wafer includes a dielectric sidewall along one side of the first semiconductor wafer. At least one dielectric via is formed perpendicularly through the dielectric sidewall, and the first semiconductor wafer is flipped. A metal wiring is formed on the back side of the first semiconductor wafer and connected to the dielectric via. The first semiconductor wafer is bonded to an interposer layer below the first semiconductor wafer by a plurality of first hybrid bonds between the first surface of the first semiconductor wafer and the top surface of an interposer layer. The first semiconductor wafer is bonded to a second semiconductor wafer above the first semiconductor wafer by a plurality of second hybrid bonds between the second surface of the first semiconductor wafer and the bottom surface of a second semiconductor wafer.

[0095] In some embodiments, the first hybrid bond is formed by a plurality of first bonding pad metals embedded in and flush with the first surface of the first semiconductor wafer and a plurality of second bonding pad metals embedded in and flush with the top surface of the interposer. In some embodiments, the second hybrid bond is formed by a plurality of third bonding pad metals embedded in and flush with the second surface of the first semiconductor wafer and a plurality of fourth bonding pad metals embedded in and flush with the bottom surface of the second semiconductor wafer.

[0096] In another embodiment of this disclosure, a semiconductor package is disclosed. The semiconductor package may include a first semiconductor wafer having a first surface and a second surface opposite to each other, wherein the first semiconductor wafer includes a dielectric sidewall along one side of the first semiconductor wafer and at least one first via structure perpendicularly through the dielectric sidewall. The semiconductor package also includes metal wiring on the back side of the first semiconductor wafer and connected to the first via structure, a plurality of first hybrid bonds between the first surface of the first semiconductor wafer and the top surface of an interposer below the first semiconductor wafer, and a plurality of second hybrid bonds between the second surface of the first semiconductor wafer and the bottom surface of a second semiconductor wafer above the first semiconductor wafer, wherein the first semiconductor wafer is bonded to the interposer by the first hybrid bonds and to the second semiconductor wafer by the second hybrid bonds.

[0097] In some embodiments, the first hybrid bonding includes a plurality of first bonding pad metals embedded in and flush with a first surface of a first semiconductor wafer, and a plurality of second bonding pad metals embedded in and flush with a top surface of an interposer. In some embodiments, the second hybrid bonding includes a plurality of third bonding pad metals embedded in and flush with a second surface of a first semiconductor wafer, and a plurality of fourth bonding pad metals embedded in and flush with a bottom surface of a second semiconductor wafer.

[0098] As used herein, the terms “about” and “approximately” generally refer to a value plus or minus 10%. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0099] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package, characterized by, comprising: an interposer; a first semiconductor die disposed above the interposer and having a first surface and a second surface opposite each other; a second semiconductor die disposed above the first semiconductor die and having a top surface and a bottom surface opposite each other; and a dielectric sidewall disposed along a side of the first semiconductor die and above the interposer, wherein at least one first via structure vertically passes through the dielectric sidewall and is electrically connected to a power distribution network.

2. The semiconductor package of claim 1, wherein, wherein the second semiconductor die is a high bandwidth memory stack, the high bandwidth memory stack comprising: a logic base layer; and a plurality of high bandwidth memory layers located on the logic base layer and stacked on each other.

3. The semiconductor package of claim 2, wherein, wherein a first layer and a second layer of the high bandwidth memory stack have a third surface and a fourth surface facing each other, respectively, the first layer and the second layer are bonded by a plurality of third hybrid bonds between the third surface of the first layer and the fourth surface of the second layer of the high bandwidth memory stack.

4. The semiconductor package of claim 3, wherein, wherein the plurality of third hybrid bonds are formed by a plurality of fifth bond pads embedded into the third surface of the first layer of the high bandwidth memory stack and flush with the third surface of the first layer and a plurality of sixth bond pads embedded into the fourth surface of the second layer of the high bandwidth memory stack and flush with the fourth surface of the second layer.

5. A semiconductor package, characterized by, comprising: a first semiconductor die disposed above an interposer and having a first surface and a second surface opposite each other; and at least one dielectric sidewall disposed along a side of the first semiconductor die and above the interposer, wherein at least one first via structure vertically passes through the at least one dielectric sidewall and is electrically connected to a power distribution network via the interposer.

6. The semiconductor package of claim 5, wherein, wherein the first semiconductor die includes a metal wire on a backside of the first semiconductor die and electrically connected to the first via structure.

7. The semiconductor package of claim 6, wherein the semiconductor package is a flip chip semiconductor package. wherein the first semiconductor die includes at least one second via structure through a silicon portion of the first semiconductor die, and wherein the at least one second via structure is electrically connected to the metal wire.

8. A semiconductor package, characterized by, comprising: a first semiconductor die having a first surface and a second surface opposite each other, wherein the first semiconductor die includes a dielectric sidewall along a side of the first semiconductor die and at least one first via structure vertically passing through the dielectric sidewall; a metal wire on a backside of the first semiconductor die and connected to the at least one first via structure; a plurality of first hybrid bonds between the first surface of the first semiconductor die and a top surface of an interposer below the first semiconductor die, wherein the first semiconductor die is bonded to the interposer by the plurality of first hybrid bonds; and a plurality of second hybrid bonds between the second surface of the first semiconductor die and a bottom surface of a second semiconductor die above the first semiconductor die, wherein the first semiconductor die is bonded to the second semiconductor die by the plurality of second hybrid bonds.

9. The semiconductor package of claim 8, wherein the semiconductor package is a flip chip semiconductor package. wherein the plurality of first hybrid bonds comprise: a plurality of first bond pad metals embedded into and flush with the first surface of the first semiconductor wafer; and a plurality of second bond pad metals embedded into and flush with the top surface of the interposer.

10. The semiconductor package of claim 8, wherein the semiconductor package is a flip chip semiconductor package. wherein the plurality of second hybrid bonds comprise: a plurality of third bond pad metals embedded into and flush with the second surface of the first semiconductor wafer; and a plurality of fourth bond pad metals embedded into and flush with the bottom surface of the second semiconductor wafer. a plurality of second bond pad metals embedded into and flush with the top surface of the interposer. wherein the plurality of second hybrid bonds comprise: a plurality of third bond pad metals embedded into and flush with the second surface of the first semiconductor wafer; and a plurality of fourth bond pad metals embedded into and flush with the bottom surface of the second semiconductor wafer.

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