Synchronous motor star sealing control device for elevator and elevator

Abstract

The utility model provides a synchronous motor star sealing control device for an elevator and the elevator, and relates to the technical field of electronic circuits. The device comprises a motor control digital processor and a star sealing circuit, wherein the motor control digital processor is used for forwarding an elevator running state signal to the star sealing circuit; the star sealing circuit is used for providing a first motor driving signal for the inverter circuit according to a preset pulse signal under the condition that the elevator running state signal indicates that the running state of the elevator is a stopping state or a braking state; wherein the inverter circuit is configured to turn off the first transistor and turn on the second transistor in response to a first motor driving signal, so that the input end of a winding of the motor connected with the inverter circuit is in short circuit, the motor generates braking torque, and the first transistor is an upper bridge arm of the inverter circuit; the second transistor is a lower bridge arm of the inverter circuit. The utility model has the advantages of small volume and fast response.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, specifically to a synchronous motor sealing star control device for elevators and an elevator. Background Technology

[0002] As elevators have become an indispensable tool in modern life, the industry has always maintained high requirements for their safety and reliability. Currently, the star-sealed technology and safety torque shutdown technology of elevator motors are both implemented through contactors. This method is characterized by its large size and slow response speed. Moreover, the complex wiring of contactors results in excessively high maintenance costs. Utility Model Content

[0003] In view of this, the present invention provides a synchronous motor sealing star control device for elevators and an elevator.

[0004] One aspect of this utility model provides a synchronous motor sealing star control device for elevators. The device includes a motor control digital processor and a sealing star circuit. The motor control digital processor forwards an elevator operating status signal to the sealing star circuit. The sealing star circuit provides a first motor drive signal to an inverter circuit based on a preset pulse signal when the elevator operating status signal indicates that the elevator is in a stopped or braking state. The inverter circuit is configured to turn off a first transistor and turn on a second transistor in response to the first motor drive signal, short-circuiting the input terminals of the windings of the motor connected to the inverter circuit to generate braking torque. The first transistor is the upper arm of the inverter circuit, and the second transistor is the lower arm of the inverter circuit.

[0005] According to an embodiment of this utility model, the aforementioned star-sealing circuit includes a safety torque control circuit, a star-sealing logic circuit, and a motor drive circuit; the safety torque control circuit includes a control signal input terminal and a control signal output terminal; the star-sealing logic circuit includes a star-sealing enable signal input terminal, a star-sealing signal input terminal, and a star-sealing signal output terminal; the motor drive circuit includes a logic signal input terminal and a drive signal output terminal; the control signal input terminal is connected to the first signal output terminal of the motor control digital processor; the control signal output terminal is connected to the star-sealing signal input terminal; the star-sealing enable signal input terminal is connected to the second signal output terminal of the motor control digital processor. The output terminal is connected to the above-mentioned star-sealing signal; the output terminal is connected to the above-mentioned logic signal input terminal; the output terminal is connected to the gate of the transistor included in the above-mentioned inverter circuit; the safety torque control circuit is used to output a set pulse signal when the above-mentioned elevator running status signal indicates that the elevator's running status is the above-mentioned stop state or the above-mentioned braking state; the above-mentioned star-sealing logic circuit is used to adjust the above-mentioned set pulse signal to the above-mentioned preset pulse signal when the above-mentioned elevator running status signal indicates that the elevator's running status is the above-mentioned stop state or the above-mentioned braking state; the above-mentioned motor drive circuit is used to output a first motor drive signal according to the above-mentioned preset pulse signal.

[0006] According to an embodiment of this utility model, the aforementioned star-sealing logic circuit includes an enable control circuit, a multi-channel first logic AND circuit, and a multi-channel logic control circuit; the enable control circuit includes an enable input terminal, a first enable output terminal, and a second enable output terminal; the enable input terminal serves as the star-sealing enable signal input terminal; each of the aforementioned first logic AND circuits includes a first AND gate input terminal, a second AND gate input terminal, and an AND gate output terminal; each of the aforementioned logic control circuits includes a first logic input terminal, a second logic input terminal, a third logic input terminal, and a logic output terminal; the star-sealing signal input terminal includes the first AND gate input terminal and the first logic input terminal of the aforementioned first logic AND circuit; the star-sealing signal output terminal includes the AND gate output terminal and the logic output terminal of the aforementioned first logic AND circuit; the first enable output terminal is connected to the second logic input terminal and the second AND gate input terminal of the aforementioned first logic AND circuit respectively; the second enable output terminal is connected to the third logic input terminal; the logic output terminal is connected to the second transistor included in the aforementioned inverter circuit; the AND gate output terminal of the aforementioned first logic AND circuit is connected to the first transistor.

[0007] According to an embodiment of the present invention, each of the above-mentioned logic control circuits includes a second AND circuit and a logic OR circuit; the second AND circuit includes a first AND gate input, a second AND gate input, and an AND gate output; the logic OR circuit includes a first OR gate input, a second OR gate input, and an OR gate output; the first AND gate input of the second AND circuit serves as the first logic input; the second AND gate input of the second AND circuit serves as the second logic input; the second OR gate input serves as the third logic input; the OR gate output serves as the logic output; and the AND gate output of the second AND circuit is connected to the first OR gate input.

[0008] According to an embodiment of this utility model, the enable control circuit includes a delay resistor, a delay capacitor, a third AND circuit, a fourth AND circuit, and multiple NOT circuits; the third AND circuit includes a first AND gate input, a second AND gate input, and an AND gate output; the fourth AND circuit includes a first AND gate input, a second AND gate input, and an AND gate output; each of the NOT circuits includes a NOT gate input and a NOT gate output; the multiple NOT circuits include a first NOT circuit, a second NOT circuit, and a third NOT circuit; the AND gate output of the third AND circuit serves as a first enable output; the AND gate output of the fourth AND circuit serves as a second enable output; the NOT gate of the first NOT circuit... The gate input terminal serves as the aforementioned enable input terminal; the NOT gate input terminal of the aforementioned first logic NOT circuit is connected to the first AND gate input terminal of the aforementioned fourth logic AND circuit; the NOT gate output terminal of the aforementioned first logic NOT circuit is connected to the first AND gate input terminal of the aforementioned third logic AND circuit and one end of the aforementioned delay resistor; the other end of the aforementioned delay resistor is connected to one end of the aforementioned delay capacitor and the NOT gate input terminal of the aforementioned second logic NOT circuit; the NOT gate output terminal of the aforementioned second logic NOT circuit is connected to the second AND gate input terminal of the aforementioned fourth logic AND circuit and the NOT gate input terminal of the aforementioned third logic NOT circuit; the NOT gate output terminal of the aforementioned third logic NOT circuit is connected to the second AND gate input terminal of the aforementioned third logic AND circuit; the other end of the aforementioned delay capacitor is grounded.

[0009] According to an embodiment of the present invention, the aforementioned safe torque control circuit includes a multi-channel logic adjustment circuit and a fault logic circuit; the aforementioned fault logic circuit includes a fault signal input terminal and a fault signal output terminal; each of the aforementioned logic adjustment circuits includes a pulse signal input terminal, a fault signal input terminal, and a pulse signal output terminal; the aforementioned control signal input terminal includes the aforementioned pulse signal input terminal and a fault signal input terminal; the aforementioned control signal output terminal includes the aforementioned pulse signal output terminal and the aforementioned enable signal output terminal; the aforementioned fault signal output terminal is connected to the aforementioned fault signal input terminal.

[0010] According to an embodiment of the present invention, each of the above-mentioned logic adjustment circuits includes a resistor and a plurality of MOSFETs; one end of the resistor serves as the pulse signal input terminal; the other end of the resistor is connected to the source of each of the above-mentioned MOSFETs; the drain of each of the above-mentioned MOSFETs is connected to ground; the pulse signal output terminal includes the source of each of the above-mentioned MOSFETs; and the fault logic circuit is connected to the gate of each of the above-mentioned MOSFETs.

[0011] According to an embodiment of the present invention, the fault logic circuit includes a multi-channel switching circuit; each of the switching circuits includes a switching resistor and an optocoupler; the optocoupler includes a first terminal, a second terminal, a third terminal, and a fourth terminal; the fault signal input terminal includes a first signal input terminal and a second signal input terminal; the first signal input terminal is connected to one end of the switching resistor; the other end of the switching resistor is connected to the first terminal of the optocoupler; the second signal input terminal is connected to the second terminal of the optocoupler; the third terminal is connected to ground; and the control signal output terminal includes the fourth terminal.

[0012] According to an embodiment of the present invention, the motor control digital processor is further configured to output a preset drive pulse signal to the star-sealing circuit; the star-sealing circuit is configured to provide a second motor drive signal to the inverter circuit according to the preset drive pulse signal when the elevator operating status signal indicates that the elevator is in normal operating condition; wherein, the inverter circuit is configured to turn on the first transistor or the second transistor in response to the second motor drive signal, or turn off the first transistor or the second transistor, so that the inverter circuit outputs a preset AC power to the motor, thereby causing the motor to drive the elevator car.

[0013] Another aspect of this utility model provides an elevator, including: the aforementioned synchronous motor star control device for elevators.

[0014] According to an embodiment of this utility model, a first motor drive signal is provided to the inverter circuit via a star-sealing circuit, causing the first transistor in the inverter circuit to turn off and the second transistor to turn on, thereby short-circuiting the input terminal of the motor winding connected to the inverter circuit and cutting off the AC power input to the motor winding. Compared with existing technologies that use contactors to achieve star-sealing technology and safety torque shutdown technology for elevator motors, the star-sealing circuit is smaller in size and has a faster signal transmission speed. Attached Figure Description

[0015] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0016] Figure 1The schematic diagram illustrates the structure of a synchronous motor sealing star control device for an elevator according to an embodiment of the present invention.

[0017] Figure 2 The schematic diagram illustrates the structure of the sealing circuit according to an embodiment of the present invention;

[0018] Figure 3 The schematic diagram illustrates the structure of the first logic circuit of an embodiment of the present invention;

[0019] Figure 4 The schematic diagram illustrates the structure of the logic control circuit of an embodiment of the present invention;

[0020] Figure 5 The schematic diagram illustrates the structure of the enable control circuit of an embodiment of the present invention;

[0021] Figure 6 The schematic diagram illustrates the structure of the star-sealing logic circuit of an embodiment of the present invention;

[0022] Figure 7 The schematic diagram illustrates the structure of the logic adjustment circuit of an embodiment of the present invention;

[0023] Figure 8 The schematic diagram illustrates the structure of the fault logic circuit of an embodiment of the present invention;

[0024] Figure 9 The schematic diagram illustrates the structure of a safety torque control circuit according to an embodiment of the present invention;

[0025] Figure 10 This schematic diagram illustrates the structure of a synchronous motor sealing star control device for an elevator according to another embodiment of the present invention.

[0026] Figure 11 The schematic diagram illustrates the structure of the inverter circuit according to an embodiment of the present invention;

[0027] Figure 12 The schematic diagram illustrates the structure of a synchronous motor sealing star control device for an elevator according to another embodiment of the present invention.

[0028] Figure 13 This schematic diagram illustrates the waveform of the sealing signal when the elevator stops normally according to an embodiment of the present invention; and

[0029] Figure 14 The schematic diagram illustrates the waveform of the sealing star signal during emergency braking of an elevator according to an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0032] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0033] When using expressions such as "at least one of A, B, and C," the meaning should generally be interpreted according to the understanding of someone skilled in the art. For example, "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C. Similarly, when using expressions such as "at least one of A, B, or C," the meaning should generally be interpreted according to the understanding of someone skilled in the art. For example, "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C.

[0034] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference in the accompanying drawings and are not intended to limit the scope of protection of this utility model. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this utility model.

[0035] Safe Torque Off (STO) technology refers to preventing the application of power sources capable of causing rotation to the motor. STO technology is applied to elevators with AC or DC motors powered and controlled by static components. It achieves safe motor control by cutting off the power supply to the motor. Electronic star-off refers to using the existing power module of the frequency converter to limit the unexpected speed of the car by short-circuiting the three-phase windings of the motor in a safe torque off state.

[0036] Currently, both the star-sealing technology and the safety torque shutdown technology of elevator motors are implemented using contactors. This method is characterized by its large size and slow response speed.

[0037] Figure 1 The schematic diagram illustrates the structure of a synchronous motor sealing star control device for an elevator according to an embodiment of the present invention.

[0038] like Figure 1 As shown, the synchronous motor sealing star control device for elevators provided in the embodiments of this utility model includes: a motor control digital processor and a sealing star circuit; wherein, the motor control digital processor is used to forward elevator operating status signals to the sealing star circuit; the sealing star circuit is used to provide a first motor drive signal to the inverter circuit according to a preset pulse signal when the elevator operating status signal indicates that the elevator is in a stopped state or a braking state; wherein, the inverter circuit is configured to turn off a first transistor and turn on a second transistor in response to the first motor drive signal, so that the input terminal of the winding of the motor connected to the inverter circuit is short-circuited, so that the motor generates braking torque, wherein the first transistor is the upper bridge arm of the inverter circuit; the second transistor is the lower bridge arm of the inverter circuit.

[0039] According to an embodiment of this utility model, the elevator control system includes an elevator control cabinet and a frequency converter connected to the control cabinet. The frequency converter includes a motor control digital processor and an inverter circuit. The motor control digital processor receives elevator operating status signals from the elevator control cabinet and then sends these signals to a star-sealing circuit. When the elevator is in a stopped or braking state, the star-sealing circuit outputs a first motor drive signal determined according to a preset pulse signal.

[0040] According to an embodiment of this utility model, the first transistor may include multiple upper bridge arm transistors; the second transistor may include multiple lower bridge arm transistors; one end of each upper bridge arm transistor is connected to the positive terminal of the DC power supply of the inverter circuit, and the other end is connected to one end of the corresponding lower bridge arm transistor; the other end of the corresponding lower bridge arm transistor is connected to the negative terminal of the DC power supply of the inverter circuit. Each upper bridge arm transistor and its corresponding lower bridge arm transistor constitute one bridge arm of the inverter circuit.

[0041] According to an embodiment of this utility model, a first motor drive signal is provided to the inverter circuit via a star-sealing circuit, causing the first transistor in the inverter circuit to turn off and the second transistor to turn on, thereby short-circuiting the input terminal of the motor winding connected to the inverter circuit and cutting off the AC power input to the motor winding. Compared with existing technologies that use contactors to achieve star-sealing technology and safety torque shutdown technology for elevator motors, the star-sealing circuit is smaller in size and has a faster signal transmission speed.

[0042] Figure 2The schematic diagram illustrates the structure of the sealing circuit of an embodiment of the present invention.

[0043] like Figure 2 As shown, the star-sealing circuit includes a safety torque control circuit, a star-sealing logic circuit, and a motor drive circuit. The safety torque control circuit includes a control signal input terminal and a control signal output terminal. The star-sealing logic circuit includes a star-sealing enable signal input terminal, a star-sealing signal input terminal, and a star-sealing signal output terminal. The motor drive circuit includes a logic signal input terminal and a drive signal output terminal. The control signal input terminal is connected to the first signal output terminal of the motor control digital processor. The control signal output terminal is connected to the star-sealing signal input terminal. The star-sealing enable signal input terminal is connected to the second signal output terminal of the motor control digital processor. The star-sealing signal output terminal is connected to the logic signal input terminal. The drive signal output terminal is connected to the gate of the transistor included in the inverter circuit. The safety torque control circuit is used to output a set pulse signal when the elevator running status signal indicates that the elevator's running status is a stopped state or a braking state. The star-sealing logic circuit is used to adjust the set pulse signal to a preset pulse signal when the elevator running status signal indicates that the elevator's running status is a stopped state or a braking state. The motor drive circuit is used to output a first motor drive signal according to the preset pulse signal.

[0044] According to an embodiment of this utility model, the motor control digital processor includes a first signal output terminal and a second signal output terminal. When the elevator running status signal indicates that the elevator is in a stopped or braking state, the safety torque control circuit outputs a setting pulse signal, for example, the setting pulse signal can be a low-level signal. This setting pulse signal can satisfy the condition that after the setting pulse signal is input to the motor drive circuit, the motor drive signal output by the motor drive circuit can make all the transistors in the inverter circuit turn off.

[0045] According to an embodiment of this utility model, when the elevator running status signal indicates that the elevator is in a stopped or braking state, regardless of the waveform of the set pulse signal input to the star-sealing logic circuit, the star-sealing logic circuit will adjust the set pulse signal to a preset pulse signal. The preset pulse signal satisfies the condition that after the preset pulse signal is input to the motor drive circuit, the motor drive signal output by the motor drive circuit can make the transistors of the upper bridge arm in the inverter circuit all turn off and the transistors of the lower bridge arm all turn on.

[0046] According to an embodiment of the present invention, the motor drive circuit can be a power amplifier circuit; since the preset pulse signal output by the star-sealed logic circuit is a digital signal with weak driving capability, it is necessary to amplify the preset pulse signal to improve its driving capability, and use the amplified preset pulse signal as the first motor drive signal.

[0047] According to embodiments of this invention, the star-sealing circuit improves the effectiveness of star-sealing control. The star-sealing logic circuit, replacing the hardware star-sealing method with a contactor, offers advantages such as smaller size, faster response, and greater reliability. When the elevator stops or undergoes emergency braking, both the safe torque loss (STO) function and the electronic star-sealing function must operate simultaneously. By directly removing the star-sealing contactor used in existing technologies and using the inverter's built-in IGBTs for star-sealing, there is no significant increase in cost, resulting in cost savings.

[0048] According to an embodiment of this utility model, the star-sealing logic circuit includes an enable control circuit, a multi-channel first logic AND circuit, and a multi-channel logic control circuit. The enable control circuit includes an enable input terminal, a first enable output terminal, and a second enable output terminal. The enable input terminal serves as the star-sealing enable signal input terminal. Each first logic AND circuit includes a first AND gate input terminal, a second AND gate input terminal, and an AND gate output terminal. Each logic control circuit includes a first logic input terminal, a second logic input terminal, a third logic input terminal, and a logic output terminal. The star-sealing signal input terminal includes the first AND gate input terminal and the first logic input terminal of the first logic AND circuit. The star-sealing signal output terminal includes the AND gate output terminal and the logic output terminal of the first logic AND circuit. The first enable output terminal is connected to the second logic input terminal and the second AND gate input terminal of the first logic AND circuit, respectively. The second enable output terminal is connected to the third logic input terminal. The logic output terminal is connected to the second transistor. The AND gate output terminal of the first logic AND circuit is connected to the first transistor.

[0049] According to an embodiment of this utility model, the enable input terminal is used to receive a motor operating status signal. The first AND gate input terminal of the first logic AND circuit is used to receive a preset pulse signal. The AND gate output terminal of the first logic AND circuit is used to output a preset pulse signal corresponding to the motor drive signal that turns off the first transistor; the logic output terminal is used to output a preset pulse signal corresponding to the motor drive signal that turns on the second transistor.

[0050] Figure 3 The schematic diagram illustrates the structure of the first logic and circuit of an embodiment of the present invention.

[0051] like Figure 3 As shown, the first logic AND circuit may include an AND gate circuit. The second AND gate input of the AND gate circuit is used to input the output of the enable control circuit. The signal output by the enable control circuit is multiplied by the signal input by the first AND gate input of the AND gate circuit. The AND gate output outputs a preset pulse signal corresponding to the motor drive signal that turns on the first transistor.

[0052] Figure 4 The schematic diagram illustrates the structure of the logic control circuit of an embodiment of the present invention.

[0053] like Figure 4 As shown, each logic control circuit includes a second AND circuit and a logic OR circuit; the second AND circuit includes a first AND gate input, a second AND gate input, and an AND gate output; the logic OR circuit includes a first OR gate input, a second OR gate input, and an OR gate output; the first AND gate input of the second AND circuit serves as the first logic input; the second AND gate input of the second AND circuit serves as the second logic input; the second OR gate input serves as the third logic input; the OR gate output serves as the logic output; the AND gate output of the second AND circuit is connected to the first OR gate input.

[0054] According to an embodiment of this utility model, the second logic AND circuit can select an AND gate circuit, which performs a multiplication operation on two input digital signals. The logic OR circuit can select an OR gate circuit, which performs an addition operation on two input digital signals. The first AND gate input terminal of the second logic AND circuit is used to input a setting pulse signal, and the second AND gate input terminal is used to input the output of an enable control circuit. The signal output by the enable control circuit is multiplied by the signal input by the first AND gate input terminal, and the AND gate output terminal outputs a preset pulse signal corresponding to the motor drive signal that turns off the second transistor. This preset pulse signal is then input to the first OR gate input terminal. The second OR gate input terminal is used to input the output signal of the enable control circuit. The signal output by the enable control circuit is added by the signal output by the AND gate output terminal, and the OR gate output terminal outputs a preset pulse signal corresponding to the motor drive signal that turns on the second transistor.

[0055] Figure 5 The schematic diagram illustrates the structure of the enable control circuit of an embodiment of the present invention.

[0056] like Figure 5As shown, the enable control circuit includes a delay resistor 504, a delay capacitor 507, a third AND circuit 501, a fourth AND circuit 502, and multiple NOT circuits. The third AND circuit 501 includes a first AND gate input, a second AND gate input, and an AND gate output. The fourth AND circuit 502 includes a first AND gate input, a second AND gate input, and an AND gate output. Each NOT circuit includes a NOT gate input and a NOT gate output. The multiple NOT circuits include a first NOT circuit 503, a second NOT circuit 505, and a third NOT circuit 506. The AND gate output of the third AND circuit 501 serves as the first enable output. The AND gate output of the fourth AND circuit 502 serves as the second enable output. The NOT gate of the first NOT circuit 503... The gate input is used as an enable input; the NOT gate input of the first logic NOT circuit 503 is connected to the first AND gate input of the fourth logic AND circuit 502; the NOT gate output of the first logic NOT circuit 503 is connected to the first AND gate input of the third logic AND circuit 501 and one end of the delay resistor 504; the other end of the delay resistor 504 is connected to one end of the delay capacitor 507 and the NOT gate input of the second logic NOT circuit 505; the NOT gate output of the second logic NOT circuit 505 is connected to the second AND gate input of the fourth logic AND circuit 502 and the NOT gate input of the third logic NOT circuit 506; the NOT gate output of the third logic NOT circuit 506 is connected to the second AND gate input of the third logic AND circuit 501; the other end of the delay capacitor 507 is grounded.

[0057] According to embodiments of this utility model, both the third AND circuit 501 and the fourth AND circuit 502 can be selected as AND gate circuits, which perform a multiplication operation on the two input digital signals. The NOT circuit can be selected as a NOT gate circuit, which inverts the input signal. The connection relationship between the delay resistor 504 and the delay capacitor 507 determines the dead time of the preset pulse signal.

[0058] Figure 6 The schematic diagram illustrates the structure of the star-sealing logic circuit of an embodiment of the present invention.

[0059] like Figure 6 As shown, the star-sealing logic circuit includes: a delay resistor 504, a delay capacitor 507, multiple AND gate modules, multiple OR gate modules, and multiple NOT gate modules; each AND gate module includes a first input terminal, a second input terminal, and an output terminal; each OR gate includes a first input terminal, a second input terminal, and an output terminal; each NOT gate module includes an input terminal and an output terminal.

[0060] The multiple AND gate modules include a first logic AND gate circuit 601, a second logic AND gate circuit 602, a third logic AND gate circuit 603, a fourth logic AND gate circuit 604, a fifth logic AND gate circuit 605, a sixth logic AND gate circuit 606, a third logic AND circuit 501, and a fourth logic AND circuit 502; the multiple OR gate modules include a first logic OR circuit 607, a second logic OR circuit 608, and a third logic OR circuit 609; the multiple NOT gate modules include a first logic NOT circuit 503, a second logic NOT circuit 505, and a third logic NOT circuit 506.

[0061] The star-sealing logic circuit includes a signal input terminal, a signal output terminal, and an enable signal input terminal; the first input terminal of the first logic AND gate 601, the first input terminal of the second logic AND gate 602, the first input terminal of the third logic AND gate 603, the first input terminal of the fourth logic AND gate 604, the first input terminal of the fifth logic AND gate 605, and the first input terminal of the sixth logic AND gate 606 serve as the signal input terminals of the star-sealing logic circuit.

[0062] The second input terminals of the first AND gate 601, the second input terminal of the second AND gate 602, the second input terminal of the third AND gate 603, the second input terminal of the fourth AND gate 604, the second input terminal of the fifth AND gate 605, the second input terminal of the sixth AND gate 606, and the output terminal of the third AND gate 501 are connected to each other.

[0063] The first input terminal of the first logic OR circuit 607 is connected to the output terminal of the second logic AND gate circuit 602; the first input terminal of the second logic OR circuit 608 is connected to the output terminal of the fourth logic AND gate circuit 604; the first input terminal of the third logic OR circuit 609 is connected to the output terminal of the sixth logic AND gate circuit 606. The second input terminals of the first logic OR circuit 607, the second logic OR circuit 608, the third logic OR circuit 609, and the output terminal of the fourth logic AND circuit 602 are connected to each other.

[0064] The enable signal input terminal of the star-sealing logic circuit is connected to the first input terminal of the fourth logic AND circuit 502, and also to the input terminal of the first logic NOT circuit 503; the output terminal of the first logic NOT circuit 503 is connected to the first input terminal of the third logic AND circuit 501, and also to one end of the delay resistor 504; the other end of the delay resistor 504 is connected to one end of the delay capacitor 507, and also to the input terminal of the second logic NOT circuit 505; the other end of the delay capacitor 507 is connected to ground; the output terminal of the second logic NOT circuit 505 is connected to the second input terminal of the fourth logic AND circuit 502, and also to the input terminal of the third logic NOT circuit 506; the output terminal of the third logic NOT circuit 506 is connected to the second input terminal of the third logic AND circuit 501.

[0065] The output terminals of the first AND gate 601, the first OR gate 607, the third AND gate 603, the second OR gate 608, the fifth AND gate 605, and the third OR gate 609 serve as the signal output terminals of the star-sealed logic circuit.

[0066] According to an embodiment of the present invention, the safety torque control circuit includes a multi-channel logic adjustment circuit and a fault logic circuit; the fault logic circuit includes a fault signal input terminal and a fault signal output terminal; each logic adjustment circuit includes a pulse signal input terminal, a fault signal input terminal and a pulse signal output terminal; the control signal input terminal includes a pulse signal input terminal and a fault signal input terminal; the control signal output terminal includes a pulse signal output terminal and an enable signal output terminal; the fault signal output terminal is connected to the fault signal input terminal.

[0067] According to an embodiment of the present invention, the star-sealing logic circuit can output a preset pulse signal through the star-sealing enable signal, and the motor drive circuit outputs a first motor drive signal and a second motor drive signal according to the preset pulse signal. Thus, the star-sealing logic circuit can indirectly control the drive pulse of the first transistor of the upper bridge arm and the drive pulse of the second transistor of the lower bridge arm of the inverter circuit through the star-sealing enable signal.

[0068] According to an embodiment of the present invention, Figure 6 In the diagram, BOTxPWM(IN) represents the digital signal input to the control second transistor of the star-shaped logic circuit, TOPxPWM(IN) represents the digital signal input to the control first transistor of the star-shaped logic circuit, BOTxPWM(OUT) represents the digital signal output from the star-shaped logic circuit to control the second transistor, and TOPxPWM(OUT) represents the digital signal output from the star-shaped logic circuit to control the first transistor. The value of x is 1, 2, or 3, where x represents the bridge arm. OUT1 represents the output of the first logic NOT circuit, OUT2 represents the output of the second logic NOT circuit, and OUT3 represents the output of the third logic NOT circuit.

[0069] Figure 7 The schematic diagram illustrates the structure of the logic adjustment circuit of an embodiment of the present invention.

[0070] like Figure 7 As shown, each logic adjustment circuit includes a resistor 701 and multiple MOSFETs 702; one end of the resistor serves as the pulse signal input terminal; the other end of the resistor is connected to the source of each MOSFET 702; the drain of each MOSFET 702 is connected to ground; the pulse signal output terminal includes the source of each MOSFET 702; and the fault logic circuit is connected to the gate of each MOSFET 702.

[0071] According to an embodiment of this invention, MOSFET 702 can be selected as an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Resistor 701 acts as a matching resistor in this logic adjustment circuit. The fault logic circuit is used to output a high-level or low-level signal to the gate of MOSFET 702. When the fault logic circuit outputs a high-level signal to the gate of MOSFET 702, MOSFET 702 is turned on, making the signal level at the source of MOSFET 702 low, that is, the pulse signal output terminal outputs a low level. When the fault logic circuit outputs a low-level signal to the gate of MOSFET 702, MOSFET 702 is turned off, making the signal level at the source of MOSFET 702 unchanged from the signal level input at the pulse signal input terminal, that is, the signal level output at the pulse signal output terminal is consistent with the signal level input at the pulse signal input terminal.

[0072] Figure 8 The schematic diagram illustrates the structure of a fault logic circuit according to an embodiment of the present invention.

[0073] like Figure 8 As shown, the fault logic circuit includes a multi-channel switching circuit; each switching circuit includes a switching resistor 801 and an optocoupler 802; the optocoupler 802 includes a first terminal, a second terminal, a third terminal, and a fourth terminal; the fault signal input terminal includes a first signal input terminal and a second signal input terminal; the first signal input terminal is connected to one end of the switching resistor 801; the other end of the switching resistor 801 is connected to the first terminal of the optocoupler 802; the second signal input terminal is connected to the second terminal of the optocoupler 802; the third terminal is connected to ground; the control signal output terminal includes the fourth terminal.

[0074] According to an embodiment of the present invention, when the voltage difference between the signals input at the first signal input terminal and the second signal input terminal causes the light-emitting diode in the optocoupler 802 to conduct, the light receiver in the optocoupler 802 conducts, causing the fourth terminal to output a low-level signal; when the voltage difference between the signals input at the first signal input terminal and the second signal input terminal causes the light-emitting diode in the optocoupler 802 to fail to conduct, the fourth terminal outputs a high-level signal.

[0075] Figure 9 The schematic diagram illustrates the structure of a safety torque control circuit according to an embodiment of the present invention.

[0076] like Figure 9As shown, the safety torque control circuit includes a first resistor 901, a second resistor 902, a third resistor 903, a fourth resistor 904, a fifth resistor 905, a sixth resistor 906, and a multi-channel logic adjustment circuit. The safety torque control circuit includes a signal input terminal, a signal output terminal, and a brake enable signal input terminal. One end of the first resistor 901, one end of the second resistor 902, one end of the third resistor 903, one end of the fourth resistor 904, one end of the fifth resistor 905, and one end of the sixth resistor 906 serve as the signal input terminal of the safety torque control circuit. Each logic adjustment circuit includes a level adjustment circuit and a switching circuit. The level adjustment circuit includes a first MOSFET 907, a second MOSFET 908, a third MOSFET 909, a fourth MOSFET 910, a fifth MOSFET 911, and a sixth MOSFET 912.

[0077] The switching circuit includes a signal input terminal and a signal output terminal; the signal input terminal of the switching circuit serves as the brake enable signal input terminal of the safety torque control circuit; the signal output terminal of the switching circuit, the gate of the first MOSFET 907, the gate of the second MOSFET 908, the gate of the third MOSFET 909, the gate of the fourth MOSFET 910, the gate of the fifth MOSFET 911, and the gate of the sixth MOSFET 912 are connected to each other; the switching circuit is used to turn the first MOSFET 907, the second MOSFET 908, the third MOSFET 909, the fourth MOSFET 910, the fifth MOSFET 911, and the sixth MOSFET 912 on and off according to a preset rule.

[0078] The drains of the first MOSFET 907, the second MOSFET 908, the third MOSFET 909, the fourth MOSFET 910, the fifth MOSFET 911, and the sixth MOSFET 912 are all connected to ground. The source of the first MOSFET 907 is connected to the other end of the first resistor 901. The source of the second MOSFET 908 is connected to the other end of the second resistor 902. The source of the third MOSFET 909 is connected to the other end of the third resistor 903. The source of the fourth MOSFET 910 is connected to the other end of the fourth resistor 904. The source of the fifth MOSFET 911 is connected to the other end of the fifth resistor 905. The source of the sixth MOSFET 912 is connected to the other end of the sixth resistor 906.

[0079] The sources of the first MOSFET 907, the second MOSFET 908, the third MOSFET 909, the fourth MOSFET 910, the fifth MOSFET 911, and the sixth MOSFET 912 serve as the signal output terminals of the safety torque control circuit; the signal output terminals of the safety torque control circuit are connected to the signal input terminals of the star-sealed logic circuit.

[0080] Figure 9In the diagram, BOTxPWM represents the digital signal input to the control second transistor of the safety torque control circuit, and TOPxPWM represents the digital signal input to the control first transistor of the safety torque control circuit. The value of x is 1, 2, or 3, where x represents the bridge arm. L-SK and O-SK are elevator operating status signals input to the safety torque control circuit; different values ​​of L-SK and O-SK represent different elevator operating states.

[0081] According to an embodiment of this utility model, STO (Safe Torque Tolerance) technology is implemented using a safe torque control circuit. A dual-channel circuit architecture consisting of two switching circuits and two level adjustment circuits is adopted. One switching circuit and one level adjustment circuit are connected; the other switching circuit and the other level adjustment circuit are connected. The safety integrity level of the safe torque control circuit reaches SIL3, with a hardware fault margin of 1. Combined with real-time comparison of the dual-channel states, the control of the motor is ensured to be safe and reliable. STO, replacing contactor control of the motor, has advantages such as low operating noise, small size, and fast response speed.

[0082] Figure 10 The schematic diagram illustrates the structure of a synchronous motor sealing star control device for an elevator according to another embodiment of the present invention.

[0083] like Figure 10 As shown, taking a motor with three-phase windings as an example, the motor control digital processor generates three upper arm drive pulses and three lower arm drive pulses for the inverter circuit. The safety torque control circuit blocks all six drive pulses when the elevator malfunctions, cutting off the motor's power supply to prevent the power that would cause rotation from being applied to the motor. The star-blocking logic circuit controls the upper and lower arm drive pulses to generate upper and lower arm on / off drive pulses based on the star-blocking enable signal generated by the motor control digital processor. The motor drive circuit implements motor drive and star-blocking based on the upper and lower arm drive pulses. The star-blocking circuit also includes a matching resistor; the safety torque control circuit is connected to the star-blocking logic circuit through the matching resistor.

[0084] Figure 11 The schematic diagram illustrates the structure of the inverter circuit according to an embodiment of the present invention.

[0085] like Figure 11As shown, the inverter circuit of the frequency converter includes a first transistor 1101, a second transistor 1102, a first transistor 1103, a second transistor 1104, a first transistor 1105, a second transistor 1106, a first diode 1107, a second diode 1108, a third diode 1109, a fourth diode 1110, a fifth diode 1111, and a sixth diode 1112. Specifically, the first transistor 1101 and the second transistor 1102 form the first bridge arm of the inverter circuit, the first transistor 1103 and the second transistor 1104 form the second bridge arm, and the first transistor 1105 and the second transistor 1106 form the third bridge arm.

[0086] The motor includes three-phase windings; the input terminals of the three-phase windings include U, V, and W terminals; the inverter circuit includes a signal input terminal and a voltage output terminal; the voltage output terminal of the inverter circuit is connected to the three-phase windings of the motor; the collector of the first transistor 1101 is connected to the positive terminal of the DC power supply; the emitter of the first transistor 1101 is connected to the U terminal of the motor; the collector of the second transistor 1102 is connected to the U terminal of the motor; the emitter of the first transistor 1101 is connected to the negative terminal of the DC power supply; the collector of the first transistor 1103 is connected to the positive terminal of the DC power supply; the emitter of the first transistor 1103 is connected to the V terminal of the motor.

[0087] The collector of the second transistor 1104 is connected to the V terminal of the motor; the emitter of the second transistor 1104 is connected to the negative terminal of the DC power supply; the collector of the first transistor 1105 is connected to the positive terminal of the DC power supply; the emitter of the first transistor 1105 is connected to the W terminal of the motor; the collector of the second transistor 1106 is connected to the W terminal of the motor; the emitter of the second transistor 1106 is connected to the negative terminal of the DC power supply.

[0088] The anode of the first diode 1107 is connected to the emitter of the first transistor 1101; the cathode of the first diode 1107 is connected to the collector of the first transistor 1101; the anode of the second diode 1108 is connected to the emitter of the second transistor 1102; the cathode of the second diode 1108 is connected to the collector of the second transistor 1102; the anode of the third diode 1109 is connected to the emitter of the first transistor 1103; the cathode of the third diode 1109 is connected to the collector of the first transistor 1103. The anode of the fourth diode 1110 is connected to the emitter of the second transistor 1104; the cathode of the fourth diode 1110 is connected to the collector of the second transistor 1104; the anode of the fifth diode 1111 is connected to the emitter of the first transistor 1105; the cathode of the fifth diode 1111 is connected to the collector of the first transistor 1105; the anode of the sixth diode 1112 is connected to the emitter of the second transistor 1106; the cathode of the sixth diode 1112 is connected to the collector of the second transistor 1106.

[0089] The gates of the first transistor 1101, the second transistor 1102, the first transistor 1103, the second transistor 1104, the first transistor 1105, and the second transistor 1106 serve as the signal input terminals of the inverter circuit. The signal input terminals of the inverter circuit are connected to the signal output terminals of the safety torque control circuit and also to the signal output terminals of the star-sealed logic circuit.

[0090] Figure 12 The schematic diagram illustrates the structure of a synchronous motor sealing star control device for an elevator according to another embodiment of the present invention.

[0091] like Figure 12 As shown, the motor digital control processor sends a brake enable signal to the motor drive circuit. Based on this signal, the motor drive circuit outputs a brake drive signal to the gate of the IGBT in the inverter circuit of the frequency converter. This IGBT absorbs energy during elevator braking. The motor digital control processor forwards the elevator operating status signal to the star-sealing logic circuit via a star-sealing enable signal. For example, when the elevator operating status signal indicates normal operation, the star-sealing enable signal outputs a low level, and the motor drive circuit sends a second motor drive signal to the first and second transistors of the inverter circuit. When the elevator operating status signal indicates that the elevator is stopped or braking, the star-sealing enable signal outputs a high level, and the motor drive circuit sends a second motor drive signal to the second transistor of the inverter circuit. The U, V, and W terminals of the motor are connected to the midpoints of the bridge arms of the inverter circuit. Figure 12In the diagram, Vbus+ represents the positive terminal of the DC bus, and Vbus- represents the negative terminal. The frequency converter includes an inverter circuit and a rectifier circuit. The rectifier circuit converts AC power to DC power, and the DC power is then converted back to AC power to supply power to the motor. BOTx represents the motor drive signal input to the second transistor, TOPx represents the motor drive signal input to the first transistor, and x represents the bridge arm number. For example, BOT1 represents the motor drive signal input to the second transistor of the first bridge arm.

[0092] According to an embodiment of the present invention, the motor control digital processor is further configured to output a preset drive pulse signal to the star-sealing circuit; the star-sealing circuit is configured to provide a second motor drive signal to the inverter circuit according to the preset drive pulse signal when the elevator running status signal indicates that the elevator is in normal operating condition; wherein, the inverter circuit is configured to turn on the first transistor or the second transistor in response to the second motor drive signal, or turn off the first transistor or the second transistor, so that the inverter circuit outputs a preset AC power to the motor so that the motor drives the elevator car to run.

[0093] The present invention also provides an elevator, which includes the above-mentioned synchronous motor star control device for elevators.

[0094] Figure 13 The schematic diagram illustrates the waveform of the sealing signal when the elevator stops normally according to an embodiment of the present invention.

[0095] like Figure 13 As shown, under normal circumstances, when the elevator stops, the three-phase windings of the motor need to be short-circuited to limit the unexpected speed of the car without affecting the safety torque shut-off. After the elevator stops, the optocoupler of the switching circuit of the safety torque control circuit is de-conductive, causing each MOSFET in each logic adjustment circuit to conduct, resulting in a low-level output from the safety torque control circuit. This causes the input signals BOTxPWM(IN) and TOPxPWM(IN) of the star-sealing logic circuit to become 0 (low level). At this time, the motor control digital processor enables the electronic star-sealing signal (EDB-ENABLE), changing from a low level (0) to a high level (1).

[0096] When the electronic star-sealing signal level is 0 (low level), the AND gate output of the third AND logic circuit outputs a high level, and the AND gate output of the fourth AND logic circuit outputs a low level. When the first AND gate input of each first AND logic circuit is low, the AND gate output outputs a low level; when the first AND gate input of each first AND logic circuit is high, the AND gate output outputs a high level. When the first AND gate input of each second AND logic circuit is low, the AND gate output outputs a low level. When the first OR gate input is low, and the second OR gate input is low, the OR gate output outputs a low level. When the first AND gate input of each second AND logic circuit is high, the AND gate output outputs a high level. When the first OR gate input is high, and the second OR gate input is low, the OR gate output outputs a high level.

[0097] When the electronic star-sealing signal level is 1 (high), the AND gate output of the third AND logic circuit outputs a low level, and the AND gate output of the fourth AND logic circuit outputs a high level. When the first AND gate input of each first AND logic circuit is low, its output is low; when the first AND gate input of each first AND logic circuit is high, its output is low. When the first AND gate input of each second AND logic circuit is low, its output is low. When the first OR gate input is low and the second OR gate input is high, its output is high. When the first AND gate input of each second AND logic circuit is high, its output is low. When the first OR gate input is high and the second OR gate input is high, its output is high.

[0098] After the dead time Td (determined by the internal RC), the output signal BOTxPWM(OUT) of the star-sealed logic circuit changes from low level 0 to high level 1. The output signal TOPxPWM(OUT) of the star-sealed logic circuit remains low level 0. When BOTxPWM(OUT) becomes high level, the motor drive circuit amplifies the power of the BOTxPWM(OUT) signal, causing the lower bridge arm of the inverter circuit of the frequency converter to conduct. When TOPxPWM(OUT) remains low level 0, the motor drive circuit amplifies the power of the TOPxPWM(OUT) signal, causing the upper bridge arm of the inverter circuit of the frequency converter to turn off.

[0099] When BOTxPWM(OUT) is high (1), the lower bridge arm of the inverter circuit of the frequency converter is turned on, realizing the short circuit of the three-phase winding of the motor and playing a star-blocking role. When TOPxPWM(OUT) is low (0), the upper bridge arm of the inverter circuit of the frequency converter remains off, maintaining the safe torque cancellation (ST0) function.

[0100] Figure 14 The schematic diagram illustrates the waveform of the sealing star signal during emergency braking of an elevator according to an embodiment of the present invention.

[0101] like Figure 14 As shown, in emergency braking, the BOTxPWM(IN) and TOPxPWM(IN) drive pulse signals operate normally. The elevator needs to short-circuit the three-phase windings of the motor when the speed is ≤0.05m / s. At this time, the motor control digital processor enables the electronic star-sealing signal, changing it from a low level (0) to a high level (1). It is necessary to prevent damage to BOTxPWM(OUT) and TOPxPWM(OUT) due to IGBT shoot-through caused by the electronic star-sealing signal. The star-sealing logic circuit integrates an RC delay circuit.

[0102] When the elevator brakes in an emergency, the internal input signals BOTxPWM(IN) and TOPxPWM(IN) of the star-sealing logic circuit operate normally, emitting a PWM wave. At this time, the motor control digital processor enables the electronic star-sealing signal DB_ENABLE, changing it from a low level (0) to a high level (1). The internal output signal TOPxPWM(OUT) of the star-sealing logic circuit changes from a high level (1) to a low level (0). The internal output signal BOTxPWM(OUT) of the star-sealing logic circuit also outputs a low level, such as... Figure 14 The dead time indicated in the code is used to implement the STO function within this dead time. After the Td dead time (the time is determined by the internal RC), TOPxPWM(OUT) remains low, and BOTxPWM(OUT) changes from 0 (low level) to 1 (high level), which turns on the second transistor of the lower bridge arm, short-circuits the three-phase windings of the motor, and prevents the IGBT from shoot-through between the upper and lower bridges.

[0103] like Figure 14 As shown, during dead time and in the star-sealed state, TOPxPWM(OUT) is low, keeping the first transistor of the upper bridge arm off. During dead time, BOTxPWM(OUT) also outputs a low level, at which point the STO function takes effect. Therefore, even though TOPxPWM(IN) and BOTxPWM(IN) are still outputting PWM waves normally, the EDB_ENABLE signal, through the RC circuit, replaces the function of the STO logic unit, completing both the STO and electronic star-sealing functions.

[0104] The function of STO (Stop-Off Transmission) is to disconnect the inverter from the motor when the elevator stops or undergoes emergency braking. This is achieved by turning off the upper and lower bridge arm transistors of the inverter. The function of electronic star-stop is to short-circuit the three-phase windings of the motor when the elevator stops or undergoes emergency braking. This is achieved by turning on the second transistor of the lower bridge arm of the inverter circuit.

[0105] The synchronous motor star-sealing control device for elevators provided by this utility model uses the existing power module of the frequency converter. In the safe torque off state, it limits the speed of the car from accidental movement by short-circuiting the three-phase windings of the motor.

[0106] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the present invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present invention, and all such substitutions and modifications should fall within the scope of the present invention.

Claims

1. A synchronous motor star-connection control device for an elevator, characterized by The device comprises a motor control digital processor and a starve circuit; The motor control digital processor is configured to forward an elevator operation state signal to the starve circuit; The starve circuit is configured to provide a first motor drive signal to an inverter circuit according to a preset pulse signal when the elevator operation state signal indicates that the elevator is in a stop state or a braking state; The inverter circuit is configured to turn off a first transistor and turn on a second transistor in response to the first motor drive signal, so that an input end of a winding of a motor connected to the inverter circuit is short-circuited, so that the motor generates a braking torque, wherein the first transistor is an upper bridge arm of the inverter circuit, and the second transistor is a lower bridge arm of the inverter circuit.

2. The synchronous motor star-delta control device for an elevator according to claim 1, characterized by, The starve circuit comprises a safety torque control circuit, a starve logic circuit and a motor drive circuit; The safety torque control circuit comprises a control signal input end and a control signal output end; the starve logic circuit comprises a starve enable signal input end, a starve signal input end and a starve signal output end; and the motor drive circuit comprises a logic signal input end and a drive signal output end; The control signal input end is connected to a first signal output end of the motor control digital processor; the control signal output end is connected to the starve signal input end; the starve enable signal input end is connected to a second signal output end of the motor control digital processor; the starve signal output end is connected to the logic signal input end; and the drive signal output end is connected to a gate of a transistor included in the inverter circuit; The safety torque control circuit is configured to output a set pulse signal when the elevator operation state signal indicates that the elevator is in the stop state or the braking state; The starve logic circuit is configured to adjust the set pulse signal to the preset pulse signal when the elevator operation state signal indicates that the elevator is in the stop state or the braking state; The motor drive circuit is configured to output a first motor drive signal according to the preset pulse signal.

3. The synchronous motor star-delta control device for an elevator according to claim 2, characterized by, The starve logic circuit comprises an enable control circuit, a plurality of first logic and circuits and a plurality of logic control circuits; The enable control circuit comprises an enable input end, a first enable output end and a second enable output end; and the enable input end serves as the starve enable signal input end; Each of the first logic and circuits comprises a first AND gate input end, a second AND gate input end and an AND gate output end; and each of the logic control circuits comprises a first logic input end, a second logic input end, a third logic input end and a logic output end; The starve signal input end comprises the first AND gate input end and the first logic input end of the first logic and circuit; and the starve signal output end comprises the AND gate output end and the logic output end of the first logic and circuit; The first enable output end is connected to the second logic input end and the second AND gate input end of the first logic and circuit respectively; and the second enable output end is connected to the third logic input end. The logic output end is connected with the second transistor; the AND gate output end of the first logic AND circuit is connected with the first transistor.

4. The synchronous motor star-delta control device for an elevator according to claim 3, characterized by Each of the logic control circuits comprises a second logic AND circuit and a logic OR circuit; The second logic AND circuit comprises a first AND gate input end, a second AND gate input end and an AND gate output end; the logic OR circuit comprises a first OR gate input end, a second OR gate input end and an OR gate output end; The first AND gate input end of the second logic AND circuit serves as the first logic input end; the second AND gate input end of the second logic AND circuit serves as the second logic input end; the second OR gate input end serves as the third logic input end; and the OR gate output end serves as the logic output end; The AND gate output end of the second logic AND circuit is connected with the first OR gate input end.

5. The synchronous motor star-delta control device for an elevator according to claim 3, characterized by The enable control circuit comprises a delay resistor, a delay capacitor, a third logic AND circuit, a fourth logic AND circuit and a plurality of logic NOT circuits; The third logic AND circuit comprises a first AND gate input end, a second AND gate input end and an AND gate output end; the fourth logic AND circuit comprises a first AND gate input end, a second AND gate input end and an AND gate output end; each of the logic NOT circuits comprises a NOT gate input end and a NOT gate output end; and the plurality of logic NOT circuits comprises a first logic NOT circuit, a second logic NOT circuit and a third logic NOT circuit; The AND gate output end of the third logic AND circuit serves as a first enable output end; the AND gate output end of the fourth logic AND circuit serves as a second enable output end; and the NOT gate input end of the first logic NOT circuit serves as the enable input end; The NOT gate input end of the first logic NOT circuit is connected with the first AND gate input end of the fourth logic AND circuit; the NOT gate output end of the first logic NOT circuit is connected with the first AND gate input end of the third logic AND circuit and one end of the delay resistor respectively; the other end of the delay resistor is connected with one end of the delay capacitor and the NOT gate input end of the second logic NOT circuit respectively; the NOT gate output end of the second logic NOT circuit is connected with the second AND gate input end of the fourth logic AND circuit and the NOT gate input end of the third logic NOT circuit respectively; the NOT gate output end of the third logic NOT circuit is connected with the second AND gate input end of the third logic AND circuit; and the other end of the delay capacitor is grounded.

6. The synchronous motor star-delta control device for an elevator according to claim 2, characterized by The safety torque control circuit comprises a plurality of logic adjustment circuits and a fault logic circuit; The fault logic circuit comprises a fault signal input end and a fault signal output end; and each of the logic adjustment circuits comprises a pulse signal input end, a fault signal input end and a pulse signal output end; The control signal input end comprises the pulse signal input end and the fault signal input end; and the control signal output end comprises the pulse signal output end and the enable signal output end; The fault signal output end is connected with the fault signal input end.

7. A synchronous motor star-delta control device for an elevator according to claim 6, characterized in that Each of the logic adjustment circuits comprises a resistor and a plurality of MOS transistors; one end of the resistor serves as the pulse signal input end; the other end of the resistor is connected with the source of each of the MOS transistors; and the drain of each of the MOS transistors is connected with the ground. The pulse signal output end comprises a source of each MOS tube; The fault logic circuit is connected with a gate of each MOS tube.

8. The synchronous motor star-delta control device for an elevator according to claim 6, characterized by, The fault logic circuit comprises a plurality of switch circuits; Each switch circuit comprises a switch resistor and an optocoupler; The optocoupler comprises a first end, a second end, a third end and a fourth end; the fault signal input end comprises a first signal input end and a second signal input end; The first signal input end is connected with one end of the switch resistor; the other end of the switch resistor is connected with the first end of the optocoupler; the second signal input end is connected with the second end of the optocoupler; the third end is connected with the ground; the control signal output end comprises the fourth end.

9. The synchronous motor star-delta control device for an elevator according to claim 1, characterized by, The motor control digital processor is further configured to output a preset drive pulse signal to the starve circuit; The starve circuit is configured to provide a second motor drive signal to the inverter circuit according to the preset drive pulse signal when the elevator operation state signal indicates that the operation state of the elevator is a normal operation state; The inverter circuit is configured to turn on or turn off the first transistor or the second transistor in response to the second motor drive signal, so that the inverter circuit outputs a preset alternating current to the motor, so that the motor drives the elevator car to operate.

10. An elevator, characterized by Comprise: The synchronous motor starve control device for the elevator according to any one of claims 1 to 9.

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